Table of Contents
Advertisement
Quick Links
CMS80F661x 数据手册
CMS80F751x Reference Manual
Enhanced Flash 8-bit 1T 8051- Microcontroller
Rev. 1.05
Please note the following regarding the CMS Intellectual Property Policy
＊China-Micro Semiconductor Co. Ltd has applied for a patent and enjoys absolute legal rights. The patents relating to MCU or
other products of China-Micro Semiconductor Co., Ltd. have not been authorized for use. Any company, organization or individual
that improperly infringes the patent rights of China-Micro Semiconductor Co., Ltd., and China-Micro Semiconductor Co., Ltd. will
take all possible legal actions to stop the infringer's improper infringement, and recover the losses suffered of China-Micro
Semiconductor Co., Ltd due to the infringement, or the illegal interests of the infringer.
＊The name and logo of China-Micro Semiconductor Co., Ltd. are registered trademarks of China-Micro Semiconductor Co., Ltd.
＊China-Micro Semiconductor Co., Ltd reserves the right to further explain the improvements in reliability, functionality and design of the
products in the specification. And China-Micro Semiconductor Co., Ltd is not responsible for the use of the specifications. The application
mentioned in the article is only for illustrative purposes, and China-Micro Semiconductor Co., Ltd does not ensure or represent that these
applications may be applied without further modifications, and its products are not recommended for use in areas that may be hazardous
to others due to malfunction or other reasons. China-Micro Semiconductor Co., Ltd's products are not authorized for use as a critical
device in life-saving, life-sustaining devices or systems. China-Micro Semiconductor Co., Ltd has the right to modify the product without
prior notice. If you want to get the latest information, please refer to our website http://www.mcu.com.cn.
www.mcu.com.cn
1 / 273
Rev.
0.10
Advertisement
Table of Contents
Related Manuals for Cmsemicon CMS80F751 Series
Summary of Contents for Cmsemicon CMS80F751 Series
-
Page 1: Contents Cms80F751X Reference Manual
CMS80F661x 数据手册 CMS80F751x Reference Manual Enhanced Flash 8-bit 1T 8051- Microcontroller Rev. 1.05 Please note the following regarding the CMS Intellectual Property Policy ＊China-Micro Semiconductor Co. Ltd has applied for a patent and enjoys absolute legal rights. The patents relating to MCU or other products of China-Micro Semiconductor Co., Ltd. -
Page 2: Table Of Contents
CMS80F751x Reference Manual Contents CMS80F751x Reference Manual ..................... 1 Contents ........................... 2 1. Central Processing Unit（CPU） ................... 13 Reset Vector（0000H） ............................13 BOOT Partition ................................13 Accumulator（ACC） ..............................15 B Register（B） ................................ 15 Stack Pointer Register（SP） ........................... 15 Data Pointer Register（DPTR0/DPTR1）......................... 15 Data Pointer Selection Register（DPS）... - Page 3 CMS80F751x Reference Manual 5.4.1 Sleep And Wake-Up .............................. 48 5.4.2 Wake Waiting Status ............................. 48 5.4.3 Sleep And Wake-Up Time ............................. 49 5.4.4 Reset Operation During Sleep ..........................49 5.4.5 Sleep Power Consumption In Debug Mode ......................49 5.4.6 Sleep Mode Application Example .......................... 50 6.
- Page 4 CMS80F751x Reference Manual 7.2.2 Port Reuse Function Configuration Register ......................73 7.2.3 Port Input Function Allocation Register ......................... 74 7.2.4 Communication Input Function Allocation Register ....................76 7.2.5 External Port Interrupt Control Register ........................ 77 7.2.6 Reuse Functions Application Notes ........................78 8.
- Page 5 CMS80F751x Reference Manual 10.2.7 Timer2 Compare/Capture Channel1 Register High 8-Bit CCH1 ................99 10.2.8 Timer2 Compare/Capture Channel2 Register Low 8-Bit CCL2 ................99 10.2.9 Timer2 Compare/Capture Channel2 Register High 8-Bit CCH2 ................99 10.2.10 Timer2 Compare/Capture Channel3 Register Low 8-Bit CCL3 ................99 10.2.11 Timer2 Compare/Capture Channel3 Register High 8-Bit CCH3 ................
- Page 6 CMS80F751x Reference Manual 12. LSE_Timer ........................123 12.1 Overview ................................. 123 12.2 Related Registers ..............................123 12.2.1 LSE Timer Data Register Low 8-bit LSECRL ...................... 123 12.2.2 LSE Timer Data Register High 8-bit LSECRH ..................... 123 12.2.3 LSE Timer Control Register LSECON ......................... 124 12.3 Interrupt And Sleep Wake-up ..........................
- Page 7 CMS80F751x Reference Manual 17.2.1 BUZZER Control Register BUZCON ........................140 17.2.2 BUZZER Frequency Control Register BUZDIV ....................140 17.3 Function Description ..............................141 18. Enhanced PWM Module ....................142 18.1 Overview ................................. 142 18.2 Characteristic ................................142 18.3 Pin Configuration ..............................143 18.4 Function Description ..............................
- Page 8 CMS80F751x Reference Manual 18.6.9 PWM Up Compare Interrupt Flag Register PWMUIF ..................162 18.6.10 PWM Down Compare Interrupt Flag Register PWMDIF ..................162 19. Hardware LCD Driver ..................... 163 19.1 Overview ................................. 163 19.2 Characteristic ................................163 19.3 Related Register ..............................164 19.3.1 LCD Control Register LCDCON0 ........................
- Page 9 CMS80F751x Reference Manual 21.1 Overview ................................. 184 21.2 SPI Port Configuration ............................. 185 21.3 SPI Hardware Description ............................186 21.4 SPI Related Register ............................... 187 21.4.1 SPI Control Register SPCR..........................187 21.4.2 SPI Data Register SPDR ............................ 188 21.4.3 Slave Select Control Register SSCR ........................188 21.4.4 SPI State Register SPSR ............................
- Page 10 CMS80F751x Reference Manual 23.2 UARTn Port Configuration ............................214 23.3 UARTn Baud Rate ..............................215 23.3.1 Baud Rate Clock Source ............................. 215 23.3.2 Baud Rate Calculation ............................215 23.3.3 Baud Rate Deviation ............................216 23.4 UARTn Registers ..............................218 23.4.1 UART0/1 Baud Rate Selection Register FUNCCR ..................... 218 23.4.2 UARTn Buffer Register SBUFn ...........................
- Page 11 CMS80F751x Reference Manual 24.6.12 AD Comparator Data Register ADCMPL ......................236 24.6.13 AD Reference Voltage Control Register ......................237 24.7 ADC Interrupt ................................238 24.7.1 Interrupt Mask Register EIE2 ..........................238 24.7.2 Interrupt Priority Control Register EIP2 ....................... 239 24.7.3 External Interrupt Flag Bit Register EIF2 ......................240 25.
- Page 12 CMS80F751x Reference Manual 29.3 Function Description ..............................261 30. Unique ID（UID） ......................262 30.1 Overview ................................. 262 30.2 UID Register Description ............................262 31. User Configuration ......................265 32. Online Programming And Debugging ................267 32.1 Online Programming Mode............................267 32.2 Online Debug Mode ..............................
-
Page 13: Central Processing Unit（Cpu
CMS80F751x Reference Manual 1. Central Processing Unit（CPU） This series is a microcontroller with 8-bit 8051 frame structure. The CPU is the core component of the microcontroller, which is composed of arithmetic units, controllers, and special register groups. The arithmetic unit module mainly implements data arithmetic and logic operations, bit variable processing and data transfer operations;... - Page 14 CMS80F751x Reference Manual BOOT Control Register（BOOTCON） F691H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 BOOTCON Reset value BOOT area control bit (this register can only be written when the chip is configured as Bit7~Bit0 D<7:0>: BOOT_1K/BOOT_2K/BOOT_4K); If you switch from APROM area to BOOT area, you need to write 0x55 to it, then perform 0x55= software reset or generate watchdog reset;...
-
Page 15: Accumulator（Acc
CMS80F751x Reference Manual 1.3 Accumulator（ACC） ALU is an 8Bit wide arithmetic logic unit, and all the mathematics and logic operations of the MCU are completed through it. It can add, subtract, shift and logic operations on data; ALU also controls the status bit (in the PSW status register) to indicate the status of the result of the operation. -
Page 16: Data Pointer Selection Register（Dps
CMS80F751x Reference Manual 1.7 Data Pointer Selection Register（DPS） Data Pointer Selection Register DPS 0x86 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset value Bit7~Bit6 ID<1:0>: Self-subtract/ self-add function selection. DPTR0 add 1 or DPTR1 add 1; DPTR0 minus 1 or DPTR1 add 1; DPTR0 add 1 or DPTR1 minus 1;... -
Page 17: Program Counter（Pc
CMS80F751x Reference Manual Select Bank2; Select Bank3. Bit2 Overflow Flag; Arithmetic or logical operation has overflow; Arithmetic or logical operation has no overflow. Bit1 Reserved, must be 0. Bit0 Parity; The highest bit of the result is carried. The highest bit of the result does not carry. 1.9 Program Counter（PC）... -
Page 18: Memory And Register Map
CMS80F751x Reference Manual 2. Memory And Register Map This series of micro-controllers has the following types of memories: ◆ Maximum 32KB FLASH program memory (shared by APROM area and BOOT area). ◆ Maximum 1KB non-volatile data memory (Data FLASH). ◆ Maximum 256B general-purpose internal data memory (RAM). -
Page 19: Non-Volatile Data Memory Data Flash
CMS80F751x Reference Manual 2.2 Non-volatile Data Memory Data FLASH The non-volatile data memory Data FLASH can be used to store important data such as constant data, calibration data, protection and safety-related information. The data stored in this area has the characteristic that the data will not be lost when the chip is powered off or suddenly or unexpectedly. -
Page 20: General Data Register Ram
CMS80F751x Reference Manual 2.3 General Data Register RAM The internal data memory is divided into 3 parts: low 128Bytes, high 128Bytes, and special function register SFR. The structure diagram of RAM space allocation is shown in the figure below: Upper 128bytes Special Function Registers Internal RAM 128bytes... - Page 21 CMS80F751x Reference Manual 80Bytes General Purpose Register 16Bytes Bit Addressable (128Bits) Register Bank3 8Bytes (8Bytes) Register Bank2 8Bytes (8Bytes) Register Bank1 8Bytes (8Bytes) Register Bank0 8Bytes (8Bytes) Rev. 1.05 www.mcu.com.cn...
-
Page 22: General External Data Register Xram
CMS80F751x Reference Manual 2.4 General External Data Register XRAM There is a maximum 2KB XRAM area inside the chip, which is not related to FLASH/RAM. The structure diagram of XRAM space allocation is shown in the figure below: 07FFH XRAM 2 KB （indirect address）... -
Page 23: Special Function Register Table Sfr
CMS80F751x Reference Manual 2.5 Special Function Register Table SFR Special function registers refer to a collection of special-purpose registers, which are essentially on-chip RAM units with special functions, which are discretely distributed in the address range 80H~FFH. Users can perform byte access to them through direct addressing instructions. - Page 24 CMS80F751x Reference Manual The BANK0 register table is as follows: BANK0 0xF8 PCRCDL PCRCDH MLOCK MADRL MADRH MDATA MCTRL 0xF0 I2CSADR I2CSCR I2CSBUF I2CMSA I2CMCR I2CMBUF I2CMTP 0xE8 ADCON2 SCON1 SBUF1 SPCR SPSR SPDR SSCR 0xE0 0xD8 ADCCHS ADRESL ADRESH ADCON1 ADCON0 0xD0...
-
Page 25: External Special Function Register Xsfr
CMS80F751x Reference Manual 2.6 External Special Function Register XSFR XSFR is a special register shared by the address space and XRAM. It mainly includes: port control register and other function control registers. Seeking the address range is as follows: FFFFH XSFR area：4K F000H EFFFH... - Page 26 CMS80F751x Reference Manual Address Registers Register Description F01DH P1SR P1 port slope control register F01EH P1DS P1 port data input selection register F020H P20CFG P20 port configuration register F021H P21CFG P21 port configuration register F022H P22CFG P22 port configuration register F023H P23CFG P23 port configuration register...
- Page 27 CMS80F751x Reference Manual Address Registers Register Description F08EH P16EICFG P16 port interrupt control register F08FH P17EICFG P17 port interrupt control register F090H P20EICFG P20 port interrupt control register F091H P21EICFG P21 port interrupt control register F092H P22EICFG P22 port interrupt control register F093H P23EICFG P23 port interrupt control register...
- Page 28 CMS80F751x Reference Manual Address Registers Register Description F12AH PWM0DIV PWM0 frequency division control register F12BH PWM1DIV PWM1 frequency division control register F12CH PWM2DIV PWM2 frequency division control register F12DH PWM3DIV PWM3 frequency division control register F12EH PWM4DIV PWM4 frequency division control register F12FH PWM5DIV PWM5 frequency division control register...
- Page 29 CMS80F751x Reference Manual Address Registers Register Description F162H PWM23DT PWM2/3 Dead-band Delay Data Register F163H PWM45DT PWM4/5 Dead-band Delay Data Register F164H PWMMASKE PWM Mask Enable Control Register F165H PWMMASKD PWM Mask Data Register F166H PWMFBKC PWM Brake Control Register F167H PWMFBKD PWM Brake Data Register...
- Page 30 CMS80F751x Reference Manual Address Registers Register Description F5E4H UID4 UID<39:32> F5E5H UID5 UID<47:40> F5E6H UID6 UID<55:48> F5E7H UID7 UID<63:56> F5E8H UID8 UID<71:64> F5E9H UID9 UID<79:72> F5EAH UID10 UID<87:80> F5EBH UID11 UID<95:88> F650H LCDSEG0 LCD SEG0 Register F651H LCDSEG1 LCD SEG1 Register F652H LCDSEG2 LCD SEG2 Register...
- Page 31 CMS80F751x Reference Manual Address Registers Register Description F698H PS_SCLK SPI clock input port allocation register F699H PS_MOSI SPI slave input port allocation register F69AH PS_MISO SPI master input port allocation register F69BH PS_NSS SPI chip select input port allocation register F69CH PS_SCL IIC clock input port allocation register...
- Page 32 CMS80F751x Reference Manual Address Registers Register Description F75CH LEDC7DATA0 LED COM7 corresponds to SEG7-SEG0 data register F75DH LEDC7DATA1 LED COM7 corresponds to SEG15-SEG8 data register F75EH LEDC7DATA2 LED COM7 corresponds to SEG19-SEG16 data register F760H LEDCOMEN LED COM7~COM0 enable control register F761H LEDSEGEN0 LED SEG7-SEG0 enable register 0...
-
Page 33: Reset
CMS80F751x Reference Manual 3. Reset The reset time (Reset Time) refers to the time from the chip reset to the chip starting to execute instructions, and its default design value is about 16ms. This time includes the oscillator start-up time and configuration time. This reset time will exist regardless of whether the chip is reset by power-on or other reasons. - Page 34 CMS80F751x Reference Manual Whether the system is a power-on reset can be judged by the PORF (WDCON.6) flag bit. The reset types that can set the PORF flag bit to 1 are: power-on reset, LVR reset, external reset, and CONFIG protection reset. 0x97 Bit7 Bit6...
-
Page 35: External Reset
CMS80F751x Reference Manual 3.2 External Reset External reset refers to the reset signal from the external port (NRST), which resets the chip after being input by the Schmitt trigger. If the NRST pin is held low for more than 16us (three rising edges of the internal LSI clock sampling) during the operating voltage range and stable oscillation, a reset will be requested.After the internal state is initialized and the reset state becomes "1", it takes 16ms to stabilize before the internal RESETB signal becomes "1", and the program starts to execute from the vector address 0000H. -
Page 36: Watchdog Reset (Wdt)
CMS80F751x Reference Manual 3.4 Watchdog Reset (WDT) The watchdog reset is a protection setting for the system. In the normal state, the watchdog timer is cleared by the program. If an error occurs, the system is in an unknown state and the watchdog timer overflows and the system is reset. After the watchdog resets, the system restarts to the normal state. -
Page 37: Software Reset
CMS80F751x Reference Manual 3.5 Software Reset Program software reset can be implemented inside the chip. Software reset can relocate the program flow to reset address 000H, and then run the program again. The user can write the software reset control bit WDCON[7] (SWRST=1) to realize a custom software reset. -
Page 38: Clock Structure
CMS80F751x Reference Manual 4. Clock Structure The clock source of the system clock has 4 types, and the clock source and clock frequency division can be selected through the setting of the system configuration register or the user register. The system clock sources are as follows: ◆... -
Page 39: Related Registers
CMS80F751x Reference Manual 4.2 Related registers 4.2.1 Oscillator Control Register CLKDIV 0x8F Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CLKDIV CLKDIV7 CLKDIV6 CLKDIV5 CLKDIV4 CLKDIV3 CLKDIV2 CLKDIV1 CLKDIV0 Reset Value Frequency division bit of system clock Fsys; Bit7~Bit0 CLKDIV<7:0>: 00H= Fsys=Fsys_pre;... -
Page 40: System Clock Status Register Sckstau
CMS80F751x Reference Manual 101= HSE; 100= HSI; Other= Invalid value, access is forbidden. After the clock source is switched, the system will switch successfully within a few system clock cycles. It is recommended that the program execute 6*NOP before executing other instructions. Modify the instruction sequence required by SCKSEL (no other instructions can be inserted in the middle): TA,#0AAH TA,#055H... -
Page 41: System Clock Monitor Register Scm
CMS80F751x Reference Manual 4.2.4 System Clock Monitor Register SCM F697H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 XT_SCM SCMEN SCMIE SCMIF SCMSTA Reset Value Bit7 SCMEN: The vibration stop detection module is enabled; Enable; Disable. Bit6 SCMIE: Oscillation detection interrupt enable (the interrupt and the LSE timer interrupt share an interrupt entry);... -
Page 42: Function Clock Control Register
CMS80F751x Reference Manual 4.2.5 Function Clock Control Register Watchdog overflow time/timer clock source selection register CKCON 0x8E Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CKCON WTS2 WTS1 WTS0 Reset Value Bit7~Bit5 WTS<2:0>: WDT overflow time selection; 000= *Tsys; 001= *Tsys;... - Page 43 CMS80F751x Reference Manual UART0/1 Baud Rate Selection Register FUNCCR 0x91 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 UART1_CK UART1_CK UART1_CK UART0_CK UART0_CK UART0_CK FUNCCR Reset Value Bit7 Reserved, must be 0. Bit6~Bit4 UART1_CKS<2:0>: Timer clock source selection of UART1; 000= Timer1 overflow clock;...
-
Page 44: System Clock Switching
CMS80F751x Reference Manual 4.3 System Clock Switching The crystal oscillator port of the chip can only be connected with HSE or LSE, so it is forbidden to use the HSE/LSE mutual switching function. When the current chip selects the external HSE clock (config_03H_Bit7=0), it is forbidden to use LSE related functions. -
Page 45: System Clock Monitoring
CMS80F751x Reference Manual 4.4 System Clock Monitoring System clock monitoring (SCM: system clock monitoring) is a monitoring protection circuit designed to prevent the system from not working due to the stop of the crystal oscillator. When HSE/LSE is used as the system clock, once the HSE/LSE clock is detected to stop, the system will force start the HSI clock source. -
Page 46: Power Management
CMS80F751x Reference Manual 5. Power Management The low power modes are divided into 2 types: ◆ IDLE: Idle mode ◆ STOP: Sleep mode When the user is developing the program, it is strongly recommended to use the IDLE and STOP macros to control the system mode of the microcontroller. -
Page 47: Power Monitoring Register Lvdcon
CMS80F751x Reference Manual 5.2 Power Monitoring Register LVDCON The MCU has its own power detection function. If the LVD module is enabled (LVDEN=1) and the voltage monitoring point LVDSEL is set at the same time, when the power supply voltage drops below the LVD setting value, an interrupt will be generated to remind the user. -
Page 48: Stop Sleep Mode
CMS80F751x Reference Manual 5.4 STOP Sleep Mode In this mode, all circuits except LVD module and LSE module are closed (LVD/LSE module must be closed by software), the system is in low power consumption mode, and the digital circuits are not working. 5.4.1 Sleep And Wake-Up After entering the sleep mode, the sleep wake-up function can be turned on (SWE=1 must be set) to wake up the sleep mode. -
Page 49: Sleep And Wake-Up Time
CMS80F751x Reference Manual 5.4.3 Sleep And Wake-Up Time The total wake-up time of using external interrupt to wake up the system is: Power manager stabilization time (200us) + wake-up waiting time The total wake-up time of the system using timed wake-up is: Power manager stabilization time (200us) + wake-up timer timing + wake-up waiting time (The conditions for the time given above are Fsys >... -
Page 50: Sleep Mode Application Example
CMS80F751x Reference Manual 5.4.6 Sleep Mode Application Example Before the system enters the sleep mode, if the user needs to obtain a smaller sleep current, please confirm the status of all I/O. If there are floating I/O ports in the user’s plan, set all the floating ports as output ports to ensure Each input port has a fixed state to avoid that when the I/O is in the input state, the port line level is in an uncertain state and increases the sleep current;... -
Page 51: Interrupt
CMS80F751x Reference Manual 6. Interrupt 6.1 Interruption Overview The chip has 22 interrupt sources and interrupt vectors: Interrupt source Interrupt description Interrupt vector Same priority sequence INT0 External Interruption 0 0-0x0003 Timer0 Timer0 interruption 1-0x000B INT1 External Interruption 1 2-0x0013 Timer1 Timer1 Interruption 3-0x001B... -
Page 52: External Interruption
CMS80F751x Reference Manual 6.2 External Interruption 6.2.1 INT0/INT1 Interruption The chip supports 8051 native INT0, INT1 external interrupt. INT0/INT1(P0 .0 / P0.1) can choose to descend along or low level trigger interrupt, the relevant control register is TCON. INT0 and INT1 occupy two interrupt vectors. 6.2.2 GPIO Interruption Each GPIO pin on the chip supports external interrupts, and can support falling edge/rising edge/double edge interrupts, and the edge trigger type is configured through the PxNEICFG register. -
Page 53: Interruption Register
CMS80F751x Reference Manual 6.4 Interruption Register 6.4.1 Interruption Mask Register Interruption Mask Register IE 6.4.1.1 Interrupt Mask Register IE is a readable and writable register that can be operated by bit. When an interrupt condition occurs, the interrupt flag will be set, regardless of the corresponding interrupt enable bit or the state of the global enable bit EA (in the IE register). -
Page 54: Interruption Mask Register Eie2
CMS80F751x Reference Manual Interruption Mask Register EIE2 6.4.1.2 0xAA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIE2 SPIIE I2CIE WDTIE ADCIE PWMIE Reset Value Bit7 SPIIE: SPI interrupt enable; Enable SPI interrupt; Disable SPI interrupt; Bit6 I2CIE: C interrupt enable; Enable I C interrupt;... -
Page 55: Timer2 Interruption Mask Register T2Ie
CMS80F751x Reference Manual Timer2 Interruption Mask Register T2IE 6.4.1.3 0xCF Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T2IE T2OVIE T2EXIE T2C3IE T2C2IE T2C1IE T2C0IE Reset Value Bit7 T2OVIE: Timer2 overflow interrupt enable; Enable interrupt; Disable interrupt. Bit6 T2EXIE: Timer2 external load interrupt enable; Enable interrupt;... -
Page 56: P1 Port Interrupt Control Register P1Extie
CMS80F751x Reference Manual P1 Port Interrupt Control Register P1EXTIE 6.4.1.5 0xAD Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P1EXTIE P17IE P16IE P15IE P14IE P13IE P12IE P11IE P10IE Reset Value Bit7~Bit0 P1iIE: P1i port interrupt enable（i=0-7）; Allow interrupt; Prohibit interrupt. P2 Port Interrupt Control Register P2EXTIE 6.4.1.6 0xAE... -
Page 57: Interrupt Priority Control Register
CMS80F751x Reference Manual 6.4.2 Interrupt Priority Control Register Interrupt Priority Control Register IP 6.4.2.1 Interrupt priority control register IP is a readable and writable register that can be operated bit by bit. 0xB8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset Value Bit7... -
Page 58: Interrupt Priority Control Register Eip1
CMS80F751x Reference Manual Interrupt Priority Control Register EIP1 6.4.2.2 0xB9 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP1 PACMP Reset Value Bit7 PACMP: Analog comparator interrupt priority control; Set to high level interrupt; Set to low level interrupt. Bit6 Reserved, must to be 0. -
Page 59: Interrupt Priority Control Register Eip3
CMS80F751x Reference Manual Set to low level interrupt. Bit3 PPWM: PWM interrupt priority control; Set to high level interrupt; Set to low level interrupt. Bit2 Reserved, must to be 0. Bit1 PT4: TIMER4 interrupt priority control; Set to high level interrupt; Set to low level interrupt. -
Page 60: Interrupt Flag Bit Register
CMS80F751x Reference Manual 6.4.3 Interrupt Flag Bit Register Timer0/1、INT0/1 Interrupt Flag Bit Register TCON 6.4.3.1 0x88 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TCON Reset Value Bit7 TF1: Timer1 counter overflow interrupt flag; Timer1 counter overflow, hardware automatically cleared when entering the interrupt service program, or software cleared;... -
Page 61: Timer2 Interrupt Flag Bit Register T2If
CMS80F751x Reference Manual Timer2 Interrupt Flag Bit Register T2IF 6.4.3.2 0xC9 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T2IF T2EXIF T2C3IF T2C2IF T2C1IF T2C0IF Reset Value Bit7 TF2: Timer2 counter overflow interrupt flag; Timer2 counter overflow, which needs to be cleared by software; Timer2 counter has no overflow. -
Page 62: Spi Interrupt Flag Bit Register Spsr
CMS80F751x Reference Manual Bit6 I2CIF: C total interrupt indicator position, read only; C produces an interrupt (after clearing the specific interrupt flag bit, this bit is automatically cleared); There was no interruption to the I Bit5 Reserved, must to be 0. Bit4 ADCIF: ADC interrupt flag;... -
Page 63: I2C Master Mode Interrupt Flag Bit Register I2Cmcr/I2Cmsr
CMS80F751x Reference Manual I2C Master Mode Interrupt Flag Bit Register I2CMCR/I2CMSR 6.4.3.5 0xF5 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 I2CMCR RSTS STOP START I2CMSR I2CMIF BUS_BUSY IDLE ARB_LOST DATA_ACK ADDR_ACK ERROR BUSY Reset Value Bit7 RSTS: C active module reset control; Reset the main control module (I C registers of the entire main control module, including I2CMSR);... -
Page 64: Uart Control Register Sconn
CMS80F751x Reference Manual UART Control Register SCONn 6.4.3.7 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCONn UnSM0 UnSM1 UnSM2 UnREN UnTB8 UnRB8 Reset Value BANK0: Register SCON0 address 0x98; register SCON1 address 0xEA. Bit7~Bit2 U1SM0、U1SM1、U1SM2、U1REN、U1TB8、U1RB8: UART1related control bits, see UARTn function description for details Bit1 Tln:... -
Page 65: P2 Interrupt Flag Bit Register P2Extif
CMS80F751x Reference Manual P2 Interrupt Flag Bit Register P2EXTIF 6.4.3.10 0xB6 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P2EXTIF P27IF P26IF P25IF P24IF P23IF P22IF P21IF P20IF Reset Value Bit7~Bit0 P2iIF: P2i port interrupt flag (i=0-7); P2i When the port is interrupted, the software needs to be cleared; P2i There was no interruption to the P2i port. -
Page 66: Clear Operation Of Interrupt Flag
CMS80F751x Reference Manual 6.4.4 Clear Operation Of Interrupt Flag The clearing operation of the interrupt flag bit is divided into the following types: ◆ Hardware is automatically cleared (need to enter the interrupt service program) ◆ Software clear ◆ Read/write operation clear Flag bit automatically cleared by hardware The bits that support automatic hardware clearing are the interrupt flag bits generated by INT0, INT1, T0, T1, T3, and T4. -
Page 67: Special Interrupt Flag Bits In Debug Mode
CMS80F751x Reference Manual 6.4.5 Special Interrupt Flag Bits In Debug Mode The flag bit in the system does not write 0 to the flag bit zero, but needs to read/write other registers to clear the flag bit. In the test state, the Breakpoint is executed, and after the single step operation or stop operation, the emulator will read the value of all registers from the system to the simulation software. -
Page 68: I/O Port
CMS80F751x Reference Manual 7. I/O Port 7.1 GPIO Function The chip has four I/O ports: PORT0、PORT1、PORT2、PORT5. PORTx is a bidirectional port. Its corresponding data direction register is PxTRIS. Setting a position (= 1) of PxTRIS will configure the corresponding pin as an output. Clearing a bit (= 0) of PxTRIS configures the corresponding PORTx pin as an input. -
Page 69: Portx Direction Register Pxtris
CMS80F751x Reference Manual 7.1.2 PORTx Direction Register PxTRIS Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PxTRIS PxTRIS7 PxTRIS6 PxTRIS5 PxTRIS4 PxTRIS3 PxTRIS2 PxTRIS1 PxTRIS0 Reset value Register P0TRIS Address: 0x9A; Register P1TRIS Address: 0xA1; Register P2TRIS Address: 0xA2; Register P5TRIS Address: 0xA5. -
Page 70: Portx Pull-Down Resistor Control Register Pxrd
CMS80F751x Reference Manual 7.1.5 PORTx Pull-Down Resistor Control Register PxRD Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PxRD PxRD7 PxRD6 PxRD5 PxRD4 PxRD3 PxRD2 PxRD1 PxRD0 Reset value Register P0RD Address: F00BH; Register P1RD Address: F01BH; Register P2RD Address: F02BH; Register P3RD Address: F05BH. Bit7~Bit0 PxRD<7:0>: Pull-down resistor control;... -
Page 71: Reuse Function
CMS80F751x Reference Manual 7.2 Reuse Function 7.2.1 Port Reuse Function Table The pins share multiple functions, and each I/O port can be flexibly configured with digital functions or designated analog functions. The digital function of the external input is selected by the port input function allocation register (PS_XX); the multiplexing function is selected by the port multiplexing function configuration register (PxnCFG). - Page 72 CMS80F751x Reference Manual LED port allocation, analog module, CONFIG configuration port are as follows: GPIO(0) ANA(1) CONFIG LEDSEG LEDCOM TOUCH LCDSEG LCDCOM ACMP COM0 COM0 COM1 COM1 COM2 COM2 COM3 COM3 SEG0 COM4 SEG0 COM4 SEG1 COM5 SEG1 COM5 SEG2 COM6 SEG2 COM6...
-
Page 73: Port Reuse Function Configuration Register
CMS80F751x Reference Manual 7.2.2 Port Reuse Function Configuration Register PORTx Function Configuration Registers PxnCFG Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PxnCFG PxnCFG2 PxnCFG1 PxnCFG0 Reset Value Bit7~Bit3 Reserved，all must be 0; Bit2~Bit0 PxnCFG<2:0>: Function configuration, please refer to Reuse Function Explanation; 000= GPIO function;... -
Page 74: Port Input Function Allocation Register
CMS80F751x Reference Manual 7.2.3 Port Input Function Allocation Register There are digital functions with only input status inside the chip, such as INT0/INT1... etc. This type of digital input function has nothing to do with the port reuse status. As long as the assigned port supports digital input (such as RXD0 as a digital input and GPIO as an input function), the port supports this function. - Page 75 CMS80F751x Reference Manual If multiple ports are configured for the same digital function at the same time, the priority will decrease in the order of P00, P01, ..., P54, P55. If P03 and P13 are configured as T1 functions at the same time, the P03 configuration is valid and the P13 configuration is invalid.
-
Page 76: Communication Input Function Allocation Register
CMS80F751x Reference Manual 7.2.4 Communication Input Function Allocation Register When the port is used as a communication port (UART0/UART1/SPI/IIC), there are multiple input ports available, and different port inputs can be selected by setting the following registers. The communication input function port allocation registers are as follows: Register Address... -
Page 77: External Port Interrupt Control Register
CMS80F751x Reference Manual 7.2.5 External Port Interrupt Control Register When using an external interrupt, you need to configure the port as a GPIO function and set the direction as an input port. Or the multiplexing function is an input port (such as RXD0, RXD1), and each port can be configured as a GPIO interrupt function. PORTx external interrupt control register Px EICFG. -
Page 78: Reuse Functions Application Notes
CMS80F751x Reference Manual 7.2.6 Reuse Functions Application Notes Reuse function configuration register is configured as analog function (0x01) by default, and the value of register is set to 0x00 if digital function is used. The input of the reuse function is relatively independent of the external interrupt (GPIO interrupt) of the port and the structure of the port input function. -
Page 79: Watchdog Timer（Wdt
CMS80F751x Reference Manual 8. Watchdog Timer（WDT） 8.1 Overview Watchdog Timer is an on-chip timer with optional overflow time and clock source provided by the system clock Fsys. When the watchdog timer counts to the set overflow value, the watchdog overflow interrupt flag (WDTIF = 1) is generated. If the global interrupt is enabled (EA=1) and the watchdog timer interrupt is enabled (EIE2[5]=1), the CPU will execute the interrupt service program and clear the watchdog counter by writing the register WDCON[0]=1. -
Page 80: Watchdog Overflow Control Register Ckcon
CMS80F751x Reference Manual Note: 1. If WDT in CONFIG is configured to Enable, WDT is always enabled regardless of the state of WDTRE control bits ,and the overflow reset function of WDT is forcibly turned on. 2. If WDT in CONFIG is configured to SOFTWARE CONTROL, WDT can be enabled or disabled by using WDTRE control bits. -
Page 81: Wdt Interrupt
CMS80F751x Reference Manual 8.3 WDT Interrupt The watchdog timer can enable or close interrupts through the EIE2 register, and set high/low priority through the EIP2 register, the interrupt related bits are as follows. 8.3.1 Interruption Mask Register EIE2 0xAA Bit7 Bit6 Bit5 Bit4... -
Page 82: Interrupt Priority Control Register Eip2
CMS80F751x Reference Manual 8.3.2 Interrupt Priority Control Register EIP2 0xBA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP2 PSPI PWDT PADC PPWM Reset value Bit7 PSPI: SPI interrupt priority control; Set to high level interrupt; Set to low level interrupt. Bit6 PI2C: I2C interrupt priority control;... -
Page 83: Timer 0/1（Timer0/1
CMS80F751x Reference Manual 9. Timer 0/1（Timer0/1） Timer 0 is similar to the type and structure of Timer1 and is two 16-bit timers. Timer1 has three modes of operation, and Timer0 has four modes of operation. They provide basic timing and event count operations. -In "Timer mode", the timing register is incremented every 12 or 4 system cycles when the timer clock is enabled. -
Page 84: Related Register
CMS80F751x Reference Manual 9.2 Related Register 9.2.1 Timer0/1 Mode Register TMOD 0x89 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 GATE1 T1M1 T1M0 GATE0 T0M1 T0M0 TMOD Reset value Bit7 Timer1 gate control; GATE1: Enable; Disable. Bit6 CT1: Timer1 timer/counter selection; Counting;... -
Page 85: Timer0/1 Control Register Tcon
CMS80F751x Reference Manual 9.2.2 Timer0/1 Control Register TCON 0x88 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TCON Reset Value Timer1 counter overflow interrupt flag; Bit7 TF1: Timer1 counter overflow, hardware automatically cleared when entering the interrupt service program; Timer1 counter no overflow. Timer1 run control;... -
Page 86: Timer0 Low Bit Data Register Tl0
CMS80F751x Reference Manual 9.2.3 Timer0 Low Bit Data Register TL0 0x8A Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TL07 TL06 TL05 TL04 TL03 TL02 TL01 TL00 Reset value Bit7~ Bit0 TL0<7:0>: Timer0 low bit data register ( also as the counter low byte ) 9.2.4 Timer0 High Bit Data Register TH0 0x8C Bit7... -
Page 87: Function Clock Control Register Ckcon
CMS80F751x Reference Manual 9.2.7 Function Clock Control Register CKCON 0x8E Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CKCON WTS2 WTS1 WTS0 Reset value Bit7~Bit5 WTS<2:0>: WDT overflow time select; 000= 217*Tsys; 001= 218*Tsys; 010= 219*Tsys; 011= 220*Tsys; 100= 221*Tsys; 101= 222*Tsys;... -
Page 88: Timer0/1 Interrupt
CMS80F751x Reference Manual 9.3 Timer0/1 Interrupt Timer0/1 can enable or disable interrupt by IE register, can also set high or low priority by IP register, and the bytes of interrupt are as follows: 9.3.1 Interruption Mask Register IE 0xA8 Bit7 Bit6 Bit5 Bit4... -
Page 89: Interrupt Priority Control Register Ip
CMS80F751x Reference Manual 9.3.2 Interrupt Priority Control Register IP 0xB8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset value Bit7 Reserved, must be 0. Bit6 PS1: UART1 interrupt priority control; Set to high priority interrupt; Set to low priority interrupt. Bit5 PT2: TIMER2 interrupt priority control;... -
Page 90: Timer0/1、Int0/1 Interrupt Flag Register Tcon
CMS80F751x Reference Manual 9.3.3 Timer0/1、INT0/1 Interrupt Flag Register TCON 0x88 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TCON Reset value Bit7 TF1: Timer1 counter overflow interrupt flag; Timer1 counter overflow, hardware automatically cleared when entering the interrupt service program, or software cleared; Timer1 counter no overflow. -
Page 91: Timer0 Operating Mode
CMS80F751x Reference Manual 9.4 Timer0 Operating Mode 9.4.1 T0 -Mode0（13-Bit Timing/Counting Mode） In this mode, the Timer0 is a 13-bit register. When all bits of the counter flip from 1 to 0, the Timer0 interrupt flag TF0 is set to 1. When TCON.4 = 1 and TMOD.3 = 0 or TCON.4 = 1, TMOD.3 = 1, T0G = 1, the counting input enables to the Timer0. (TMOD.3 = 1 is set to allow timer 0 to be controlled by external pin T0G for pulse width measurement ). -
Page 92: T0 -Mode2（8-Bit Auto Reload Timing/Counting Mode
CMS80F751x Reference Manual 9.4.3 T0 -Mode2（8-Bit Auto Reload Timing/Counting Mode） The timer register in Mode 2 is an 8-bit counter (TL0) equipped with automatic reload mode, as shown in the following figure. The overflow from TL0 not only makes TF0 set to 1, but also reloads the content of TH0 from software to TL0. The TH0 value remains unchanged during reloading. -
Page 93: T0 -Mode3（Two Separate 8-Bit Timer/Counters
CMS80F751x Reference Manual 9.4.4 T0 -Mode3（Two Separate 8-Bit Timer/Counters） Timer0 in Mode3 sets TL0 and TH0 to two independent counters. The logic of Timer0 Mode3 is shown below. TL0 can operate as a timer or counter and uses the control bits of Timer0: CT0, TR0, GATE0, and TF0. TH0 can only work as a timer and uses the TR1 and TF1 flags of Timer1 to control the Timer1 interrupt. -
Page 94: Timer1 Operating Mode
CMS80F751x Reference Manual 9.5 Timer1 Operating Mode 9.5.1 T1 -Mode0（13-Bit Timing/Counting Mode） In this mode, Timer1 is a 13-bit register. When all bits of the counter are turned from 1 to 0, the Timer1 interrupt flag TF1 is set 1. When TCON.6 = 1 and TMOD.7 = 0 or when TCON.6 = 1, TMOD.7 = 1 and T1G = 1, count input enablesTimer1. ( TMOD. 7 = 1 is set to allow Timer1 to be controlled by external pin T1G for pulse width measurement ). -
Page 95: T1 -Mode2（8-Bit Auto Reload Timing/Counting Mode
CMS80F751x Reference Manual 9.5.3 T1 -Mode2（8-Bit Auto Reload Timing/Counting Mode） The timer register in Mode2 is an 8-bit counter (TL1) equipped with automatic reload mode, as shown in the following figure. The overflow from TL1 not only makes TF1 set to 1, but also reloads the content of TH1 from software to TL1. The TH1 value remains unchanged during reloading. -
Page 96: Timer 2（Timer2
CMS80F751x Reference Manual 10. Timer 2（Timer2） Timer 2 with additional comparison / capture / reload function is one of the most core peripheral units. It can be used to generate various digital signals and capture events, such as pulse generation, pulse width modulation, pulse width measurement, etc. -
Page 97: Related Register
CMS80F751x Reference Manual 10.2 Related Register 10.2.1 Timer2 Control Register T2CON 0xC8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T2PS I3FR T2R1 T2R0 T2CM T2I1 T2I0 T2CON CAPES Reset value Bit7 T2PS: Timer2 clock prescaler selection; Fsys/24; Fsys/12. Bit6 I3FR: Capture channel0 input single edge selection and compare interrupt time selection;... -
Page 98: Timer2 Low Bit Data Register Tl2
CMS80F751x Reference Manual 10.2.2 Timer2 Low Bit Data Register TL2 0xCC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TL27 TL26 TL25 TL24 TL23 TL22 TL21 TL20 Reset value Bit7~Bit0 TL2<7:0>: Timer 2 low bit data register (also as the counter low byte). 10.2.3 Timer2 High Bit Data Register TH2 0xCD Bit7... -
Page 99: Timer2 Compare/Capture Channel1 Register Low 8-Bit Ccl1
CMS80F751x Reference Manual 10.2.6 Timer2 Compare/Capture Channel1 Register Low 8-Bit CCL1 0xC2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CCL17 CCL16 CCL15 CCL14 CCL13 CCL12 CCL11 CCL10 CCL1 Reset value Bit7~Bit0 CCL1<7:0>: Timer2 compare/capture channel1 register low 8-bit. 10.2.7 Timer2 Compare/Capture Channel1 Register High 8-Bit CCH1 0xC3 Bit7 Bit6... -
Page 100: Timer2 Compare/Capture Channel3 Register High 8-Bit Cch3
CMS80F751x Reference Manual Timer2 Compare/Capture Channel3 Register High 8-Bit CCH3 10.2.11 0xC7 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CCH37 CCH36 CCH35 CCH34 CCH33 CCH32 CCH31 CCH30 CCH3 Reset value Bit7~Bit0 CCH3<7:0>: Timer2 compare/capture channel3 register high 8-bit. Timer2 Compare Capture Control Register CCEN 10.2.12 0xCE Bit7... -
Page 101: Timer2 Interrupt
CMS80F751x Reference Manual 10.3 Timer2 Interrupt Timer2 can enable or close the total interrupt through register IE, and can also set high / low priority through IP register. Timer2 has four types of interruption : Timed overflow interrupt. ◆ ◆ External pin T2EX falling edge interrupt. -
Page 102: Timer2 Interrupt Mask Register T2Ie
CMS80F751x Reference Manual Bit0 EX0: External interrupt 0 enable; Enable external interrupt 0; Disable external interrupt 0; Timer2 Interrupt Mask Register T2IE 10.3.1.2 0xCF Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T2IE T2OVIE T2EXIE T2C3IE T2C2IE T2C1IE T2C0IE Reset value Bit7 T2OVIE: Timer2 overflow interrupt enable;... -
Page 103: Interrupt Priority Control Register Ip
CMS80F751x Reference Manual Interrupt Priority Control Register IP 10.3.1.3 0xB8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset value Bit7 Reserved, must be 0. Bit6 PS1: UART1 interrupt priority control; Set to high priority interrupt; Set to low priority interrupt. Bit5 PT2: TIMER2 interrupt priority control;... -
Page 104: Timer2 Interrupt Flag Register T2If
CMS80F751x Reference Manual Timer2 Interrupt Flag Register T2IF 10.3.1.4 0xC9 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T2IF T2EXIF T2C3IF T2C2IF T2C1IF T2C0IF Reset value Bit7 TF2: Timer2 counter overflow interrupt flag; Timer2 counter overflow, which needs to be cleared by software; Timer2 counter has no overflow. -
Page 105: Timer Interrupt
CMS80F751x Reference Manual 10.3.2 Timer Interrupt The timer interrupt enable bit is set by the register T2IE[7], and the interrupt flag bit is checked by the register T2IF[7]. When the Timer2 timer overflows, the timer overflow interrupt flag bit TF2 will be set.. 10.3.3 External Trigger Interrupt The falling edge of the external pin T2EX triggers the interrupt enable bit by register T2IE[6], and the interrupt flag bit is viewed by register T2IF[6]. -
Page 106: Timer2 Function Description
CMS80F751x Reference Manual 10.4 Timer2 Function Description Timer2 is a 16-bit up-counting timer whose clock source comes from the system clock. Timer2 can be configured with the following functional modes: Timing mode. ◆ ◆ Reload mode. ◆ Gate control timing mode. ◆... -
Page 107: Gate Control Timing Mode
CMS80F751x Reference Manual 10.4.3 Gate Control Timing Mode When Timer2 is used as a gate control timer function, the external input pin T2 is used as the gated input of Timer2. If the T2 pin is high, the internal clock input is gated to the timer. T2 pin is low to stop counting. This function is often used to measure pulse width. -
Page 108: Compare Mode0
CMS80F751x Reference Manual Compare Mode0 10.4.5.1 In mode 0, when the timer count is equal to the compare register.an output signal changes from low to high. It goes back to a low level on timer overflow. Figure below shows a functional diagram of a port register in compare mode 0. The compare output channel is directly controlled by two events: timer overflow and compare operation. -
Page 109: Compare Mode1
CMS80F751x Reference Manual Compare Mode1 10.4.5.2 In comparison mode 1, it is usually used when the output signal is independent of the constant signal period and the software adaptively determines the output signal jump. If mode 1 is enabled, the software will write to the corresponding output register of the CCx port, and the new value will not appear on the output pin until the next comparison match occurs. -
Page 110: Capture Mode
CMS80F751x Reference Manual 10.4.6 Capture Mode Each of the four 16-bit compare/capture registers {RLDH, RLDL}, {CCH1, CCL1}, {CCH2, CCL2}, {CCH3, CCL3} can be used to latch the current 16-bit value of the Timer 2 registers {TH2, TL2} . Two different modes are provided for this function. In mode 0, an external event latches Timer 2 contents to a dedicated capture register. -
Page 111: Capture Mode1
CMS80F751x Reference Manual Capture Mode1 10.4.6.2 In capture mode1, the capture operation event is the execution of low byte instructions that write the capture register. The write register signal ( for example, write RLDL ) starts the capture operation, and the write value is not related to this function. Once the write instruction is executed, the contents of Timer2 are locked into the corresponding capture register. -
Page 112: Timer 3/4（Timer3/4
CMS80F751x Reference Manual 11. Timer 3/4（Timer3/4） The Timer3/4 is similar to the Timer0/1, which is two 16-bit timers. Timer3 has four working modes, Timer4 has three working modes. Compared with Timer0/1, Timer3/4 only provides timing operation. When the timer is started, the register value increases every 12 or 4 system cycles. 11.1 Overview Timer3 and Timer4 are composed of two 8-bit registers {TH3, TL3} and {TH4, TL4}, respectively. -
Page 113: Related Register
CMS80F751x Reference Manual 11.2 Related Register 11.2.1 Timer3/4 Control Register T34MOD 0xD2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T4M1 T4M0 T3M1 T3M0 T34MOD Reset value Timer4 run control; Bit7 TR4: Timer4 start; Timer4 closes. Timer4 clock selection; Bit6 T4M: Fsys/4;... -
Page 114: Timer3 High Bit Data Register Th3
CMS80F751x Reference Manual 11.2.3 Timer3 High Bit Data Register TH3 0xDB Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TH37 TH36 TH35 TH34 TH33 TH32 TH31 TH30 Reset value Bit7~Bit0 TH3<7:0>: Timer3 high 8-bit data register(also as timer high byte). 11.2.4 Timer4 Low Bit Data Register TL4 0xE2 Bit7... -
Page 115: Timer3/4 Interrupt
CMS80F751x Reference Manual 11.3 Timer3/4 Interrupt The Timer3/4 can enable or disable the interrupt through the EIE2 register, and the high/low priority level can be set through the EIP2 register. The interrupt correlation bits are as follows : 11.3.1 Interrupt Mask Register EIE2 0xAA Bit7 Bit6... -
Page 116: Interrupt Priority Control Register Eip2
CMS80F751x Reference Manual 11.3.2 Interrupt Priority Control Register EIP2 0xBA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP2 PSPI PI2C PWDT PADC PPWM Reset value Bit7 PSPI: SPI interrupt priority control; Set to high level interrupt; Set to low level interrupt. Bit6 PI2C: C interrupt priority control;... -
Page 117: External Interrupt Flag Bit Register Eif2
CMS80F751x Reference Manual 11.3.3 External Interrupt Flag Bit Register EIF2 0xB2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIF2 SPIIF I2CIF ADCIF PWMIF Reset value Bit7 SPIIF: SPI total interrupt indicator, read only; SPI produces an interrupt (this bit is automatically cleared after clearing the specific interrupt flag;... -
Page 118: Timer3 Operation Mode
CMS80F751x Reference Manual 11.4 Timer3 Operation Mode 11.4.1 T3 -Mode0（13-Bit Timing Mode） In this mode, the Timer3 is a 13-bit register. When all bits of the counter flip from 1 to 0, the Timer0 interrupt flag TF3 is set to 1. The 13-bit register is composed of 5-bit lower TL3 and TH3. The upper 3 bits of TL3 should be ignored. Timer3 Mode0 structure diagram is shown as follows : :12-T3M=0 EIF2.0... -
Page 119: T3 -Mode2（8-Bit Auto Reload Timing Mode
CMS80F751x Reference Manual 11.4.3 T3 -Mode2（8-Bit Auto Reload Timing Mode） The Timer3 register in Mode2 is an 8-bit timer ( TL3 ) equipped with automatic reload mode, as shown in the following figure. The overflow from TL3 not only makes TF3 set 1, but also reloads TH3 content from software to TL3. The TH3 value remains unchanged during reloading. -
Page 120: T3 -Mode3（Two Separate 8-Bit Timer
CMS80F751x Reference Manual 11.4.4 T3 -Mode3（Two Separate 8-Bit Timer） Timer3 in Mode3 sets TL3 and TH3 to two independent timers. The logic of Timer3 Mode3 is shown below. TL3 can operate as a timer and uses the control bits of Timer3:TR3, and TF3. TH0 can operate as a timer and uses the TR4 and TF4 flags of Timer4 to control the Timer4 interrupt. -
Page 121: Timer4 Operation Mode
CMS80F751x Reference Manual 11.5 Timer4 Operation Mode 11.5.1 T4 -Mode0（13-Bit Timing Mode） In this mode, the Timer4 is a 13-bit register. When all bits of the counter flip from 1 to 0, the Timer4 interrupt flag TF4 is set to 1. The 13-bit register is composed of 5-bit lower TL4 and TH4. The upper 3 bits of TL4 should be ignored. Timer4 Mode0 structure diagram is shown as follows : :12-T4M=0 EIF2.1... -
Page 122: T4- Mode2（8-Bit Auto Reload Timing Mode
CMS80F751x Reference Manual 11.5.3 T4- Mode2（8-Bit Auto Reload Timing Mode） The Timer4 register in Mode2 is an 8-bit timer ( TL4 ) equipped with automatic reload mode, as shown in the following figure. The overflow from TL4 not only makes TF4 set 1, but also reloads TH4 content from software to TL3. The TH4 value remains unchanged during reloading. -
Page 123: Lse_Timer
CMS80F751x Reference Manual 12. LSE_Timer 12.1 Overview The LSE timer is a 16-bit up-counting timer with a clock source from the external low speed clock LSE. When using the LSE timer function, you should first set the LSE module to be enabled, wait for the LSE clock to stabilize (about 1.5s), and then set the LSE count enable. -
Page 124: Lse Timer Control Register Lsecon
CMS80F751x Reference Manual 12.2.3 LSE Timer Control Register LSECON F696H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LSECON LSEEN LSEWUEN LSECNTEN LSESTA LSEIE LSEIF Reset value Bit7 LSEEN: LSE module enable control; Enable; Disable; Bit6 LSEWUEN: LSE timer wake-up enable control; Enable;... -
Page 125: Interrupt And Sleep Wake-Up
CMS80F751x Reference Manual 12.3 Interrupt And Sleep Wake-up The LSE timer can enable or disable interrupts through the LSECON register, and set the high/low priority through the EIP3 register. The interrupt related bits are as follows. 0xBB Bit7 Bit6 Bit5 Bit4 Bit3 Bit2... -
Page 126: Wake-Up Timer（Wut
CMS80F751x Reference Manual 13. Wake-Up Timer（WUT） 13.1 Overview Wake-Up Timer is a 12-bit, up-counting timer used for wake-up from sleep and a clock source from the internal low speed clock LSI. It can be used to wake up the system regularly in sleep mode. Configure the timing wake-up time before the system enters sleep, and enable the timing wake-up function. -
Page 127: Function Description
CMS80F751x Reference Manual 13.3 Function Description The principle of the internal wake-up timer is: after system enters the sleep mode, the CPU and all peripheral circuits stop working, and internal low power consumption oscillation LSI starts to work, and its oscillation clock is 125KHZ (T ≈... -
Page 128: Baud Rate Timer（Brt
CMS80F751x Reference Manual 14. Baud Rate Timer（BRT） 14.1 Overview There is a 16-bit baud rate timer BRT inside the chip, which mainly provides the clock for the UART module. 14.2 Related Registers 14.2.1 BRT Module Control Register BRTCON F5C0H Bit7 Bit6 Bit5 Bit4... -
Page 129: Brt Timer Data Is Loading The High 8-Bit Register Brtdh
CMS80F751x Reference Manual 14.2.3 BRT Timer Data Is Loading The High 8-bit Register BRTDH F5C2H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 BRTDH BRTDH7 BRTDH6 BRTDH5 BRTDH4 BRTDH3 BRTDH2 BRTDH1 BRTDH0 Reset value Bit7~Bit0 BRTDH<7:0>: BRT timer load value high 8-bit; 14.3 Function Description There is a 16-bit up counter inside the BRT. -
Page 130: Cycle Redundancy Check（Crc
CMS80F751x Reference Manual 15. Cycle Redundancy Check（CRC） 15.1 Overview In order to ensure safety during operation, the IEC61508 standard requires confirmation of data even when the CPU is running. This general-purpose CRC module can perform CRC calculations as a peripheral function during CPU operation. The general-purpose CRC module specifies the data to be confirmed by the program for CRC checking, not limited to the code flash area but can be used for multi-purpose checking. -
Page 131: Function Description
CMS80F751x Reference Manual 15.3 Function Description After writing the CRCIN register, and after a system clock, save the CRC operation result to the CRCDL/CRCDH register. If necessary, read the previous calculation data before writing overwise, otherwise it will be overwritten by the new calculation result. -
Page 132: Multiplication/Division Unit（Mdu
CMS80F751x Reference Manual 16. Multiplication/Division Unit（MDU） 16.1 Overview MDU（Multiplication/Division Unit） module provides the 32bit/16bit division, 16bit/16bit division, 16bit*16bit multiplication, 32bit shift operation, 32bit normalization operation functions. All operations are unsigned integer operation, among which shift operation support 32bit data left shift or right shift operation. The operation of MDU module is controlled by 7 registers （MD0/MD1/MD2/MD3/MD4/MD5/ARCON）. -
Page 133: Operation Register Md0
CMS80F751x Reference Manual 16.2.1 Operation Register MD0 0xE9 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD07 MD06 MD05 MD04 MD03 MD02 MD01 MD00 Reset value 32bit/16bit division operation: write bit7-bit0 as the dividend, read bit7-bit0 as the Bit7~Bit0 MD0<7:0>: quotient;... -
Page 134: Operation Register Md2
CMS80F751x Reference Manual 16.2.3 Operation Register MD2 0xEB Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD27 MD26 MD25 MD24 MD23 MD22 MD21 MD20 Reset value 32bit/16bit division operation: write bit23-bit16 as the dividend, read bit23-bit16 as the Bit7~Bit0 MD2<7:0>: quotient;... -
Page 135: Operation Register Md5
CMS80F751x Reference Manual 16.2.6 Operation Register MD5 0xEE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD57 MD56 MD55 MD54 MD53 MD52 MD51 MD50 Reset value 32bit/16bit division operation: write bit15-bit8 as the divisor, read bit15-bit8 as the Bit7~Bit0 MD5<7:0>: remainder;... -
Page 136: Function Description
CMS80F751x Reference Manual 16.3 Function Description The division and multiplication operation types of the MDU module are determined by the order of writing MD0~MD5, and the operation types of the shift and normalization functions are controlled by the ARCON register. The multiplication and division operation sequence of the MDU module is shown in the following table: Operation Operation... -
Page 137: 32Bit/16Bit Division Operation
CMS80F751x Reference Manual 16.3.1 32bit/16bit Division Operation The operation steps of the 32bit/16bit divider are as follows: Write the register MD0（bit7-bit0 of the dividend）; Write the register MD1（bit15-bit8 of the dividend）; Write the register MD2（bit23-bit16 of the dividend）; Write the register MD3（bit31-bit24 of the dividend）; Write the register MD4（bit7-bit0 of the divisor）;... -
Page 138: 16Bit*16Bit Multiplication Operation
CMS80F751x Reference Manual 16.3.3 16bit*16bit Multiplication Operation The operation steps of the 16bit/16bit multiplier are as follows: Write the register MD0（bit7-bit0 of the first multiplier）; Write the register MD4（bit7-bit0 of the second multiplier）; Write the register MD1（bit15-bit8 of the first multiplier）; Write the register MD5（bit15-bit8 of the second multiplier）, start the multiplication operation after writing is completed;... -
Page 139: 32Bit Normalization Operation
CMS80F751x Reference Manual 16.3.5 32bit Normalization Operation The normalization operation is to shift the operand to the left until the highest of the operand is 1 to end the shift. The 32bit normalization operation steps are as follow: Write the register MD0（bit7-bit0 of the operand）; Write the register MD1（bit15-bit8 of the operand）;... -
Page 140: Buzzer
CMS80F751x Reference Manual 17. BUZZER 17.1 Overview The buzzer consists of an 8-bit counter, a clock driver, and a control register. The buzzer drive output is a 50% duty square wave, the frequency of BUZZER is controlled by the BUZCON register and the BUZDIV register. And its frequency output can cover a wide range. -
Page 141: Function Description
CMS80F751x Reference Manual 17.3 Function Description When using the BUZZER, you need to configure the corresponding port as a BUZZER drive output port. For example, configure P16 as a BUZZER drive output port, the configuration is as follows: P16CFG = 0x04; // P16 is configured the BUZZER drive output port By configuring the corresponding register of the BUZZER drive module, you can set the BUZZER drive output port to output different frequencies. -
Page 142: Enhanced Pwm Module
CMS80F751x Reference Manual 18. Enhanced PWM Module 18.1 Overview The enhanced PWM module supports 6-channel PWM generators which can be configured as 6-channel independent PWM outputs (PG0-PG5). It can also be configured as 3 groups of synchronous PWM outputs, or 3 pairs of complementary PWM outputs with dead zone programming generators. -
Page 143: Pin Configuration
CMS80F751x Reference Manual 18.3 Pin Configuration It is necessary to configure corresponding ports as PWM channel before using enhanced PWM block, PWM channel is marked with PG0-PG5 on the pin distribution diagram, corresponding to PWM channel 0-5. The distribution of PWM channel is controlled by corresponding port configuration register, for example: P00CFG=0x05;... -
Page 144: Edge-Aligned
CMS80F751x Reference Manual 18.4.2 Edge-aligned In edge-aligned mode, the 16-bit PWM counter CNTn starts counting down in each period and compares it with the value CMPn latched in the PWMDnH/PWMDnL register. When CNTn=CMPn, PGn outputs a high level and PWMnDIF is set to 1. CNTn continues counting down to 0, and at this time, PGn will output low level and PWMnZIF will be set to 1. -
Page 145: Center-Aligned
CMS80F751x Reference Manual 18.4.3 Center-aligned In the center-aligned counting mode, symmetric counting and asymmetric counting are supported. To turn on the asymmetric counting mode, you need to set ASYMEN to 1. In the asymmetric counting mode, accurate center-aligned waveforms can be achieved. -
Page 146: Asymmetric Counting
CMS80F751x Reference Manual The center-aligned counter waveform (symmetric counting) is shown in the figure below: When PWMnCNTM=1, continuous mode is enabled, when CNTn counts to zero, reload PERIODn and CMPn PWMn clock PERIODn(new) PERIODn(old) CMPn(new) CMPn(old) Asymmetric counting 18.4.3.2 In center-aligned asymmetric counting mode, the 16-bit PWM counter CNTn counts up from 0. When CNTn=CMPn, PGn outputs a high level and PWMnUIF is set to 1;... - Page 147 CMS80F751x Reference Manual The center-aligned asymmetric counting timing is shown in the figure below: Continuous mode enable PWMnCNTM=1, when CNTn counts to zero, reload PERIODn and CMPn 1A34H PERIODn(new) PERIODn(old) 07FFH CMPDn(new) 022FH CMPDn(old) 012FH CMPn(old) 0080H 0000H PIFn ZIFn UIFn DIFn Continuous mode enable PWMnCNTM=1, when CNTn counts to zero, reload PERIODn and CMPn...
-
Page 148: Complementary Mode
CMS80F751x Reference Manual 18.4.4 Complementary Mode The 6-channel PWM can be set as 3 complementary pairs. In complementary mode, the period, duty cycle and clock division control of PG1, PG3 and PG5 are determined by the related registers of PG0, PG2 and PG4 respectively. That is, in addition to corresponding output enable control bit （PWMnOE）, The output waveforms of PG1, PG3 and PG5 are no longer controlled by their own registers. -
Page 149: Synchronize Mode
CMS80F751x Reference Manual 18.4.5 Synchronize Mode The 6-channel PWM can be set as 3 complementary pairs. In synchronize mode, the period, duty cycle and clock division control of PG1, PG3 and PG5 are determined by the related registers of PG0, PG2 and PG4 respectively. That is, in addition to corresponding output enable control bit （PWMnOE）, The output waveforms of PG1, PG3 and PG5 are no longer controlled by their own registers. -
Page 150: Pwm Related Registers
CMS80F751x Reference Manual 18.5 PWM Related Registers 18.5.1 PWM Control Register PWMCON F120H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMCON PWMRUN PWMMODE1 PWMMODE0 GROUPEN ASYMEN CNTTYPE Reset value Bit7 Reserved, must be 0; Bit6 PWMRUN: PWM clock prescaler, clock divider enable; Disable （PWMmnPSC, PWMmnDIV are all cleared to 0）;... -
Page 151: Pwm0/1 Clock Prescaler Control Register Pwm01Psc
CMS80F751x Reference Manual Enable; Disable. Bit2 PWM2OE: Output enable of PWM channel 2; Enable; Disable. Bit1 PWM1OE: Output enable of PWM channel 1; Enable; Disable. Bit0 PWM0OE: Output enable of PWM channel 0; Enable; Disable. 18.5.3 PWM0/1 Clock Prescaler Control Register PWM01PSC F123H Bit7 Bit6... -
Page 152: Pwm4/5 Clock Prescaler Control Register Pwm45Psc
CMS80F751x Reference Manual 18.5.5 PWM4/5 Clock Prescaler Control Register PWM45PSC F125H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM45PSC PWM45PSC7 PWM45PSC6 PWM45PSC5 PWM45PSC4 PWM45PSC3 PWM45PSC2 PWM45PSC1 PWM45PSC0 Reset value Bit7~Bit0 PWM45PSC<7:0>: Prescaler control of PWM channel 4/5; Prescaler clock stop, PWM4/5 counter stop; other= System clock（PWM45PSC+1）frequency division. -
Page 153: Pwm Output Polarity Control Register Pwmpinv
CMS80F751x Reference Manual 18.5.8 PWM Output Polarity Control Register PWMPINV F122H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMPINV PWM5PINV PWM4PINV PWM3PINV PWM2PINV PWM1PINV PWM0PINV Reset value Bit7~Bit6 Reserved, all must be 0. Bit5~Bit0 PWMnPINV: Output polarity control of PWM channel n (n=0-5); Reverse output;... -
Page 154: Pwm Counter Mode Control Register Pwmcntclr
CMS80F751x Reference Manual PWM Counter Mode Control Register PWMCNTCLR 18.5.11 F128H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMCNTCLR PWM5CNTCLR PWM4CNTCLR PWM3CNTCLR PWM2CNTCLR PWM1CNTCLR PWM0CNTCLR Reset value Bit7~Bit6 Reserved, all must be 0. Bit5~Bit0 PWMnCNTCLR: PWM channel n is counter clear 0 control(n=0-5)（Hardware clear 0 automatically）;... -
Page 155: Pwm Compare Data High 8-Bit Register Pwmdnh (N=0-5)
CMS80F751x Reference Manual PWM Compare Data High 8-bit Register PWMDnH (n=0-5) 18.5.15 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMDnH PWMDnH7 PWMDnH6 PWMDnH5 PWMDnH4 PWMDnH3 PWMDnH2 PWMDnH1 PWMDnH0 Reset value Register PWMDnH (n=0-5) address:F141H，F143H，F145H，F147H，F149H，F14BH. Bit7~Bit0 PWMDnH<7:0>: PWM channel n is compare date(duty cycle data) high 8-bit register. PWM Compare Data Low 8-bit Registers Down PWMDDnL (n=0-5) 18.5.16 Bit7... -
Page 156: Pwm0/1 Dead Zone Delay Data Register Pwm01Dt
CMS80F751x Reference Manual PWM0/1 Dead Zone Delay Data Register PWM01DT 18.5.19 F161H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM01DT PWM01DT7 PWM01DT6 PWM01DT5 PWM01DT4 PWM01DT3 PWM01DT2 PWM01DT1 PWM01DT0 Reset value Bit7~Bit0 PWM01DT<7:0>: PWM channel 0/1 dead zone delay data register. PWM2/3 Dead Zone Delay Data Register PWM23DT 18.5.20 F162H... -
Page 157: Pwm Mask Data Register Pwmmaskd
CMS80F751x Reference Manual PWM Mask Data Register PWMMASKD 18.5.23 F165H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMMASKD PWM5MASKD PWM4MASKD PWM3MASKD PWM2MASKD PWM1MASKD PWM0MASKD Reset value Bit7~Bit6 Reserved, all must be 0. Bit5~Bit0 PWMnMASKD: PWM channel n mask data (n=0-5); PWMn channel output is high;... -
Page 158: Pwm Brake Data Register Pwmfbkd
CMS80F751x Reference Manual PWM Brake Data Register PWMFBKD 18.5.25 F167H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMFBKD PWM5FBKD PWM4FBKD PWM3FBKD PWM2FBKD PWM1FBKD PWM0FBKD Reset value Bit7~Bit6 Reserved, all must be 0. Bit5~Bit0 PWMnFBKD: PWM channel n brake data (n=0-5); PWMn channel outputs high after braking operation;... -
Page 159: Pwm Interrupt
CMS80F751x Reference Manual 18.6 PWM Interrupt Enhanced PWM has a total of 25 interrupt flags, including 6 period interrupt flags, 6 zero-point interrupt flags, 6 upward comparison interrupt flags, 6 downward comparison interrupt flags, 1 brake interrupt flag. And the generation of interrupt flag bits, it does not matter whether the corresponding interrupt enable bit is turned on or not. -
Page 160: Interrupt Priority Control Register Eip2
CMS80F751x Reference Manual 18.6.2 Interrupt Priority Control Register EIP2 0xBA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP2 PSPI PI2C PWDT PADC PPWM Reset value Bit7 PSPI: SPI interrupt priority control; Set to high level interrupt; Set to low level interrupt. Bit6 PI2C: C interrupt priority control;... -
Page 161: Pwm Zero Interrupt Mask Register Pwmzie
CMS80F751x Reference Manual 18.6.4 PWM Zero Interrupt Mask Register PWMZIE F169H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMZIE PWM5ZIE PWM4ZIE PWM3ZIE PWM2ZIE PWM1ZIE PWM0ZIE Reset value Bit7~Bit6 Reserved, all must be 0. Bit5~Bit0 PWMnZIE: PWM channel n zero interrupt mask (n=0-5); Enable interrupt;... -
Page 162: Pwm Zero Interrupt Flag Register Pwmzif
CMS80F751x Reference Manual Generate an interruption (software clear); No interruption. 18.6.8 PWM Zero Interrupt Flag Register PWMZIF F16DH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMZIF PWM5ZIF PWM4ZIF PWM3ZIF PWM2ZIF PWM1ZIF PWM0ZIF Reset value Bit7~Bit6 Reserved, all must be 0. Bit5~Bit0 PWMnZIF: PWM channel n zero interrupt flag (n=0-5);... -
Page 163: Hardware Lcd Driver
CMS80F751x Reference Manual 19. Hardware LCD Driver 19.1 Overview Hardware LCD driver include a controller, a duty cycle generator and COM and SEG output ports. Hardware LCD driver support two modes: traditional resistance and fast charging，the bias resistance can be selected from 60KΩ, 225KΩ, and 900KΩ.Fast charging mode is a new way of design，when selecting 225KΩ, 900KΩ... -
Page 164: Related Register
CMS80F751x Reference Manual 19.3 Related Register 19.3.1 LCD Control Register LCDCON0 F680H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LCDCON0 LCDEN LCDDM1 LCDDM0 DUTY1 DUTY0 Reset Value Bit7 LCDEN: LCD Enable Control; LCD Enable; LCD Disable. Bit6 Reserved, must be 0. Bit5~Bit4 LCDDM<1:0>: LCD display mode;... -
Page 165: Lcd Control Register Lcdcon1
CMS80F751x Reference Manual 19.3.2 LCD Control Register LCDCON1 F681H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LCDCON1 LCDTEN BIAS1 BIAS0 LCDTVS3 LCDTVS2 LCDTVS1 LCDTVS0 Reset Value LCDTEN: LCD power supply voltage selection; Bit7 LCD voltage is provided by internal power supply V LCD voltage is provided by VDD. -
Page 166: Lcd Control Register Lcdcon3
CMS80F751x Reference Manual 0110= /4096; 1110= /65536; 0111= /8192; 1111= /65536. 19.3.4 LCD Control Register LCDCON3 F683H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LCDCON3 LCDRM1 LCDRM0 FCMODE FCCTL1 FCCTL0 Reset Value Bit7~Bit6 Reserved, all must be 0 LCD_RM<1:0>: LCD divider resistor selection;... -
Page 167: Seg Port Enable Control Register Lcdsegen0
CMS80F751x Reference Manual 19.3.6 SEG Port Enable Control Register LCDSEGEN0 F685H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LCDSEGEN0 SEGEN7 SEGEN6 SEGEN5 SEGEN4 SEGEN3 SEGEN2 SEGEN1 SEGEN0 Reset Value Bit7~Bit0 SEGEN<7:0>: LCD_S7-LCD_S0 port enable control; Enable; Disable. 19.3.7 SEG Port Enable Control Register LCDSEGEN1 F686H Bit7 Bit6... -
Page 168: Com -Seg Data-Sheet
CMS80F751x Reference Manual 19.4 COM -SEG data-sheet The hardware LCD driver mode is configured to different DUTY corresponding to the following data sheet. 19.4.1 1/4DUTY Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ICOM3 ICOM2 ICOM1 ICOM0 LCDSEG0 F650H SEG0 SEG0 SEG0 SEG0... -
Page 169: 1/5Duty
CMS80F751x Reference Manual 19.4.2 1/5DUTY Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ICOM4 ICOM3 ICOM2 ICOM1 ICOM0 LCDSEG0 F650H SEG0 SEG0 SEG0 SEG0 SEG0 LCDSEG1 F651H SEG1 SEG1 SEG1 SEG1 SEG1 LCDSEG2 F652H SEG2 SEG2 SEG2 SEG2 SEG2 LCDSEG3 F653H SEG3 SEG3... -
Page 170: 1/6Duty
CMS80F751x Reference Manual 19.4.3 1/6DUTY Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ICOM5 ICOM4 ICOM3 ICOM2 ICOM1 ICOM0 LCDSEG0 F650H SEG0 SEG0 SEG0 SEG0 SEG0 SEG0 LCDSEG1 F651H SEG1 SEG1 SEG1 SEG1 SEG1 SEG1 LCDSEG2 F652H SEG2 SEG2 SEG2 SEG2 SEG2 SEG2... -
Page 171: 1/8Duty
CMS80F751x Reference Manual 19.4.4 1/8DUTY Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ICOM7 ICOM6 ICOM5 ICOM4 ICOM3 ICOM2 ICOM1 ICOM0 LCDSEG0 F650H SEG0 SEG0 SEG0 SEG0 SEG0 SEG0 SEG0 SEG0 LCDSEG1 F651H SEG1 SEG1 SEG1 SEG1 SEG1 SEG1 SEG1 SEG1 LCDSEG2 F652H... -
Page 172: Hardware Led Driver
CMS80F751x Reference Manual 20. Hardware LED Driver 20.1 Overview The chip integrates a hardware LED display drive circuit, which can facilitate users to realize LED display drive. 20.2 Characteristic The LED driver supports the following features: ◆ 1/4, 1/5, 1/6, 1/8 four kinds of DUTY are optional. ◆... -
Page 173: Led Clock Prescaler Data Register Low 8-Bit Ledclkl
CMS80F751x Reference Manual COM Selection Description Table ICOM0 ICOM1 ICOM2 ICOM3 ICOM4 ICOM5 ICOM6 ICOM7 Effective SEG port DUTY LED_C0 LED_C1 LED_C2 LED_C3 LED_S0-LED_S19 LED_C0 LED_C1 LED_C2 LED_C3 LED_C4 LED_S1-LED_S19 LED_C0 LED_C1 LED_C2 LED_C3 LED_C4 LED_C5 LED_S2-LED_S19 LED_C0 LED_C1 LED_C2 LED_C3 LED_C4 LED_C5... -
Page 174: Com Port Enable Control Register Ledcomen
CMS80F751x Reference Manual 20.3.5 COM Port Enable Control Register LEDCOMEN F760H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDCOMEN COMEN7 COMEN6 COMEN5 COMEN4 COMEN3 COMEN2 COMEN1 COMEN0 Reset Value Bit7~Bit0 COMEN<7:0>: LED_C7-LED_C0 port enable control; Enable; Disable. 20.3.6 SEG Port Enable Control Register LEDSEGEN0 F761H Bit7 Bit6... -
Page 175: Com0 Corresponds To Seg Data Register Ledc0Datan（N=0-2
CMS80F751x Reference Manual 20.3.9 COM0 Corresponds To SEG Data Register LEDC0DATAn（n=0-2） Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDC0DATAn SEG[8n+7] SEG[8n+6] SEG[8n+5] SEG[8n+4] SEG[8n+3] SEG[8n+2] SEG[8n+1] SEG[8n] Reset Value LEDC0DATA0 address: F740H; LEDC0DATA1 address: F741H; LEDC0DATA2 address: F742H. When n = 0/1: Bit7~Bit0 SEG<8n+7:8n>: When COM0 port is valid, SEG[8n+7]-SEG[8n] port data output;... -
Page 176: Com2 Corresponds To Seg Data Register Ledc2Datan（N=0-2
CMS80F751x Reference Manual COM2 Corresponds To SEG Data Register LEDC2DATAn（n=0-2） 20.3.11 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDC2DATAn SEG[8n+7] SEG[8n+6] SEG[8n+5] SEG[8n+4] SEG[8n+3] SEG[8n+2] SEG[8n+1] SEG[8n] Reset Value LEDC2DATA0 address: F748H; LEDC2DATA1 address: F749H; LEDC2DATA2 address: F74AH. When n = 0/1: Bit7~Bit0 SEG<8n+7:8n>: When COM2 port is valid, SEG[8n+7]-SEG[8n] port data output;... -
Page 177: Com4 Corresponds To Seg Data Register Ledc4Datan（N=0-2
CMS80F751x Reference Manual COM4 Corresponds To SEG Data Register LEDC4DATAn（n=0-2） 20.3.13 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDC4DATAn SEG[8n+7] SEG[8n+6] SEG[8n+5] SEG[8n+4] SEG[8n+3] SEG[8n+2] SEG[8n+1] SEG[8n] Reset Value LEDC4DATA0 address: F750H; LEDC4DATA1 address: F751H; LEDC4DATA2 address: F752H. When n = 0/1: Bit7~Bit0 SEG<8n+7:8n>: When COM4 port is valid, SEG[8n+7]-SEG[8n] port data output;... -
Page 178: Com6 Corresponds To Seg Data Register Ledc6Datan（N=0-2
CMS80F751x Reference Manual COM6 Corresponds To SEG Data Register LEDC6DATAn（n=0-2） 20.3.15 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDC6DATAn SEG[8n+7] SEG[8n+6] SEG[8n+5] SEG[8n+4] SEG[8n+3] SEG[8n+2] SEG[8n+1] SEG[8n] Reset Value LEDC6DATA0 address: F758H; LEDC6DATA1 address: F759H; LEDC6DATA2 address: F75AH. When n = 0/1: Bit7~Bit0 SEG<8n+7:8n>: When COM6 port is valid, SEG[8n+7]-SEG[8n] port data output;... -
Page 179: Seg Port P04-P07 Drive Current Control Register Ledsdrp0H
CMS80F751x Reference Manual SEG Port P04-P07 Drive Current Control Register LEDSDRP0H 20.3.17 F711H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDSDRP0H DRC3 DRC2 DRC1 DRC0 Reset Value Bit7~Bit4 Reserved, all must be 0 Bit3~Bit0 DRC<3:0>: Source current drive selection control (control P04/P05/P06/P07 four SEG ports) 0000= 0mA;... -
Page 180: Seg Port P14-P17 Drive Current Control Register Ledsdrp1H
CMS80F751x Reference Manual SEG Port P14-P17 Drive Current Control Register LEDSDRP1H 20.3.19 F713H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDSDRP1H DRC3 DRC2 DRC1 DRC0 Reset Value Bit7~Bit4 Reserved, all must be 0 Bit3~Bit0 DRC<3:0>: Source current drive selection control (control P14/P15/P16/P17 four SEG ports); 0000= 0mA;... -
Page 181: Seg Port P24-P27 Drive Current Control Register Ledsdrp2H
CMS80F751x Reference Manual SEG Port P24-P27 Drive Current Control Register LEDSDRP2H 20.3.21 F715H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDSDRP2H DRC3 DRC2 DRC1 DRC0 Reset Value Bit7~Bit4 Reserved, all must be 0 Bit3~Bit0 DRC<3:0>: Source current drive selection control (control P24/P25/P26/P27 four SEG ports); 0000= 0mA;... -
Page 182: Com Port Current Sink Selection Register P0Dr
CMS80F751x Reference Manual COM Port Current Sink Selection Register P0DR 20.3.22 F00CH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0DR P0DR7 P0DR6 P0DR5 P0DR4 P0DR3 P0DR2 P0DR1 P0DR0 Reset Value P0DR7: Bit7 P07 drive current selection; 150mA; 50mA. P0DR6: Bit6 P06 drive current selection;... -
Page 183: Led Driver Output Waveform
CMS80F751x Reference Manual 20.4 LED Driver Output Waveform According to the relevant configuration registers of the LED driver, the corresponding LED driver output waveform can be set. LED configuration 1/4DUTY, common cathode drive mode, the waveform is shown in the figure below: COM0 is COM0 is valid valid... -
Page 184: Spi
CMS80F751x Reference Manual 21. SPI 21.1 Overview The SPI is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of serial clock signal SCK. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. -
Page 185: Spi Port Configuration
CMS80F751x Reference Manual 21.2 SPI Port Configuration To use the SPI function, you need to configure the related port as SPI channels, and select the corresponding port input through the communication input port register. For example, configure P00, P01, P02, P03 as SPI communication ports. The configuration code is as follows: PS_SCLK = 0x00;... -
Page 186: Spi Hardware Description
CMS80F751x Reference Manual 21.3 SPI Hardware Description When an SPI transfer occurs, an 8-bit character is shifted out on data pin while a different 8-bit character is simultaneously shifted in a second data pin. An 8-bit shift register in the master and another 8- bit shift register in the slave are connected as a circular 16-bit shift register. -
Page 187: Spi Related Register
CMS80F751x Reference Manual 21.4 SPI Related Register 21.4.1 SPI Control Register SPCR 0xEC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SPCR SPEN SPR2 MSTR CPOL CPHA SPR1 SPR0 Reset Value Reserved, must be 0. Bit7 SPI mode enable; Bit6 SPEN: Enable;... -
Page 188: Spi Data Register Spdr
CMS80F751x Reference Manual 21.4.2 SPI Data Register SPDR 0xEE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SPDR SPIDATA7 SPIDATA6 SPIDATA5 SPIDATA4 SPIDATA3 SPIDATA2 SPIDATA1 SPIDATA0 Reset Value Data send or received by the SPI. Bit7~Bit0 SPIDATA<7:0>: write: Write the data to be send(Send order from high to low). read: Received data. -
Page 189: Spi State Register Spsr
CMS80F751x Reference Manual 21.4.4 SPI State Register SPSR 0xED Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SPSR SPISIF WCOL SSCEN Reset Value Bit7 SPISIF: SPI complete flag, Read only; SPI transfer to complete (Read SPSR first, then clear after reading/writing SPDR); SPI not transferred. -
Page 190: Spi Master Model
CMS80F751x Reference Manual 21.5 SPI Master Model When the SPI is configured in master mode, the transfer is initiated by writing to the SPDR register. When a new byte is written into the SPDR register, the SPI starts to transfer. The serial clock SCLK is generated by SPI. In the master mode, SPI is enabled and SCLK is output. -
Page 191: Write Collision Error
CMS80F751x Reference Manual 21.5.1 Write Collision Error A write collision occurs if the SPI data register is written while a transfer is in progress. The transfer continues undisturbed, and the write data that caused the error is not written to the shifter. The write wollision is indicated by the WCOL flag in SPSR register. -
Page 192: Spi Slave Mode
CMS80F751x Reference Manual 21.6 SPI Slave Mode When configured as SPI slave the transfer is initiated by external SPI master module by assertion of the SPI slave select input, and generation of the SCK serial clock. Before the start of the transfer, it is necessary to determine which SPI slave will be used to exchange data. The NSS is asserted (cleared = 0), the clock signal connected to the SCLK line will cause the SPI slave to shift into receiver shift register contents of the MOSI line, and drives the MISO line with contents of the transmitter shift register. - Page 193 CMS80F751x Reference Manual In case CPHA is cleared, WCOL generation can also be caused by writing to SPDR register when any NSS line is cleared. At this time, the SPI master can also complete without generating the serial clock SCLK. This is because the start of the transfer is not explicitly specified, and the NSS being driven low after the full byte transfer may indicate the start of the next byte transfer.
-
Page 194: Spi Clock Control Logic
CMS80F751x Reference Manual 21.7 SPI Clock Control Logic 21.7.1 SPI Clock Phase And Polarity Control Software can select any of four combinations of serial clock (SCK) phase and polarity using two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, When the transmission is idle, the CPOL control bit selection high or low has no significant impact on the transmission format. -
Page 195: Cpha=1 Transport Format
CMS80F751x Reference Manual 21.7.4 CPHA=1 Transport Format Figure below is a timing diagram of an SPI transfer where CPHA = 1. Two waveforms are shown for SCLK: one for CPOL= 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing diagram since the SCLK, MISO, and MOSI pins are directly connected between the master and the slave. -
Page 196: Spi Data Transmission
CMS80F751x Reference Manual 21.8 SPI Data Transmission 21.8.1 SPI Transfer Start All SPI transfers are started and controlled by a master SPI device. As a slave, the transfer to begin with the first SCLK edge or the falling edge of NSS, depending on the CPHA format selected. When CPHA = 0, the falling edge of NSS indicates the beginning of a transfer. -
Page 197: Spi Timing Diagram
CMS80F751x Reference Manual 21.9 SPI Timing Diagram 21.9.1 Master Mode Transmission When the clock polarity of SPI is CPOL=0 and the clock phase CPHA=1, the system clock CLK after NSS is low in SPI master control mode, MOSI starts to output, and the data of MOSI is output on the rising edge of the SCLK clock. The timing diagram of the main control mode is shown in the figure below: 21.9.2 Slave Mode Transmission When the SPI clock polarity CPOL=0 and the clock phase CPHA=1, the data on MISO starts to output after the falling edge... -
Page 198: Spi Interrupt
CMS80F751x Reference Manual 21.10 SPI Interrupt SPI's interrupt number is 22, The interrupt vector is 0x00B3. If the SPI interrupt is to be enabled, the SPIIE must be set to 1, and set the total interrupt EA. If the SPI related interrupt enable is turned on and the SPI total interrupt indication bit SPIIF = 1, the CPU will enter the interrupt service routine. -
Page 199: Interrupt Priority Control Register Eip2
CMS80F751x Reference Manual Disable Timer4 interrupt. Bit0 ET3: Timer3 interrupt enable; Enable Timer3 interrupt; Disable Timer3 interrupt. Interrupt Priority Control Register EIP2 21.10.2 0xB8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP2 PSPI PI2C PWDT PADC PPWM Reset value Bit7 PSPI: SPI interrupt priority control;... -
Page 200: Peripheral Interrupt Flag Register Eif2
CMS80F751x Reference Manual Peripheral Interrupt Flag Register EIF2 21.10.3 0xB2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIF2 SPIIF I2CIF ADCIF PWMIF Reset value Bit7 SPIIF: SPI total interrupt indicator, read only; SPI produces an interrupt (this bit is automatically cleared after clearing the specific interrupt flag;... -
Page 201: I 2 C Module
CMS80F751x Reference Manual 22. I C Module 22.1 Overview This module provides the interface between the microprocessor and the I C bus. The connection diagram is shown in the figure below, and supports arbitration and clock synchronization so that it can run in multi-master system. I C supports normal and fast modes. -
Page 202: I 2 C Port Configuration
CMS80F751x Reference Manual 22.2 I C Port Configuration If you use the I C function, you should first configure the corresponding ports as SCL and SDA channels. For example, configure P00 and P01 ports as I C functions: PS_SCL = 0x00; //Select port P00 as the SCL pin PS_SDA = 0x01;... -
Page 203: I 2 C Period Timer Register In Master Mode
CMS80F751x Reference Manual 22.3.1 I C Period Timer Register In Master Mode In order to generate a wide range of SCL frequency, this model have 8-bit timer which is used to standard and fast transmission. When TIMER_PRD ≠ 0，Ideal clock cycle of SCL = 2* (1+TIMER_PRD)* 10* Tsys When TIMER_PRD＝0，Ideal clock cycle of SCL = 3* 10* Tsys Refer to IIC Application Manual for the specific calculation formula of SCL. - Page 204 CMS80F751x Reference Manual Enable; Disable. Run enable; Bit0 RUN: Enable; Disable. The combination of the following control bit list can realize all kinds of operations in master control module: START: send start signal. SEND: send data or address. RECEIVE: receive data. STOP: send end signal.
- Page 205 CMS80F751x Reference Manual The combination of control bit(receiving state in main control module) OPERATION STOP START RECEIVE(master machine maintain in receive mode) STOP STOP after RECEIVE RECEIVE (master machine maintain in receive mode) No combination Repeat START, followed by RECAIVE(master machine maintain in receive mode) Repeat START, followed by SEND and STOP Repeat START, followed by RECAIVE(master machine...
-
Page 206: I 2 C Slave Address Register
CMS80F751x Reference Manual No response of addressing slave machine and arbitration conflict. Busy flag in I C master control mode; Bit0 BUSY: Sending data. 22.3.3 I C Slave Address Register The salve address register is composed by 8 bits: address bit of 7 bits(A6-A0) and receive/send bit(R/S). R/S determines whether the next operation is to receive(1) or to send(0). -
Page 207: I 2 C Slave Mode
CMS80F751x Reference Manual 22.4 I C Slave Mode There are five registers that is used to connect object device: address, control, send data and receive data. Register Address Write Read Own Address register (I2CSADR) Own Address register I2CSADR 0xF1 Control register I2CSCR Status register I2CSSR 0xF2 0xF3... -
Page 208: Sending And Receiving Cached Register Of I C Slave Mode I2Csbuf
CMS80F751x Reference Manual The status register consists of three bits: SENDFIN, RREQ and TREQ. The SENDFIN bit indicates that the host I controller has completed receiving data during the single or continuous transmission operation of I2CS. The RREQ bit indicates that the I2CS device has received data from the I C host machine, then the I2CS device should read a byte from the receiving register(I2CSBUF). -
Page 209: I 2 C Interrupt
CMS80F751x Reference Manual 22.5 I C interrupt The interruption number of I C is 21, where the interruption vector is 0x00AB. To enable I C interrupt, the enable bit(I2CIE) is set to 1, and the master interruption enable bit(EA) is set to 1. If all the interruption enable is turned on and master interruption enable(I2CIF) is set to 1, then the CPU will enter the interrupt service program. -
Page 210: Interrupt Priority Control Register Eip2
CMS80F751x Reference Manual 22.5.2 Interrupt Priority Control Register EIP2 0xBA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP2 PSPI PI2C PWDT PADC PPWM Reset value Bit7 PSPI: SPI interrupt priority control; Set to high level interrupt; Set to low level interrupt. Bit6 PI2C: C interrupt priority control;... -
Page 211: Peripheral Interrupt Flag Register Eif2
CMS80F751x Reference Manual 22.5.3 Peripheral Interrupt Flag Register EIF2 0xB2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIF2 SPIIF I2CIF ADCIF PWMIF Reset value Bit7 SPIIF: SPI total interrupt indicator, read only; SPI produces an interrupt (this bit is automatically cleared after clearing the specific interrupt flag;... -
Page 212: I 2 C Transmission Method Of Slave Mode
CMS80F751x Reference Manual 22.6 I C Transmission Method of Slave Mode The default I C address of all the waveform presented in this section is 0x39 ("00111001"). 22.6.1 Single Receiving The following figure shows the sequence of signals received by I C during single data. -
Page 213: Continuous Receiving
CMS80F751x Reference Manual 22.6.3 Continuous Receiving The following figure shows the sequence of signals received by I C during burst data. Continuous receive sequence: Starting conditions. Addressing by I C host machine. The address is confirmed by I The data is received by I The data is confirmed by I Stop conditions. -
Page 214: Uartn Moudle
CMS80F751x Reference Manual 23. UARTn Moudle 23.1 Overview The Universal Synchronous Asynchronous Receiver Transmitter (UART0 / UART1) provides a flexible method for full-duplex data exchange with external devices. There are two physically independent receiving and sending buffers inside UARTn.SBUFn, which can be used to distinguish between receiving and sending buffers by reading and writing commands to SBUFn. -
Page 215: Uartn Baud Rate
CMS80F751x Reference Manual 23.3 UARTn Baud Rate When UARTn is in mode 0, the baud rate is fixed to the system clock divided by 12 (Fsys/12); in mode 2, the baud rate is fixed to the system clock divided by 32 or 64 (Fsys /32, Fsys/64); In mode 1 and mode 3, the baud rate is generated by the timer Timer1 or Timer4 or Timer2 or BRT module. -
Page 216: Baud Rate Deviation
CMS80F751x Reference Manual BRTCKDIV is the BRT timer prescaler selection bit, which is set by the register BRTCON. The value of BRT under the corresponding baud rate should be set to: SMODn Fsys×2 {BRTDH,BRTDL}=65536- BRTCKDIV 32×2 ×BaudRate 23.3.3 Baud Rate Deviation When UARTn is in mode 1 and mode 3, select different baud rate clock sources, the error is as follows under different baud rates: Table 1) and 2) are part of the baud rate related information in the 8-bit auto-reload mode of Timer 1/Timer 4 in the variable... - Page 217 CMS80F751x Reference Manual 3）SMODn=0，BRTCKDIV=0 Baud rate Fsys=8MHz Fsys=16MHz Fsys=24MHz Fsys=48MHz {BRT, Actual {BRTH, Actual {BRTH, Actual {BRTH, Actual BRTL} Rate Error BRTL} Rate Error BRTL} Rate Error BRTL} Rate Error 4800 65484 4808 -0.16 65432 4808 -0.16 65380 4808 -0.16 65224 4808 -0.16...
-
Page 218: Uartn Registers
CMS80F751x Reference Manual 23.4 UARTn Registers The UARTn has the same functionality as a standard 8051 UART. The related registers are: FUNCCR、SBUFn、SCONn、 PCON、IE、IP、EIP3. The UARTn data buffer (SBUFn) consists of two separate registers: transmit and receive registers. A data written into the SBUFn will be set in UARTn output register and starts a transmission. Reading SBUFn will read data from the UARTn receive register. -
Page 219: Uart Control Register Sconn
CMS80F751x Reference Manual 23.4.3 UART Control Register SCONn Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCONn UnSM0 UnSM1 UnSM2 UnREN UnTB8 UnRB8 Reset value BANK0: SCON0 register address: 0x98; SCON1 register address: 0xEA. Control bit for multi-processor communications; Bit7~Bit6 UnSM0- UnSM1: Master control synchronous mode;... -
Page 220: Pcon Register
CMS80F751x Reference Manual 23.4.4 PCON Register 0x87 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PCON SMOD0 SMOD1 STOP IDLE Reset value Register in BANK0 Bit7 SMOD0: UART0 baud rate double; UART0 baud rate doubling; UART0 baud rate normal. Bit6 SMOD1: UART1 baud rate double;... -
Page 221: Uartn Interrupt
CMS80F751x Reference Manual 23.5 UARTn Interrupt The interrupt number of UART0 is 4, and its interrupt vector is 0x0023. The interrupt number of UART1 is 6, and its interrupt vector is 0x0033. Enable UARTn interrupt needs to set 1 to ESn bit and set 1 to overall interrupt enable bit: EA. If related interrupt enabling is turned on, Tin = 1 or RIn = 1, CPU will enter related ISR (Interrupt Service Routines). -
Page 222: Interrupt Priority Control Register Ip
CMS80F751x Reference Manual 23.5.2 Interrupt Priority Control Register IP 0xB8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset value Bit7 Reserved, must be 0. Bit6 PS1: UART1 interrupt priority control; Set to high priority interrupt; Set to low priority interrupt. Bit5 PT2: TIMER2 interrupt priority control;... -
Page 223: Interrupt Priority Control Register Eip3
CMS80F751x Reference Manual 23.5.3 Interrupt Priority Control Register EIP3 0xBB Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP3 PTOUCH PLVD PLSE Reset value Bit7~Bit5 Reserved, all must be 0. Bit4 PTOUCH: TOUCH interrupt priority control; Set to high priority interrupt; Set to low priority interrupt. -
Page 224: Uartn Mode
CMS80F751x Reference Manual 23.6 UARTn Mode 23.6.1 Mode 0 - Synchronous Mode Pin RXDn serves as input and TXDn as output. TXDn output is a shift clock. The baud rate is fixed at 1/12 of the CLK clock frequency. Eight bits are transmitted with LSB first. Initialize the reception by setting the flag in SCONn, set as: RIn = 0 and RENn = 1. -
Page 225: Mode 2 - 9-Bit Asynchronous Mode (Fixed Baud Rate)
CMS80F751x Reference Manual 23.6.3 Mode 2 - 9-bit Asynchronous Mode (Fixed Baud Rate) This mode is similar to Mode 1 with two differences. The baud rate is fixed at 1/32 or 1/64 of CLK clock frequency, and 11 bits are transmitted or received: a start bit (0), 8 data bits (LSB first), a programmable 9th bit, and a stop bit (1). The 9th bit can be used to control the parity checking of the UARTn interface: at transmission, bit TBn8 in SCONn is output as the 9th bit, and at receive, the 9th bit affects RBn8 in SCONn. -
Page 226: Analog To Digital Conversion (Adc)
CMS80F751x Reference Manual 24. Analog To Digital Conversion (ADC) 24.1 Overview The ADC can convert the analog input signal into a 12-bit binary representing the signal, the block diagram of ADC structure is shown in the figure below. The port analog input signal and internal analog signal is connected to the input of the analog to digital converter after passing through the multiplexer. -
Page 227: Adc Configuration
CMS80F751x Reference Manual 24.2 ADC Configuration When configuring and using the ADC, the following factors must be considered: ⚫ Port configuration. Channel selection. ⚫ ⚫ ADC conversion clock source. ⚫ Interrupt control. ⚫ Result storage format. 24.2.1 Port Configuration The ADC can convert analog signals and convert digital signals. When converting analog signals, should be configured as an analog port by configuring the corresponding. -
Page 228: Conversion Clock
CMS80F751x Reference Manual 24.2.4 Conversion Clock The ADCKS bit of the ADCON1 register can be set by software to select the clock source for conversion. The time to complete one bit conversion is defined as T . A complete 12-bit conversion requires 18.5 T cycles (the ADCK ADCK... -
Page 229: Adc Hardware Triggered Start
CMS80F751x Reference Manual 24.3 ADC Hardware Triggered Start In addition to the software-triggered AD conversion, the ADC module also can be triggered by the hardware, one for the external port edge trigger mode, one It is an edge or period trigger of PWM. Using hardware to trigger the ADC requires ADCEX to be set, that is, enable the external trigger ADC function. -
Page 230: Adc Results Of Comparison
CMS80F751x Reference Manual 24.4 ADC Results Of Comparison ADC block provides a set of digital comparators for comparison between the results of ADC and the numbers pre-loaded in {ADCMPH,ADCMPL}. The conversion results of ADC will be compared with preset value ADCMP every time, the result of comparison will be stored in ADCMPO flag bit, this flag bit will be updated automatically after the conversion. -
Page 231: A/D Conversion Step
CMS80F751x Reference Manual 24.5.4 A/D Conversion Step The configuration steps for analog to digital conversion using ADC are as follows: PIN Configuration: ⚫ Use a pin as an output driver is forbidden (PxTRIS register); ⚫ Configure pins as analog input pin. Configure ADC interrupt (optional): ⚫... -
Page 232: Related Register
CMS80F751x Reference Manual 24.6 Related Register The following nine registers are related to AD conversion: ⚫ AD control registers:ADCON0、ADCON1、ADCON2、ADCCHS、ADCLDO; ⚫ Comparator control register: ADCMPC; ⚫ Delay data register: ADDLYL; ⚫ AD results data registers: ADRESH/L; Comparator data register: ADCMPH/L. ⚫ 24.6.1 AD Control Register ADCON0 0xDF Bit7... -
Page 233: Ad Control Register Adcon1
CMS80F751x Reference Manual 24.6.2 AD Control Register ADCON1 0xDE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCON1 ADEN ADCKS2 ADCKS1 ADCKS0 Reset value Bit7 ADEN: ADC enable; Enable ADC; Disable ADC, no operating current is consumed. Bit6~Bit4 ADCKS<2:0>: ADC conversion clock select. 000= Fsys/2;... -
Page 234: Ad Channel Selection Register Adcchs
CMS80F751x Reference Manual 24.6.4 AD Channel Selection Register ADCCHS 0xD9 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCCHS CHS5 CHS4 CHS3 CHS2 CHS1 CHS0 Reset value Bit7 Reserved, must to be 0; Bit5~Bit0 CHS<5:0>: Analog channel select; 000000= AIN0; 010000= AIN16;... -
Page 235: Ad Hardware Trigger Delay Data Register Addlyl
CMS80F751x Reference Manual Bit3~Bit2 Reserved, all must to be 0. Bit1~Bit0 ADDLY<9:8>: ADC hardware trigger delay data [9:8] bits. 24.6.6 AD Hardware Trigger Delay Data Register ADDLYL 0xD3 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADDLYL ADDLY7 ADDLY6 ADDLY5 ADDLY4 ADDLY3 ADDLY2... -
Page 236: Ad Data Register High Adresh，Adfm=1(Right-Aligned)
CMS80F751x Reference Manual 24.6.9 AD Data Register High ADRESH，ADFM=1(Right-aligned) 0xDD Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADRESH ADRES11 ADRES10 ADRES9 ADRES8 Reset value Bit7~Bit4 Unused. Bit3~Bit0 ADRES<11:8>: ADC results register. Number 11 to 8 bit of 12-bit conversion results. AD Data Register Low ADRESH，ADFM=1(Right-aligned) 24.6.10 0xDC... -
Page 237: Ad Reference Voltage Control Register
CMS80F751x Reference Manual AD Reference Voltage Control Register 24.6.13 F692H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCLDO LDOEN VSEL1 VSEL0 Reset value Bit7 LDOEN ADC_LDO enable; Enable LDO, the reference voltage can only select the voltage corresponding to VSEL [1:0];... -
Page 238: Adc Interrupt
CMS80F751x Reference Manual 24.7 ADC Interrupt The ADC module allows an interrupt to be generated after the analog to digital conversion is completed. The ADC Interrupt Enable bit is the ADCIE bit in the EIE2 register. The ADC Interrupt Flag is the ADCIF bit in the EIF2 register. The ADCIF bit must be cleared in software. -
Page 239: Interrupt Priority Control Register Eip2
CMS80F751x Reference Manual 24.7.2 Interrupt Priority Control Register EIP2 0xBA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP2 PSPI PI2C PWDT PADC PPWM Reset value Bit7 PSPI: SPI interrupt priority control; Set to high level interrupt; Set to low level interrupt. C interrupt priority control;... -
Page 240: External Interrupt Flag Bit Register Eif2
CMS80F751x Reference Manual 24.7.3 External Interrupt Flag Bit Register EIF2 0xB2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIF2 SPIIF I2CIF ADCIF PWMIF Reset value Bit7 SPIIF: SPI total interrupt indicator, read only; SPI produces an interrupt (this bit is automatically cleared after clearing the specific interrupt flag;... -
Page 241: Temperature Sensor
CMS80F751x Reference Manual 25. Temperature Sensor 25.1 Overview The chip contains a temperature sensor whose output analog varies with the chip temperature. The temperature change can be indirectly obtained by ADC sampling and converting the analog signal output by the sensor. 25.2 Register Description 25.2.1 Temperature Sensor Control Register TS_REG 0xF693... -
Page 242: Functional Characteristic
CMS80F751x Reference Manual 25.3.2 Functional Characteristic The temperature sensor has the following characteristics: When the temperature changes from -40 °C to 125 °C, the analog signal voltage range of the temperature sensor is 0.7V ~ 1.4V; When the temperature changes from -40 °C to 125 °C, the slope of analog quantity changing with temperature is K:3.5±0.2 mV/℃;... -
Page 243: Calculation Formula
CMS80F751x Reference Manual 25.3.3 Calculation Formula The conversion result of temperature sensor is: ×4096 In the above formula, RES is the measured 12-bit AD conversion value, �� is the reference voltage of ADC (unit: V), ������ is the output voltage of analog signal (unit: V), and ∆V is the output voltage of analog signal. ��... -
Page 244: Touch
CMS80F751x Reference Manual 26. TOUCH The touch module is an integrated circuit designed to realize the human touch interface, which can replace the mechanical light touch button to realize the operation interface of waterproof and dustproof, sealing and isolation, solid and beautiful. technical parameter: ◆... -
Page 245: Acmp0/1
CMS80F751x Reference Manual 27. ACMP0/1 The chip contains two analog comparators, ACMP0 and ACMP1. When the positive terminal voltage is greater than the negative terminal voltage, the comparator outputs logic 1, otherwise it outputs 0, which can also be changed by the output polarity selection bit. - Page 246 CMS80F751x Reference Manual The comparator hysteresis control block diagram is shown below: The negative terminal voltage of the comparator is fixed, and The positive terminal voltage of the comparator is fixed, the output waveform is changed when the positive terminal and the negative terminal voltage is changed, and its voltage is changed.
-
Page 247: Related Register
CMS80F751x Reference Manual 27.3 Related Register 27.3.1 Comparator Control Register CnCON0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CnCON0 CnEN CnCOFM CnN2G CnNS1 CnNS0 CnPS2 CnPS1 CnPS0 Reset value C0CON0 address: F500H; C1CON0 address: F503H. Bit7 CnEN: Comparator n enable; Enable;... -
Page 248: Comparator Control Register C0Con1
CMS80F751x Reference Manual 27.3.2 Comparator Control Register C0CON1 F501H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 C0CON1 C0OUT C0CRS C0ADJ4 C0ADJ3 C0ADJ2 C0ADJ1 C0ADJ0 Reset value Bit7 C0OUT: Comparator 0 result (read only). Bit6 C0CRS: Comparator 0 adjustment mode input port select; The positive and negative terminal are connected together and input from the positive terminal;... -
Page 249: Comparator Adjust Bit Select Register C0Adje
CMS80F751x Reference Manual 0000= (0~1)*Tsys; 0001= (1~2)*Tsys; 0010= (2~3)*Tsys; 0011= (4~5)*Tsys; 0100= (8~9)*Tsys; 0101= (16~17)*Tsys; 0110= (32~33)*Tsys; 0111= (64~65)*Tsys; 1000= (128~129)*Tsys; 1001= (256~257)*Tsys; 1010= (512~513)*Tsys; Other= (0~1)*Tsys. 27.3.3 Comparator Adjust Bit Select Register C0ADJE F50AH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0... -
Page 250: Comparator Hysteresis Control Register Cnhys
CMS80F751x Reference Manual 27.3.4 Comparator Hysteresis Control Register CnHYS Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CnHYS CnHYS_PNS1 CnHYS_PNS0 CnHYS_S1 CnHYS_S0 Reset value C0HYS address:F50CH; C1HYS address:F50DH. Bit7~Bit4 Reserved, all must to be 0. Positive and negative hysteresis selection bit; Bit3~Bit2 CnHYS_PNS<1:0>... -
Page 251: Comparator Brake Control Register Cnfbcon
CMS80F751x Reference Manual 27.3.6 Comparator Brake Control Register CNFBCON F507H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CNFBCON C1FBEN C0FBEN C1FBLS C0FBLS Reset value Bit7~Bit4 Reserved, all must to be 0. Bit3 C1FBEN: Comparator 1 output controlling PWM brake enable; Disable;... -
Page 252: Comparator Interrupt
CMS80F751x Reference Manual 27.4 Comparator Interrupt Both Comparator 0 and Comparator 1 can set interrupts, and both share an interrupt vector entry. After entering the interrupt service program, the user can use the interrupt flag bit to determine which type of interrupt is generated. Comparator interrupt priority and interrupt enable can be set by the following relevant register bits. -
Page 253: Comparator Interrupt Flag Register Cnif
CMS80F751x Reference Manual 27.4.3 Comparator Interrupt Flag Register CNIF F509H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CNIF C1IF C0IF Reset value Bit7~ Bit2 Reserved, all must to be 0. Bit1 C1IF: Comparator 1 interrupt flag (writing 0 to clear); Compare 1 output changes. -
Page 254: Op0/1
CMS80F751x Reference Manual 28. OP0/1 The chip contains two operational amplifier modules, OP0 and OP1, basic signal amplification and signal calculation functions can be realized with a small number of peripheral components. 28.1 OP Amp Characteristics Its characteristics are as follows: ◆... -
Page 255: Related Register
CMS80F751x Reference Manual 28.3 Related Register 28.3.1 Op Amp Control Register OPnCON0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 OPnCON0 OPnEN OPnCOFM OPnFIL OPnOS OPnNS1 OPnNS0 OPnPS1 OPnPS0 Reset value OP0CON0 address: F520H; OP1CON0 address: F523H. Bit7 OPnEN: OPn enable; Enable;... -
Page 256: Op Amp Adjustment Bit Selection Register Opnadje
CMS80F751x Reference Manual 28.3.3 Op Amp Adjustment Bit Selection Register OPnADJE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 OPnADJE OPnADJE7 OPnADJE6 OPnADJE5 OPnADJE4 OPnADJE3 OPnADJE2 OPnADJE1 OPnADJE0 Reset value OP0ADJE address: F526H; OP1ADJE address: F527H. OPn offset voltage adjustment mode select. Bit7~Bit0 OPnADJE<7:0>: Determined by OPnADJ<4:0>... -
Page 257: Flash Memory
CMS80F751x Reference Manual 29. Flash Memory 29.1 Overview FLASH memory includes program memory (APROM/BOOT) and non-volatile data memory (Data FLASH). The maximum program memory space is 32KB, divided into 64 sectors, each sector contains 512B. The maximum data memory space is 1KB, divided into 2 sectors, each sector contains 512B. -
Page 258: Related Register
CMS80F751x Reference Manual 29.2 Related Register 29.2.1 FLASH Protection Lock Register MLOCK 0xFB Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MLOCK MLOCK7 MOCK6 MLOCK5 MLOCK4 MLOCK3 MLOCK2 MLOCK1 MLOCK0 Reset value Bit7~Bit0 MLOCK<7:0>: Memory operation enable bit (this register only supports write operation, read as 00H); AAH= Allow memory related R/W/E operations;... -
Page 259: Flash Memory High Address Register Madrh
CMS80F751x Reference Manual 29.2.4 FLASH Memory High Address Register MADRH 0xFD Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MADRH MADRH7 MADRH6 MADRH5 MADRH4 MADRH3 MADRH2 MADRH1 MADRH0 Reset value Bit7~Bit0 MADRH<7:0>: Specify the higr 8-bit of the address for memory read/write operations. 29.2.5 Program CRC Operation Result Data Register Low 8-bit PCRCDL 0xF9 Bit7... -
Page 260: Flash Memory Control Register Mctrl
CMS80F751x Reference Manual 29.2.7 FLASH Memory Control Register MCTRL 0xFF Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MCTRL MERR MREG MMODE1 MMODE0 CRCADR MSTART Reset value Bit7~Bit6 Reserved. Bit5 MERR: Operation error flag (write 0 clear); Before the programming operation, the write operation is immediately terminated when the data in the test programming address is not "FFH"... -
Page 261: Function Description
CMS80F751x Reference Manual 29.3 Function Description During the FLASH memory read/write/erase operation, the CPU is in a suspended state, and when the operation is completed, the CPU continues to run instructions. The operation memory instruction must be followed by 6 NOP instructions, for example: MOV MCTRL, #09H ;... -
Page 262: Unique Id（Uid
CMS80F751x Reference Manual 30. Unique ID（UID） 30.1 Overview Each chip has a different 96-bit unique identification number, that is, unique identification. It has been set at the factory and cannot be modified by the user. 30.2 UID Register Description UID0 F5E0H Bit7 Bit6... - Page 263 CMS80F751x Reference Manual UID4 F5E4H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 UID4 UID39 UID38 UID37 UID36 UID35 UID34 UID33 UID32 Reset value Bit7~Bit0 UID<39:32> UID5 F5E5H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 UID5 UID47 UID46 UID45 UID44 UID43 UID42...
- Page 264 CMS80F751x Reference Manual UID9 F5E9H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 UID9 UID79 UID78 UID77 UID76 UID75 UID74 UID73 UID72 Reset value Bit7~Bit0 UID<79:72> UID10（0xF5EA） F5EAH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 UID10 UID87 UID86 UID85 UID84 UID83 UID82...
-
Page 265: User Configuration
CMS80F751x Reference Manual 31. User Configuration The system configuration register (CONFIG) is the FLASH option for the MCU initial condition, cannot be accessed and operated by the program. It contains the following: WDT（Watchdog working mode selection） ENABLE Forced to open WDT ⚫... - Page 266 CMS80F751x Reference Manual ⚫ ENABLE(OPEN PULLUP) External reset enable and open reset internal pull-up resistor 11. WAKE UP_WAIT TIME（Sleep and wake-up and wait for the oscillator to stabilize the default time is 1.0s） ⚫ 50us ⚫ ⚫ 100us ⚫ 10ms ⚫...
-
Page 267: Online Programming And Debugging
CMS80F751x Reference Manual 32. Online Programming And Debugging 32.1 Online Programming Mode The chip can be serially programmed in the final application circuit. Programming can be done simply through the following 4 wires: ⚫ ⚫ ⚫ ⚫ Online serial programming allows users to use unprogrammed devices to manufacture circuit boards and program the chip only before the product is delivered, so that the latest version of firmware or customized firmware can be programmed into the chip. -
Page 268: Online Debug Mode
CMS80F751x Reference Manual 32.2 Online Debug Mode The chip supports 2-wire (DSCK, DSDA) online debugging function. If you use the online debugging function, you need to set DEBUG in the system configuration register to ENABLE. When using debug mode, you need to pay attention to the following points: ◆... -
Page 269: Instruction Description
CMS80F751x Reference Manual 33. Instruction Description Assembly instructions include 5 categories: Arithmetic operations, logic operations, data transfer operations, Boolean operations and program branch instructions, All of these instructions are compatible with standard 8051. 33.1 Symbol Description Symbol Description Working register R0-R7 The unit address of the internal data memory RAM (00H-FFH) or the address in the special function register Direct Indirect internal or external RAM location addressed by register (@R0 or @R1) -
Page 270: List Of Instruction
CMS80F751x Reference Manual 33.2 List Of Instruction Instruction Description Operation type A,Rn Add register to accumulator. A,direct Add directly addressed data to accumulator. A,@Ri Add indirectly addressed data to accumulator. A,#data Add immediate data to accumulator. ADDC A,Rn Add register to accumulate or with carry. ADDC A,direct Add directly addressed data to accumulator with carry. - Page 271 CMS80F751x Reference Manual Instruction Description Clear accumulator. Complement accumulator. Rotate accumulator left. Rotate accumulator left through carry. Rotate accumulator right. Rotate accumulator right through carry. SWAP Swap nibbles within the accumulator. Data transmission type A,Rn Move register to accumulator. A,direct Move directly addressed data to accumulator.
- Page 272 CMS80F751x Reference Manual Instruction Description C,/bit OR complement of directly addressed bit to carry. C,bit Move directly addressed bit to carry flag. bit,C Move carry flag to directly addressed bit. Program jump type ACALL addr11 Absolute subroutine call in 2k address range LCALL addr16 Long subroutine call in 64k address range...
-
Page 273: Revision History
CMS80F751x Reference Manual 34. Revision History Modify content Revision Date V1.00 October 2019 initial version V1.01 June 2020 Update font and temperature sensor chapter description Modify the title of 2.3 and reset value of some registers, and V1.02 February 2021 delete the default GPIO function of PxnCFG V1.03 June 2021...
Need help?
Do you have a question about the CMS80F751 Series and is the answer not in the manual?
Questions and answers