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BAT32A237
Cmsemicon BAT32A237 Manuals
Manuals and User Guides for Cmsemicon BAT32A237. We have
2
Cmsemicon BAT32A237 manuals available for free PDF download: User Manual
Cmsemicon BAT32A237 User Manual (1066 pages)
Ultra-low power 32-bit microcontrollers based on ARM Cortex-M0+
Brand:
Cmsemicon
| Category:
Microcontrollers
| Size: 26 MB
Table of Contents
Documentation Instructions
2
Table of Contents
3
Chapter 1 CPU
22
Overview
22
Cortex-M0+ Core Features
22
Debug Features
22
SWD Interface Pins
24
ARM Reference Documents
25
Chapter 2 Pin Function
26
Port Function
26
Port Multiplexing Feature
26
Registers for Controlling Port Functions
27
Port Mode Register (Pmxx)
29
Port Register (Pxx)
30
Pull-Up Resistor Selection Register (Puxx)
31
Port Input Mode Register (Pimxx)
32
Port Output Mode Register (Pomxx)
33
Port Mode Control Register (Pmcxx)
34
Peripheral I/O Redirection Register 0 (PIOR0)
35
Peripheral I/O Redirection Register 1 (PIOR1)
37
Peripheral I/O Redirection Register 2 (PIOR2)
38
Peripheral I/O Redirection Register 3 (PIOR3)
39
Handling of Unused Pins
40
Register Settings When Using Multiplexing Function
41
Basic Concept When Using Multiplexing Function
41
Examples of Register Settings for Used Port Functions and Multiplexing Functions
42
Chapter 3 System Architecture
52
Overview
52
Flash Memory
52
System Address Partitioning
53
Chapter 4 Clock Generator
55
Function of Clock Generation Circuit
55
Configuration of Clock Generation Circuit
57
Registers for Controlling Clock Generation Circuit
60
Clock Operation Mode Control Register (CMC)
61
System Clock Control Register (CKC)
63
Clock Operation Status Control Register (CSC)
65
Oscillation Stabilization Time Counter Status Register (OSTC)
66
Oscillation Stabilization Time Select Register (OSTS)
68
Peripheral Enable Registers 0, 1 (PER0, PER1)
70
Subsystem Clock Supply Mode Control Register (OSMC)
75
High-Speed On-Chip Oscillator Frequency Select Register (HOCODIV)
76
High-Speed On-Chip Oscillator Trimming Register (HIOTRM)
77
System Clock Oscillation Circuit
78
X1 Oscillation Circuit
78
XT1 Oscillation Circuit
78
High-Speed On-Chip Oscillator
82
Low-Speed On-Chip Oscillator
82
Operation of Clock Generation Circuit
83
Clock Control
85
Example of Setting up a High-Speed On-Chip Oscillator
85
Example of Setting X1 Oscillation Circuit
87
Example of Setting XT1 Oscillation Circuit
88
CPU Clock Status Transition Diagram
89
Condition before Changing CPU Clock and Processing after Changing CPU Clock
95
Time Required to Switch CPU Clock and Main System Clock
97
Conditions before Clock Oscillation Is Stopped
98
Chapter 5 Hardware Divider
99
Features
99
Feature Description
99
Registers for Hardware Divider
99
Dividend Register (DIVIDEND)
100
Divisor Register (DIVISOR)
100
Quotient Register (QUOTIENT)
100
Remainder Register (REMAINDER)
100
Status Register (STATUS)
101
Universal Timer Unit (Timer4)
102
Function of Universal Timer Unit
104
Independent Channel Operation
104
Multi-Channel Linkage Operation Functions
106
8-Bit Timer Operation Function (Channels 1 and 3 of Unit 0 Only)
107
LIN-Bus Support (Channel 3 of Unit 0 Only)
107
Structure of Universal Timer Unit
108
List of Universal Timer Unit Register
111
Timer Count Register Mn (Tcrmn)
112
Timer Data Register Mn (Tdrmn)
114
Register for Controlling Universal Timer Unit
115
Peripheral Enable Register 0 (PER0)
116
Timer Clock Select Register M (Tpsm)
117
Timer Mode Register Mn (Tmrmn)
120
Timer Status Register Mn (Tsrmn)
124
Timer Channel Enable Status Register M (Tem)
125
Timer Channel Start Register M (Tsm)
126
Timer Channel Stop Register M (Ttm)
127
Timer Input-Output Selection Register (TIOS0, TIOS1)
128
Timer Output Enable Register M (Toem)
130
Timer Output Register M (Tom)
131
Timer Output Level Register M (Tolm)
132
Timer Output Mode Register M (Tomm)
133
Input Switch Control Register (ISC)
134
Noise Filter Enable Register (NFEN1)
135
Registers for Controlling Port Functions of Timer Input/Output Pins
136
Basic Rules of Universal Timer Unit
137
Basic Rules of Multi-Channel Linkage Operation Function
137
Basic Rules of 8-Bit Timer Operation Function (Channels 1 and 3 Only)
139
Operation of Counter
140
Count Clock (FTCLK )
140
Start Timing of Counter
142
Operation of Counter
143
Control of Channel Output (Tomn Pin)
148
Configuration of Tomn Pin Output Circuit
148
Output Settings for Tomn Pins
149
Cautions for Channel Output Operation
150
One-Time Operation of Tomn Bit
154
Timer Interrupt and Tomn Pin Output When Counting Starts
155
Control of Timer Input (Timn)
156
Structure of Timn Pin Input Circuit
156
Noise Filter
156
Cautions on Channel Input Operation
157
Independent Channel Operation Function of Universal Timer Unit
158
Operation as Interval Timer/Square Wave Output
158
Operation as External Event Counter
162
Operation as Frequency Divider (Only for Channel 0 of Unit 0)
165
Operation as Input Pulse Interval Measurement
169
Operation as Voltage High and Low Level Width Measurement of Input Signal
172
Operation
175
Operation as Delay Counter
176
Multi-Channel Coordinated Operation Function for Universal Timer Unit
179
Operation as Single Trigger Pulse Output Function
179
Operation as PWM Function
186
Operation as Multiple PWM Output Function
192
Cautions When Using a Universal Timer Unit
200
Cautions on Using Timer Output
200
Chapter 7 Timer a
201
Function of Timer a
201
Structure of Timer a
202
Registers for Controlling Timer a
203
Peripheral Enable Register 1 (PER1)
203
Subsystem Clock Supply Mode Control Register (OSMC)
204
Timer a Count Register 0 (TA0)
205
Timer a Control Register 0 (TACR0)
206
Timer AI/O Control Register 0 (TAIOC0)
207
Timer a Control Register 0 (TAMR0)
209
Timer a Event Pin Selection Register 0 (TAISR0)
210
Port Mode Register X (Pmx)
211
Operation of Timer a
212
Rewriting the Reload Register and Counter
212
Timer Mode
213
Pulse Output Mode
214
Event Counter Mode
215
Pulse Width Measurement Mode
216
Pulse Period Measurement Mode
217
Collaboration with EVENTC
218
Output Settings for each Mode
218
Cautions When Using Timer a
219
Start and Stop Control of Counting
219
Flag Access (TEDGF Bit and TUNDF Bit of TACR0 Register)
219
Access to a Counter Register
219
Change in Mode
219
Setting Procedure for TAO Pin and TAIO Pin
220
When Timer a Is Not Used
220
Stop of Timer a Operation Clock
220
Setting Steps for Deep Sleep Mode (Event Counter Mode)
221
Function Limitations in Deep Sleep Mode (Event Counter Mode Only)
221
Forced Count Stop Via the TSTOP Bit
221
Digital Filters
221
IL as the Count Source
221
Chapter 8 Timer B
222
Function of Timer B
222
Structure of Timer B
223
Registers for Controlling Timer B
224
Peripheral Enable Register 1 (PER1)
225
Timer B Mode Register (TBMR)
226
Timer B Count Control Register (TBCNTC)
227
Timer B Control Register (TBCR)
228
Timer B Interrupt Enable Register (TBIER)
229
Timer B Status Register (TBSR)
230
Timer BI/O Control Register (TBIOR)
232
Timer B Counter (TB)
234
Timer B General Registers A, B, C, D
235
Port Register and Port Mode Register
237
Operation of Timer B
238
Common Matters Relating to Multiple Modes and Functions
238
Digital Filter
241
Timer Mode (Input Capture Function)
243
Input Selection
244
Timer Mode (Output Compare Function)
246
PWM Mode
250
Phase Counting Mode
254
Timer B Interrupt
257
Cautions on Using Timer B
259
Phase Difference, Overlap and Pulse Width in Phase Counting Mode
259
Mode Switching
259
Switching of Counting Sources
259
Set-Up Steps for TBIO0 and TBIO1 Pins
260
External Clocks TBCLK0 and TBCLK1
260
Read and Write Access to SFR
261
Input Capture Operation When Stopping Count
261
Chapter 9 Timer C
262
Function of Timer C
262
Structure of Timer C
263
Registers for Controlling Timer C
264
Peripheral Enable Register 1 (PER1)
264
Timer C Count Register (TC)
265
Timer C Count Buffer Register (TCBUF)
265
Timer C Control Register 1 (TCCR1)
266
Timer C Control Register 1 (TCCR2)
267
Timer C Status Register (TCSR)
268
Operation of Timer C
269
Count Source
269
Starting the Counting of Timer C
269
Setting and Action of Triggering with Timer M Signal
270
Setting and Action for Software Triggering
271
Actions to Stop Timer C Counting
272
Setting and Action When Selecting Comparator 1 as the Trigger
272
Setting and Action for Software Triggering
272
Input Capture Action
273
Timer C Count Reset Action
274
Timer C Interrupt
276
Cautions on Using Timer C
277
Register Reading and Writing
277
Overflow Interrupt
277
Input Capture and Timer C Count Reset Action
277
Steps for Timer C and Timer M, Comparator 1 Linkage
277
Chapter 10 Timer M
278
Function of Timer M
278
Structure of Timer M
279
Registers for Controlling Timer M
280
Peripheral Enable Register 1 (PER1)
281
Timer M EVENTC Register (TMELC)
282
Timer M Start Register (TMSTR)
283
Timer M Mode Register (TMMR)
284
Timer M PWM Function Selection Register (TMPMR)
285
Timer M Function Control Register (TMFCR)
286
Timer M Output Master Enable Register 1 (TMOER1)
287
Timer M Output Master Enable Register 2 (TMOER2)
288
Timer M Output Control Register (TMOCR)
289
Timer M Digital Filter Function Selection Register I (Tmdfi) (I=0,1)
292
Timer M Control Register I (Tmcri) (I=0,1)
294
Timer M I/O Control Register Ai(Tmiorai) (I=0,1)
299
Timer M I/O Control Register CI(Tmiorci) (I=0,1)
301
Timer M Status Register 0 (TMSR0)
303
Timer M Status Register 1 (TMSR1)
307
Tmer M Interrupt Enable Register I (Tmieri) (I=0,1)
311
Timer MPWM Function Output Level Control Register I (Tmpocri) (I=0,1)
312
Timer M Counter I (Tmi) (I=0,1)
313
Timer M General Register Ai, Bi, CI, DI (Tmgrai, Tmgrbi, Tmgrci, Tmgrdi) (I=0,1)
315
Port Mode Registers (Pmxx, Pmcxx)
324
Matters Common to Multiple Modes
325
Count Source
325
Buffer Operation
326
Synchronous Operation
329
Forced Cutoff of Pulse Output
330
Events Input from the Event Linkage Controller (EVENTC)
332
Events Output to Event Link Controller (Eventc)/Direct Memory Access (DMA)
333
Operation of Timer M
334
Input Capture Function
334
Operation Example
337
Output Compare Function
339
PWM Function
346
Reset Synchronous PWM Mode
350
Complementary PWM Mode
354
PWM3 Mode
359
Timer M Interrupt
362
Cautions on Using Timer M
364
Read and Write Access to SFR
364
Mode Switching
365
Count Source
365
Input Capture Function
365
Set-Up Steps for Tmioai, Tmiobi, Tmioci, Tmiodi Pins (I=0,1)
365
External Clock TMCLK
367
Complementary PWM Mode
367
Pwmop
372
Function of PWMOP
373
PWMOP Registers
373
Operation of PWMOP
379
Output Force Cut-Off
379
Hardware Release (HS_SEL=0)
380
Software Release (HS_SEL=1)
389
Hazard Countermeasures
395
Output Forced Cutoff Source Detected and Not Detected States
396
Timing Diagram When the Counter Value of Timer M Reaches 0000H
397
Configuration Steps
399
Cautions
400
Chapter 11 Real-Time Clock
401
Function of Real-Time Clock
401
Structure of Real-Time Clock
401
Registers for Controlling Real-Time Clock
403
Peripheral Enable Register 0 (PER0)
404
Real-Time Clock Selection Register (RTCCL)
405
Real-Time Clock Control Register 0 (RTCC0)
406
Real-Time Clock Control Register 1 (RTCC1)
407
Clock Error Correction Register (SUBCUD)
409
Second Count Register (SEC)
410
Minute Count Register (MIN)
410
Hour Count Register (HOUR)
411
Day Count Register (DAY)
413
Week Count Register (WEEK)
414
Month Count Register (MONTH)
415
Year Count Register (YEAR)
415
Alarm Minute Register (ALARMWM)
416
Alarm Hour Register (ALARMWH)
416
Alarm Week Register (ALARMWW)
416
Port Mode Register and Port Register
417
Operation of Real-Time Clock
418
Starting Operation of Real-Time Clock
418
Shifting to Sleep Mode after Starting Operation
419
Reading/Writing Real-Time Clock
420
Setting Alarm of Real-Time Clock
422
Hz Output of Real-Time Clock
423
Example of Watch Error Correction of Real-Time Clock
424
Chapter 12 15-Bit Interval Timer
426
Function of 15-Bit Interval Timer
426
Structure of 15-Bit Interval Timer
426
Registers for Controlling 15-Bit Interval Timer
427
Peripheral Enable Register 0 (PER0)
427
Real-Time Clock Selection Register (RTCCL)
428
15-Bit Interval Timer Control Register (ITMC)
429
15-Bit Interval Timer Operation
430
15-Bit Interval Timer Operation Timing
430
Start of Count Operation and Re-Enter to Sleep Mode after Returned from Sleep Mode
431
Chapter 13 Clock Output/Buzzer Output Controller
432
Function of Clock Output/Buzzer Output Controller
432
Structure of Clock Output/Buzzer Output Controller
433
Registers for Control Clock Output/Buzzer Output Controller
433
Clock Output Select Registers N (Cksn)
433
Register Controlling Port Functions of Pins to be Used for Clock or Buzzer Output
435
Operation of Clock Output/Buzzer Output Controller
436
Operation of Output Pins
436
Cautions of Clock Output/Buzzer Output Controller
436
Chapter 14 Watchdog Timer
437
Function of Watchdog Timer
437
Structure of Watchdog Timer
437
Registers for Controlling Watchdog Timer
439
Watchdog Timer Enable Register (WDTE)
439
LOCKUP Control Register (LOCKCTL) and Its Protection Register (PRCR)
440
WDTCFG Configuration Register (WDTCFG0/1/2/3)
441
Operation of Watchdog Timer
442
Operation Control of Watchdog Timer
442
Setting Overflow Time of Watchdog Timer
444
Setting Window Open Period of Watchdog Timer
445
Setting of Watchdog Timer Interval Interrupt
446
Operation of the Watchdog Timer Without WDTCFG Configured
446
Chapter 15 A/D Converter
447
Function of A/D Converter
447
Registers for Controlling A/D Converter
449
Peripheral Enable Register 0 (PER0)
450
A/D Converter Mode Register 0 (ADM0)
451
A/D Converter Mode Register 1 (ADM1)
456
A/D Converter Mode Register 2 (ADM2)
457
A/D Converter Trigger Mode Register (ADTRG)
458
Analog Input Channel Specification Register (ADS)
459
12-Bit A/D Conversion Result Register (ADCR)
461
8-Bit A/D Conversion Result Register (ADCRH)
462
Conversion Result Comparison Upper Limit Setting Register (ADUL)
463
Conversion Result Comparison Lower Limit Setting Register (ADLL)
463
A/D Converter Sampling Time Control Register (ADNSMP)
464
A/D Converter Sampling Time Extension Control Register (ADSMPWAIT)
465
A/D Test Register (ADTES)
466
A/D Status Register (ADFLG)
467
A/D Converters Charge/Discharge Control Register (ADNDIS)
468
Registers for Controlling Port Functions of Analog Input Pins
469
Input Voltage and Conversion Results
470
Operation Mode of A/D Converter
471
Software Trigger Mode (Select Mode, Continuous Conversion Mode)
471
Software Trigger Mode (Select Mode, Single Conversion Mode)
472
Software Trigger Mode (Scan Mode, Sequential Conversion Mode)
473
Software Trigger Mode (Scan Mode, Single Conversion Mode)
474
Hardware Trigger No-Wait Mode (Select Mode, Sequential Conversion Mode)
475
Hardware Trigger No-Wait Mode (Select Mode, Single Conversion Mode)
476
Hardware Trigger No-Wait Mode (Scan Mode, Sequential Conversion Mode)
477
Hardware Trigger No-Wait Mode (Scan Mode, Single Conversion Mode)
478
Hardware Trigger Wait Mode (Select Mode, Sequential Conversion Mode)
479
Hardware Trigger Wait Mode (Select Mode, Single Conversion Mode)
480
Hardware Trigger Wait Mode (Scan Mode, Sequential Conversion Mode)
481
Hardware Trigger Wait Mode (Scan Mode, Single Conversion Mode)
482
A/D Converter Setup Flowchart
483
Setting up Software Trigger Mode
483
Setting up Hardware Trigger No-Wait Mode
484
Setting up Hardware Trigger Wait Mode
485
Setup When Temperature Sensor Output Voltage/Internal Reference Voltage Is Selected
486
Setting up Test Mode
487
Chapter 16 D/A Converter
488
Function of D/A Converter
488
Structure of D/A Converter
489
Registers for Controlling D/A Converter
490
Peripheral Enable Register 1 (PER1)
490
D/A Converter Mode Register (DAM)
491
D/A Conversion Value Setting Register I(Dacsi) (I=0,1)
491
Event Output Destination Select Register N(Elselrn), N=00~21
492
Registers for Controlling Port Functions of Analog Input Pins
492
Operation of D/A Converter
493
Operation in Normal Mode
493
Operation in Real-Time Output Mode
494
D/A Conversion Output Timing
495
Cautions on Using the D/A Converter
496
Chapter 17 Comparator
497
Function of Comparator
497
Structure of Comparator
498
Registers for Controlling the Comparator
500
Peripheral Enable Register 1 (PER1)
501
Comparator Mode Setting Register (COMPMDR)
502
Comparator Filter Control Register (COMPFIR)
503
Comparator Output Control Register (COMPOCR)
505
Comparator Built-In Reference Voltage Control Register (CVRCTL)
507
Comparator Built-In Reference Voltage Selection Register (Cirvm)
508
Comparator 0 Input Signal Selection Control Register (CMPSEL0)
509
Comparator 1 Input Signal Selection Control Register (CMPSEL1)
510
Registers for Controlling Port Functions of Analog Input Pins
511
Operation Instructions
512
Comparator I Digital Filter (I=0, 1)
514
Comparator I Interrupt (I=0, 1)
514
Event Signal Output to the Linkage Controller (EVENTC)
515
Output of Comparator I (I=0,1)
516
Stopping or Supplying Comparator Clock
516
Chapter 18 Programmable Gain Amplifier
517
Function of Programmable Gain Amplifier
517
Structure of Programmable Gain Amplifier
518
Registers for Controlling Programmable Gain Amplifier
519
Peripheral Enable Register 1 (PER1)
519
Programmable Gain Amplifier Control Register
520
Registers for Controlling Port Functions of Analog Input Pins
520
Operation of Programmable Gain Amplifier
521
Starting Operation Steps of Programmable Gain Amplifier
521
Stopping Operation Steps of Programmable Gain Amplifier
522
Chapter 19 Universal Serial Communication Unit
523
Function of Universal Serial Communication Unit
525
3-Wire Serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20,SSPI21)
525
Uart (Uart0~Uart2)
526
Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21)
527
Structure of Universal Serial Communication Unit
528
Shift Register
531
Lower 8/9 Bits of the Serial Data Register Mn (Sdrmn)
531
Registers for Controlling Universal Serial Communication Unit
533
Peripheral Enable Register 0 (PER0)
534
Serial Clock Select Register M (Spsm)
535
Serial Mode Register Mn (Smrmn)
536
Serial Communication Run Setting Register Mn (Scrmn)
538
Serial Data Register Mn (Sdrmn)
540
Serial Flag Clear Trigger Register Mn (Sirmn)
542
Serial State Register Mn (Ssrmn)
543
Serial Channel Start Register M (Ssm)
545
Serial Channel Stop Register M (Stm)
546
Serial Channel Enable Status Register M (Sem)
547
Serial Output Enable Register M (Soem)
548
Serial Output Register M (Som)
549
Serial Output Level Register M (Solm)
550
Input Switch Control Register (ISC)
552
Noise Filter Enable Register 0 (NFEN0)
553
Registers for Controlling Port Functions of Serial Input/Output Pins
554
Operation Stop Mode
555
Stopping the Operation by Units
555
Stopping the Operation by Channels
556
3-Wire Serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) Communication
557
Master Transmission
558
Register Settings
559
Master Reception
567
Register Setting
568
Master Transmission/Reception
576
Slave Transmission
584
Register Setting
585
Slave Reception
592
Slave Transmission/Reception
598
Calculation of Transmission Clock Frequency
607
Procedure for Handling Errors During 3-Wire I/O Communication
609
Sspi20, Sspi21)
609
Operation of Clock-Synchronous Serial Communication with Slave Selection Input Function
610
Slave Transmission
613
Register Setting
614
Slave Reception
623
Slave Transmission and Reception
630
Register Setting
631
Calculation of Transmission Clock Frequency
640
Selection Input Function
641
Operation of UART (UART0~UART2) Communication
642
UART Transmission
643
Register Setting
644
UART Reception
652
Process Flow
657
Calculation of Baud Rate
659
Handling Steps When an Error Occurs During UART (UART0~UART2) Communication
663
Communication
663
Operation of LIN Communication
664
LIN Transmission
664
LIN Reception
667
Communication (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21)
672
Address Field Transmission
673
Data Transmission
678
Data Reception
681
Generation of Stop Conditions
685
Calculation of Transfer Rate
686
Processing Steps When an Error Occurs in a Simplified I
688
C (Iic00, Iic01, Iic10, Iic11, Iic20, Iic21)
688
Communication
688
Chapter 20 Serial Interface IICA
689
Function of Serial Interface IICA
689
Structure of Serial Interface IICA
692
IICA Shift Register N (Iican)
692
Slave Address Register N (Svan)
693
SO Latch
693
Wake-Up Control Circuit
693
Serial Clock Counter
693
Interrupt Request Signal Generation Circuit
693
Serial Clock Control Circuit
693
Serial Clock Waiting Control Circuit
693
Ack Generation Circuit, Stop Condition Detection Circuit, Start Condition Detection Circuit, Ack Detection Circuit
694
Data Hold Time Correction Circuit
694
Start Condition Generation Circuit
694
Stop Condition Generation Circuit
694
Bus Status Detection Circuit
694
Registers for Controlling Serial Interface IICA
695
Peripheral Enable Register 0 (PER0)
696
IICA Control Register N0 (Iicctln0)
696
IICA Status Register N (Iicsn)
701
Master and Slave
702
IICA Flag Register N (Iicfn)
704
IICA Control Register N1 (Iicctln1)
706
IICA Low Level Width Setting Register N (Iicwln)
708
IICA High Level Width Setting Register N (Iicwhn)
708
Port Mode Register X (Pmx)
709
Functions of I
710
Pin Structure
710
Setting Transfer Clock Via Iicwln and Iicwhn Registers
711
Definition and Control Method of I C Bus
713
Start Condition
713
Address
714
Transfer Direction Specification
714
Acknowledge (ACK)
715
Stop Condition
716
Wait
717
Waitinging Release Method
719
Generation Timing and Waiting Control of Interrupt Requests (Intiican)
720
Detection Method for Address Matching
721
Error Detection
721
Extension Code
722
Arbitration
723
Wake-Up Function
725
Communication Reservation
728
Cautions
732
Communication Operation
733
Master Operation in Multi-Master System
735
Timing of I C Interrupt Request (Intiican) Generation
741
Operation When Arbitration Loss Occurs (no Communication after Arbitration Loss)
755
Timing Diagram
762
Chapter 21 CAN Controller
778
Overview
778
Features
778
Overview of Functions
779
Configuration
780
CAN Protocol
781
Frame Format
781
Frame Types
782
Data Frame and Remote Frame
782
Error Frame
789
Overload Frame
790
Functions
791
Bus Priority Configuration
791
Bit Stuffing
791
Multi Masters
791
Multi Cast
791
CAN Sleep Mode/Can Stop Mode Function
791
Error Control Function
792
Baud Rate Control
797
Connection with Target System
801
Internal Registers of CAN Controller
802
CAN Controller Configuration
802
Register Access Type
804
Register Bit Configuration
813
Bit Set/Clear Function
817
Control Registers
819
Peripheral Clock Select Register (PER0)
819
CAN Global Module Control Register (C0GMCTRL)
820
CAN Global Module Clock Select Register (C0GMCS)
822
CAN Global Automatic Block Transmission Control Register (C0GMBT)
823
CAN Global Automatic Block Transmission Delay Setting Register (C0GMABTD)
825
CAN Module Mask Register (C0Maskal, C0Maskah) (a = 1, 2, 3, or 4)
826
CAN Module Control Register (C0CTRL)
828
CAN Module Last Error Code Register (C0LEC)
832
CAN Module Information Register (C0INFO)
833
CAN Module Error Counter Register (C0ERC)
834
CAN Module Interrupt Enable Register (C0IE)
835
CAN Module Interrupt Status Register (C0INS)
837
CAN Module Bit Rate Prescaler Register (C0BRP)
838
CAN Module Bit Rate Register (C0BTR)
839
CAN Module Last In-Pointer Register (C0LIPT)
841
CAN Module Receive History List Register (C0RGPT)
842
CAN Module Last Out-Pointer Register (C0LOPT)
844
CAN Module Transmit History List Register (C0TGPT)
845
CAN Module Time Stamp Register (C0TS)
847
CAN Message Data Byte Register (C0Mdbxm) (X = 0 to 7), (C0Mdbzm) (Z = 01, 23, 45, 67)
849
CAN Message Data Length Register M (C0Mdlcm)
851
CAN Message Configuration Register (C0Mconfm)
852
CAN Message ID Register M (C0Midlm and C0Midhm)
854
CAN Message Control Register M (C0Mctrlm)
855
Serial Communication Pin Select Register 1 (PIOR3)
858
Port Mode Registers 0, 5 (PM0, PM5)
858
CAN Controller Initialization
859
CAN Module Initialization
859
Initialization of Message Buffer
859
Redefinition of Message Buffer
859
Transition from Initialization Mode to Operation Mode
861
Resetting Error Counter C0ERC of CAN Module
861
Message Reception
862
Receive Data Read
863
Receive History List Function
864
Mask Function
866
Multi-Buffer Receive Block Function
867
Remote Frame Reception
868
Message Transmission
869
Transmit History List Function
871
Automatic Block Transmission (ABT)
873
Transmission Abort Handling
875
Remote Frame Transmission
876
Power Save Modes
877
CAN Sleep Mode
877
CAN Stop Mode
879
Example of Using Power Saving Modes
880
Interrupt Function
881
Diagnostic Functions and Special Operational Modes
882
Receive-Only Mode
882
Single-Shot Mode
884
Self-Test Mode
885
Receive/Transmit Operation in each Operation Mode
886
Time Stamp Function
887
Baud Rate Setting
889
Representative Examples of Baud Rate Settings
893
Operation of CAN Controller
897
Chapter 22 Irda
922
Function of Irda
922
Registers for Controlling Irda
923
Peripheral Enable Register 0 (PER0)
923
Irda Control Register (IRCR)
924
Operation of Irda
925
Procedure for Irda Communication
925
Transmission
926
Reception
926
Selection of High Level Pulse Width
927
Cautions When Using Irda
928
Chapter 23 Enhanced DMA
929
Function of DMA
929
Structure of DMA
931
Internal Bus
931
Registers for Controlling DMA
932
Assignment of DMA Control Data Area and DMA Vector Table Area
933
Controlling Data Assignment
934
Vector Table
936
Peripheral Enable Register 1 (PER1)
938
DMA Control Register J(Dmacrj) (J=0~39)
939
DMA Block Size Register J(Dmblsj) (J=0~39)
940
DMA Transfer Count Register J(Dmactj) (J=0~39)
941
DMA Transfer Count Reload Register J (Dmrldj) (J=0~39)
942
DMA Source Address Register J(Dmsarj) (J=0~39)
943
DMA Destination Address Register J(Dmdarj) (J=0~39)
943
DMA Start Enable Register I (Dmaeni) (I=0~4)
944
DMA Base Address Register (DMABAR)
946
Operation of DMA
947
Start Source
947
Normal Mode
948
Repeat Mode
951
Chain Transfer
955
Cautions When Using DMA
957
DMA Control Data and Vector Table Settings
957
Assignment of DMA Control Data Area and DMA Vector Table Area
957
Number of Execution Clocks for DMA
958
Response Time for DMA
959
Start Source for DMA
959
Operation in Standby Mode
960
Chapter 24 Coordination Controller (EVENTC)
961
Function of EVENTC
961
Structure of EVENTC
961
Control Registers
962
Event Output Destination Select Register N(Elselrn) (N=00~21)
963
Operation of EVENTC
966
Chapter 25 Interrupt Function
968
Interrupt Function Types
968
Interrupt Source and Structure
969
Registers for Controlling Interrupt Function
975
Interrupt Request Flag Register (IF00~IF31)
975
Interrupt Mask Register (MK00~MK31)
976
External Interrupt Rising Edge Enable Register (EGP0, EGP1), External Interrupt Falling Edge Enable Register (EGN0, EGN1)
979
Operation of Interrupt Handling
981
Acceptance of Maskable Interrupt Requests
981
Acceptance of Unmaskable Interrupt Request
981
Chapter 26 Key Interrupt Function
982
Function of Key Interrupt
982
Structure of Key Interrupt
982
Registers for Controlling Key Interrupt
984
Key Return Mode Register (KRM)
984
Port Mode Register (Pmx)
985
Chapter 27 Standby Function
986
Standby Function
986
Sleep Mode
987
Sleep Mode Configuration
987
Exit from Sleep Mode
992
Deep Sleep Mode
993
Deep Sleep Mode Configuration
993
Deep Sleep Mode Release
996
Chapter 28 Reset Function
997
Reset Timing
999
Register for Confirming the Reset Source
1002
Reset Control Flag Register (RESF)
1002
Chapter 29 Power-On Reset Circuit
1004
Function of Power-On Reset Circuit
1004
Structure of Power-On Reset Circuit
1005
Operation of Power-On Reset Circuit
1006
Chapter 30 Voltage Detection Circuit
1009
Function of Voltage Detection Circuit
1009
Structure of Voltage Detection Circuit
1010
Registers for Controlling Voltage Detection Circuit
1011
Voltage Detection Register (LVIM)
1011
Voltage Detection Level Register (LVIS)
1012
Operation of Voltage Detection Circuit
1015
Settings When Used as Reset Mode
1015
Settings When Used as Interrupt Mode
1017
Settings When Used as Interrupt & Reset Mode
1019
Cautions on Voltage Detection Circuits
1025
Chapter 31 Safety Function
1027
Overview
1027
Registers Used by Safety Function
1028
Operation of Safety Functions
1028
Flash CRC Opration Function (High-Speed CRC)
1028
Flash CRC Control Register (CRC0CTL)
1029
Flash CRC Operation Result Register
1030
CRC Operation Function (Universal CRC)
1032
CRC Input Register (CRCIN)
1032
CRC Data Register (CRCD)
1033
RAM Parity Error Detection
1034
RAM Parity Error Control Register (RPECTL)
1034
SFR Guard Function
1036
SFR Guard Control Register (SFRGD)
1036
Frequency Detection Function
1037
Timer Input Select Register 0 (TIS0)
1038
A/D Test Function
1039
A/D Test Register (ADTES)
1041
Analog Input Channel Assignment Register (ADS)
1041
Digital Output Signal Level Detection Function for Input/Output Pins
1042
Port Mode Select Register (PMS)
1042
Product Unique Identification Register
1043
Chapter 32 Temperature Sensor
1044
Function of Temperature Sensor
1044
Registers for Temperature Sensor
1044
Temperature Sensor Calibration Data Register TSN25
1044
Temperature Sensor Calibration Data Register TSN125
1044
Instructions for Using the Temperature Sensor
1045
How Temperature Sensors Are Used
1045
How to Use Temperature Sensor
1046
Chapter 33 Option Bytes
1047
Function of Option Bytes
1047
User Option Bytes (000C0H~000C2H/010C0H~010C2H)
1047
Flash Data Protection Option Bytes (000C3H/010C3H, 50004H~500005H)
1048
Format of User Option Bytes
1049
Format of Flash Data Protection Option Bytes
1055
Chapter 34 FLASH Control
1056
FLASH Control Function Description
1056
FLASH Memory Structure
1056
Registers Controlling FLASH
1057
Flash Write Protection Register (FLPROT)
1057
FLASH Operation Control Register (FLOPMD1, FLOPMD2)
1058
Flash Erase Control Register (FLERMD)
1059
Flash Status Register (FLSTS)
1060
Flash Chip Erase Time Control Register (FLCERCNT)
1060
Flash Sector Erase Time Control Register (FLSERCNT)
1061
Flash Write Time Control Register (FLPROCNT)
1062
How to Operate FLASH
1063
Sector Erase
1063
Chip Erase
1064
Word Program
1064
Flash Read
1065
Cautions for FLASH Operation
1065
Appendix Revision History
1066
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Cmsemicon BAT32A237 User Manual (1037 pages)
Ultra-low power 32-bit microcontroller based on ARM Cortex-M0+
Brand:
Cmsemicon
| Category:
Microcontrollers
| Size: 25 MB
Table of Contents
Table of Contents
184
Symbol
188
Table
189
Register Name
206
Peripheral Enable Register 1
206
Timer a Control Register
206
Timer AI/O Control Register
206
Port Register
206
Port Mode Register
206
Figure
207
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