Renesas RZ/G1M User Manual
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Renesas RZ/G1M User Manual

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RZ/G1M
for Rich Graphics Applications
RZ/G Series
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp.
User's Manual: Hardware
Specifications of Individual RZ/G Series Product
Rev.1.00 Sep 2016

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Summary of Contents for Renesas RZ/G1M

  • Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp.
  • Page 2 Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures.
  • Page 3 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.
  • Page 4 Make sure to refer to the latest versions of these documents. Document Type Description Document Title Document No. User’s manual Overview of hardware, pin assignments, pin RZ/G1M User’s Manual: R01UH0626EJ0 for specifications multiplexing, and pin function controller Hardware 100 Rev.1.00 of individual (This user’s...
  • Page 5 3. Register Notation Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. All trademarks and registered trademarks are the property of their respective owners.

  • Page 6: Table Of Contents

    Contents 1. Overview ............................1-1 Introduction ................................1-1 System Configuration Diagram..........................1-2 List of Specifications ............................. 1-3 1.3.1 ARM Core ..............................1-3 1.3.2 CPU Core Peripherals ..........................1-4 1.3.3 External Bus Module ........................... 1-5 1.3.4 Internal Bus Module ............................ 1-7 1.3.5 Local Memory .............................
  • Page 7 5.3.15 Peripheral Function Select Register 5 (IPSR5) ..................5-28 5.3.16 Peripheral Function Select Register 6 (IPSR6) ..................5-29 5.3.17 Peripheral Function Select Register 7 (IPSR7) ..................5-30 5.3.18 Peripheral Function Select Register 8 (IPSR8) ..................5-31 5.3.19 Peripheral Function Select Register 9 (IPSR9) ..................5-32 5.3.20 Peripheral Function Select Register 10 (IPSR10) ..................

  • Page 8: Overview

    • CAN interface. Also, a full implementation of the extremely expandable and Internal AXI bus has been adopted for the RZ/G1M. This bus structure is optimized for maximum system performance, leading to the realization of high-performance and cost-effective premium in-vehicle infotainment systems.

  • Page 9: System Configuration Diagram

    SDRAM SDRAM Speed-pulse I/F SDHI (3 ch) DARC MMCIF (1 ch) TSIF (1 ch) DDR3- DDR3L- DBSC3 SDRAM SDRAM Crypto Engine (1 ch) (12 ch) SIM card TCON MFIS IR Receiver Figure 1.1 RZ/G1M System Configuration R01UH0626EJ0100 Rev.1.00 Sep 30,2016...

  • Page 10: List Of Specifications

    RZ/G1M 1. Overview List of Specifications 1.3.1 ARM Core Item Description  ARM Cortex-A15 Dual MPCore 1.5 GHz System CPU Cortex-A15  L1 I/D cache 32/32 Kbytes, L2 cache 1 Mbyte  NEON /VFPv4 supported  Security extension supported ARM debugger (CoreSight) ...

  • Page 11: Cpu Core Peripherals

    Pin function controller (PFC)  Setting multiplexed pin functions for LSI pins Function of the RZ/G1M pin selectable by setting the registers in the PFC module.  Module selection Enable and disable the functions of RZ/G1M LSI pins to which pin functions from multiple pin groups are assigned by setting the registers in the PFC module.

  • Page 12: External Bus Module

    RZ/G1M 1. Overview 1.3.3 External Bus Module Item Description  EX-BUS interface: max. 16-bit bus Local bus state controller  Frequency: 65 MHz (LBSC)  External area divided into several areas and managed — Allocation to space of area 0, area 1, and area 6 or allocation to space of area 0 only is selected at startup time.
  • Page 13 RZ/G1M 1. Overview Item Description  Three channels LBSC-DMAC  Address space: Physical address space  Transfer direction: Peripheral to memory (AXI-bus), memory (AXI-bus) to peripheral  Data packing for peripheral read data: Memory write data length is selectable as transfer data length to memory side.

  • Page 14: Internal Bus Module

    RZ/G1M 1. Overview 1.3.4 Internal Bus Module Item Description  On-chip main bus AXI-bus — Bus protocol : AXI3 with QoS control — Frequency: 260 MHz — Bus width: 256 bits/128 bits  On-chip CPU & GPU main bus — Corelink CCI-400 Cache Coherent Interconnect - r0p3 —...
  • Page 15 RZ/G1M 1. Overview Item Description  30 channels for ARM domain Direct memory access controller for system  Address space: 4 Gbytes on architecture (SYS-DMAC)  Data transfer length: Byte, word (2 bytes), longword (4 bytes), 8 bytes, 16 bytes, 32 bytes and 64 bytes ...

  • Page 16: Local Memory

    RZ/G1M 1. Overview Item Description Interrupt controller INTC-SYS — 10 interrupt pins which can detect external interrupts (INTC) — Fall/rise/high level/low level detection is selectable — On-chip peripheral interrupts: Priority can be specified for each module — Max. 384 shared peripheral interrupts supported —...
  • Page 17 RZ/G1M 1. Overview Item Description Display unit (DU) Display channel Two independently controllable channels Screen size and number of  Maximum screen size: 4095 × 2047 composite planes  Number of planes specifiable: 8 planes Note that possibility number of combined display depends on DCLK;...
  • Page 18 RZ/G1M 1. Overview Item Description  8-, 10-, or 12-bit YCbCr422 (CbYCrY format) Video input (VIN) Input data format  16-bit YCbCr422 (8-bit (Y) + 8-bit (CbCr) format)  20-bit YCbCr422 (10-bit (Y) + 10-bit (CbCr) format)  24-bit YCbCr422 (12-bit (Y) + 12-bit (CbCr) format) ...

  • Page 19: Video Processing

    Video Processing Item Description Video signal processor 1 The VSP1 is the successor IP of Renesas’ VIO6-IP series, and has the following features. (VSP1) (1) Supports various data formats and conversion — Supports YCbCr444/422/420, RGB, αRGB, αplane — Color space conversion and changes to the number of colors by dithering —...
  • Page 20 RZ/G1M 1. Overview Item Description Video processing unit The VCP3 is a multi-codec module which provides encoding and decoding capabilities on (VCP3) the basis of multiple video coding schemes, e.g., H.264/AVC, MPEG-4, MPEG-2 and VC-1. This IP (Intellectual Property) is a multi codec that processes the frame or each field by controlling software for VCP3 executed on host CPU.

  • Page 21: Sound Interface

    RZ/G1M 1. Overview Item Description  Supports conversion between various RGB formats. Image extraction direct memory access controller  Image extraction function: Capable of extracting an image and storing it as a separate (2D-DMAC) image in the RAM.  Image rotation/reversal function: Reverses an image vertically/horizontally or rotates it by 90°/270°.
  • Page 22 RZ/G1M 1. Overview Item Description  Volume control function including digital volume, volume ramp, and Digital volume and mute function zero-crossing mute (DVC)  The digital volume function is specified by a 24-bit fixed-point value within the range from 0 to 8 times (mute, or -120 to 18 dB) ...

  • Page 23: Storage

    RZ/G1M 1. Overview 1.3.9 Storage Item Description  Two channels (Host only 1 channel/Host-Function 1 channel selected)* USB2.0 host & function module  PHY integrated (USB2.0)  USB Host (EHCI/OHCI) 2LINK  Compliance with USB2.0  USB Function 1LINK  Compliance with USB2.0 (High-Speed) ...

  • Page 24: Network

    RZ/G1M 1. Overview 1.3.10 Network Item Description  Two channels CAN interface (CAN)  Supports CAN specification 2.0B  ISO-11898-1 compliant  Maximum bit rate: 1 Mbps  Message box — Normal mode: 32 receive-only mailboxes and 32 mailboxes for transmission/reception —...
  • Page 25 RZ/G1M 1. Overview Item Description  4-channels Timer pulse unit (TPU)  16-bit timers  Each channel outputs PWM  32-bit timer, two channels (16 bits/32 bits can be selected) Compare match timer 0 (CMT0)  Source clock: RCLK clock ...

  • Page 26: Peripheral Module

    RZ/G1M 1. Overview 1.3.12 Peripheral Module Item Description  Single channel for DVFS (open drain type IO buffer) I2C bus interface (IIC)  Two channels for general purpose  Supports single master transmission/reception  Interrupt request  DMAC request  Five channels for 3.3-V LVTTL buffers and single channel for Open drain type IO buffer...
  • Page 27 RZ/G1M 1. Overview Item Description  Six channels Serial communication Overall interface with FIFO specification  Asynchronous, clock-synchronized modes (SCIF)  Asynchronous serial communication mode The SCIF performs serial data communication based on a character-by- character asynchronous system. This feature enables serial data...
  • Page 28 RZ/G1M 1. Overview Item Description  Three channels Clock-synchronized serial interface with  Max. speed: 26 Mbps FIFO (MSIOF)  Internal 64-byte transmit FIFOs/internal 256-byte receive FIFOs  Supports master and slave modes  Internal prescaler  Supports serial formats: IIS, SPI (master and slave modes) ...

  • Page 29: Others

    RZ/G1M 1. Overview 1.3.13 Others Item Description JTAG JTAG interface for CoreSight Process 28-nm Si-CMOS Package FC-BGA2727-831 Power Supply Voltages and Temperature Range • Power supply voltage (typ.) 1.8 V: (ETM, SD, MMC, SATA, PCI Express, USB3.0, LVCMOS I/F, Xtal, JTAG, Trace and RST) 1.03 V: (core)

  • Page 30: Area Map

    RZ/G1M 2. Area Map 2. Area Map See section 2, Area Map in the RZ/G Series User’s Manual: Hardware. R01UH0626EJ0100 Rev.1.00 Sep 30,2016...

  • Page 31: Pin Assignment

    RZ/G1M 3. Pin Assignment 3. Pin Assignment Top View (Left) VDDQ_ VDDQ_ VDDQ_ M1DQ31 M1DQ29 M1DM3 M1DQ28 M1DQ17 M1DQ21 M1DQ3 M1DM0 M1DQ8 M1DQ9 M1DQ15 M0A8 M1A0 M1DQ24 M1DQ30 M1DQ16 M1DQ19 M1DQ23 M1DQ1 M1DQ0 M1DQ11 M1DQ13 M0A14 VDDQ_ M1BA1 M1A12 M1DQ26...

  • Page 32: Top View (Right)

    RZ/G1M 3. Pin Assignment Top View (Right) VDDQ_ VDDQ_ VDDQ_ M0A13 M0A11 M0CS1# M0A4 M0A2 M0DQ9 M0DQ15 M0DQ0 M0DM0 M0DQ3 M0DQ7 M0A6 M0A9 M0CS0# M0A7 M0A1 M0DQ8 M0DQ14 M0DQ12 M0DQ4 M0DQ5 M0DQ19 M0A10 M0CKE1 M0BA0 M0CAS# M0DQ10 M0DM1 M0DQ6 M0DQ1...

  • Page 33: Mode Pin Settings

    RZ/G1M 3. Pin Assignment Mode Pin Settings Input fixed values for the MPMD0, MPMD1, and BSMODE pins. These values cannot be changed after power is supplied. The values of pins MD0 to MD14, MD19 to MD24, MD27, MD28, MDT0 and MDT1 are input upon power-on reset using the PRESET# pin.
  • Page 34 RZ/G1M 3. Pin Assignment Master Boot Processor Selection Cortex-A15 boot Setting prohibited Setting prohibited Setting prohibited EXBUS Area 0 Data Bus Width 8-bit 16-bit EXTAL/XTAL Pin Setting Inputs an external clock to the EXTAL pin Connects a crystal resonator to the EXTAL/XTAL pin...
  • Page 35 RZ/G1M 3. Pin Assignment Internal External PLL3/ PLL3/ MD14 MD13 Clock Clock PLL1 PLL0 MD19: DDR3-1600 MD19: DDR3-1333 15 MHz × 1/1* × 208* × 172 × 106 (VCO = 1590 MHz) × 88 (VCO = 1320 MHz) 20 MHz ×...

  • Page 36: Pin Multiplexing

    4. Pin Multiplexing 4. Pin Multiplexing List of Multiplexed Pin Functions Table 4.1 lists the multiplexed pin functions of the RZ/G1M. The default pin function of each pin after power-on reset is "Function 1" respectively, unless otherwise mentioned in each table note.
  • Page 37 RZ/G1M 4. Pin Multiplexing Table 4.1 List of Multiplexed Pin Functions DBSC3 channel 0 (No.1 to 60): Single Function Function 1 Function 1 Function 1 Module During POR Module During POR Module During POR Pin No. Pin Name V/|IOH| Pin No. Pin Name V/|IOH| Pin No.
  • Page 38 RZ/G1M 4. Pin Multiplexing DBSC3 channel 0 (No.61 to 93): Single Function Function 1 Function 1 Function 1 Module During POR Module During POR Module During POR Pin No. Pin Name V/|IOH| Pin No. Pin Name V/|IOH| Pin No. Pin Name...
  • Page 39 RZ/G1M 4. Pin Multiplexing DBSC3 channel 1 (No.94 to 113): 3-Function Multiplexed These pins function and pin states during power-on reset depend on MD28, MD 27 and MD22 pins setting, and cannot be changed after power-on reset by software. Function 1...
  • Page 40 RZ/G1M 4. Pin Multiplexing DBSC3 channel 1 (No.114 to 133): 3-Function Multiplexed These pins function and pin states during power-on reset depend on MD28, MD 27 and MD22 pins setting, and cannot be changed after power-on reset by software. Function 1...
  • Page 41 RZ/G1M 4. Pin Multiplexing DBSC3 channel 1 (No.134 to 153): 3-Function Multiplexed These pins function and pin states during power-on reset depend on MD28, MD 27 and MD22 pins setting, and cannot be changed after power-on reset by software. Function 1...
  • Page 42 RZ/G1M 4. Pin Multiplexing DBSC3 channel 1 (No.154 to 173): 3-Function Multiplexed These pins function and pin states during power-on reset depend on MD28, MD 27 and MD22 pins setting, and cannot be changed after power-on reset by software. Function 1...
  • Page 43 RZ/G1M 4. Pin Multiplexing DBSC3 channel 1 (No.174 to 188): 3-Function Multiplexed These pins function and the pin state during power-on reset depend on MD28, MD 27 and MD22 pins setting, and cannot be changed after power-on reset by software.
  • Page 44 RZ/G1M 4. Pin Multiplexing CPG, RESET, SYSTEM, AVS, POWER ISO and Debug (No.189 to 212): Single Function Function 1 Function 1 Module During POR Module During POR Pin No. Pin Name V/|IOH| Pin No. Pin Name V/|IOH| Pull-up Pull-up(pull-down)* SYSTEM...
  • Page 45 RZ/G1M 4. Pin Multiplexing SATA, PCIEC and USB3.0 (No.213 to 254): 2-Function Multiplexed These pins function depends on the MD[24:23] pins setting, and cannot be changed after power-on reset by software. Function 1 Function 2 Function 1 Function 2 MD24=0...
  • Page 46 RZ/G1M 4. Pin Multiplexing USB 2.0 and DU/LVDS (No.255 to 292): Up to 2-Function Multiplexed These pins default function after power-on reset is USB2.0 and DU0 except for No.287 (DU0_DOTCLKIN). Function 1 GPIO Function 1 GPIO Module During POR Module During POR Pin No.
  • Page 47 RZ/G1M 4. Pin Multiplexing LBSC (D[15:0]) and GPIO (No.293 to 308): 3-Function Multiplexed These pins default function (function 1 or GPIO) after power-on reset depends on MD[3:1] pins setting. Function 1 Function 2 GPIO MD[3:1]  000 MD[3:1] = 000...
  • Page 48 RZ/G1M 4. Pin Multiplexing LBSC, MSIOF, I2C, PWM, MSIOF, and GPIO (No.309 to 324): Up to 7-Function Multiplexed and Mode Pins assigned (No.310 to 313, 316, 319, 322 to 324) These pins default function (function 1 or GPIO) after power-on reset depends on MD[3:1] pins setting.
  • Page 49 RZ/G1M 4. Pin Multiplexing LBSC, MSIOF, I2C, SCIFA, SCIFB, QSPI, SCIF, HSCIF, PWM, TPU, and GPIO (No.325 to 343): Up to 9- Function Multiplexed and Mode Pins assigned (No.328, 341, 343) These pins default function (function 1 or GPIO) after power-on reset depends on MD[3:1] pins setting. When MD[3:1] = 010, 100, 101 or 110, QSPI boot is executed after power-on reset and after that the GPIO is available.
  • Page 50 RZ/G1M 4. Pin Multiplexing LBSC, MSIOF, I2C, SCIFA, SCIFB, QSPI, SCIF, HSCIF, PWM, TPU, GPIO (No.344 to 360): Up to 9-Function Multiplexed and Mode Pins assigned (No.344, 345, 347, 348, 351) These pins default function (function 1 or GPIO) after power-on reset depends on MD[3:1] pins setting except for No.346 and 350 to 360 pins.
  • Page 51 RZ/G1M 4. Pin Multiplexing SSI, SCIF, HSCIF, MSIOF, TSIF, VIN, RCAN and GPIO (No.361 to 380): Up to 8-Function Multiplexed These pins are set for GPIO after power-on reset. For details, refer to GPSR2 register in section 5, Pin Function Controller (PFC).
  • Page 52 RZ/G1M 4. Pin Multiplexing ADG, MSIOF, SCIF, SCU, SCIFB, SCIFA, INTC, I2C, HSCIF, DU, RCAN and GPIO (No.381 to 395): Up to 8- Function Multiplexed and Mode Pin assigned (No.384) These pins are set for GPIO except for No.385 (NMI) after power-on reset. For details, refer to GPSR2 and GPSR7 registers in section 5, Pin Function Controller (PFC).
  • Page 53 RZ/G1M 4. Pin Multiplexing DU, VIN, SCIF, MSIOF, SSI, HSCIF, RCAN and GPIO (No.396 to 415): Up to 7-Function Multiplexed These pins are set for GPIO after power-on reset. For details, refer to GPSR3 register in section 5, Pin Function Controller (PFC).
  • Page 54 RZ/G1M 4. Pin Multiplexing DU, I2C, SCIF, SCIFA, RCAN, PWM, TSIF and GPIO (No.416 to 435): Up to 8-Function Multiplexed and Mode Pins assigned (No.417, 423, 426, 427) These pins are set for GPIO after power-on reset. For details, refer to GPSR3 and GPSR4 registers in section 5, Pin Function Controller (PFC).
  • Page 55 RZ/G1M 4. Pin Multiplexing VIN, I2C, HSCIF, SCIFB, LBSC, RCAN and GPIO (No.436 to 455): Up to 8-Function Multiplexed These pins are set for GPIO after power-on reset. For details, refer to GPSR4 register in section 5, Pin Function Controller (PFC).
  • Page 56 RZ/G1M 4. Pin Multiplexing VIN, EtherAVB, TSIF, I2C, RCAN, MSIOF, SCIFA, TMU and GPIO (No.456 to 475): Up to 8-Function Multiplexed These pins are set for GPIO after power-on reset. For details, refer to GPSR5 register in section 5, Pin Function Controller (PFC).
  • Page 57 RZ/G1M 4. Pin Multiplexing EtherMAC, EtherAVB, SCIFA, RCAN, MSIOF, TMU, SCIFB, PWM, SDHI, QSPI, MMC, USB2.0 and GPIO (No.476 to 495): Up to 9-Function Multiplexed These pins are set for GPIO after power-on reset except for QSPI pin during QSPI boot operation. For details, refer to GPSR5 and GPSR6 registers in section 5, PFC and section 18, Booting.
  • Page 58 RZ/G1M 4. Pin Multiplexing SDHI, PWM, TPU, I2C, MMC, SCIF, SCIFA and GPIO (No.496 to 514): Up to 6-Function Multiplexed These pins are set for GPIO after power-on reset. For details, refer to GPSR6 register in section 5, Pin Function Controller (PFC).
  • Page 59 RZ/G1M 4. Pin Multiplexing MSIOF, SCIF, VIN, MMC, I2C, IIC, RCAN, DU, ADG, PWM, SCIFA, HSCIF, SCIFB, TMU and GPIO (No.515 to 533): Up to 8-Function Multiplexed and Mode Pins assigned (No.521, 522) These pins are set for GPIO except for No.527 to 530 (I2C5 and IIC3 pins) after power-on reset. For details, refer to GPSR4, GPSR6 and GPSR7 registers in section 5, Pin Function Controller (PFC).
  • Page 60 RZ/G1M 4. Pin Multiplexing HSCIF, SCIFB, VIN, RCAN and GPIO (No.534 to 540): Up to 7-Function Multiplexed These pins are set for GPIO after power-on reset. For details, refer to GPSR7 register in section 5, Pin Function Controller (PFC). Function...
  • Page 61 RZ/G1M 4. Pin Multiplexing Thermal Sensor (No.541 to 562): Single Function Function 1 Function 1 Module During POR Module During POR Pin No. Pin Name V/|IOH| Pin No. Pin Name V/|IOH| Pull-up Pull-up Power Reserved AK16 1.8/3.3V/- Reserved 3.3V/16mA VDD_MLBPPLL0...

  • Page 62: Pin States

    RZ/G1M 4. Pin Multiplexing Pin States Table 4.2 is pin state of the RZ/G1M. [Legend] No.: Serial number, Pin No.: BGA package ball grid number, Pin Name: Pin name of function 1 in pin in Table 4.1, I/O: Input or output direction considered about all multiplexed pin functions of the pin.
  • Page 63 RZ/G1M 4. Pin Multiplexing Table 4.2 Pin States During Default Default Pin Name (Function 1) Default Pin Function State Pull-up M0CKE0 M0CKE0 M0CKE1 M0CKE1 M0BKPRST# M0BKPRST# M0RESET# M0RESET# H to L M0CK0 M0CK0 M0CK0# M0CK0# M0CK1 M0CK1 M0CK1# M0CK1# M0CS0#...
  • Page 64 RZ/G1M 4. Pin Multiplexing During Default Default Pin Name (Function 1) Default Pin Function State Pull-up M0DQ4 M0DQ4 M0DQ5 M0DQ5 M0DQ6 M0DQ6 M0DQ7 M0DQ7 M0DQS0 M0DQS0 M0DQS0# M0DQS0# M0DM0 M0DM0 VDDQ_M0DPLL0 VDDQ_M0DPLL0 VSSQ_M0DPLL0 VSSQ_M0DPLL0 M0VREFDQ0 M0VREFDQ0 M0DQ8 M0DQ8 M0DQ9 M0DQ9...
  • Page 65 RZ/G1M 4. Pin Multiplexing During Default Default Pin Name (Function 1) Default Pin Function State Pull-up M0DQ30 M0DQ30 M0DQ31 M0DQ31 M0DQS3 M0DQS3 M0DQS3# M0DQS3# M0DM3 M0DM3 VDDQ_M0DPLL3 VDDQ_M0DPLL3 VSSQ_M0DPLL3 VSSQ_M0DPLL3 VDDQ_M0BKUP VDDQ_M0BKUP M1CKE0 M1CKE0/GP_DDR1* M1CKE1 M1CKE1/GP_DDR2* M1VREFCA M1VREFCA M1BKPRST# M1BKPRST#...
  • Page 66 RZ/G1M 4. Pin Multiplexing During Default Default Pin Name (Function 1) Default Pin Function State Pull-up M1BA2 M1BA2/GP_DDR18* VDDQ_M1APLL VDDQ_M1APLL VSSQ_M1APLL VSSQ_M1APLL VDDQ_M1MPLL VDDQ_M1MPLL VSSQ_M1MPLL VSSQ_M1MPLL M1DQ0 M1DQ0/M0DQ32/Reserved* Z/Z/Z M1DQ1 M1DQ1/M0DQ33/Reserved* Z/Z/Z M1DQ2 M1DQ2/M0DQ34/Reserved* Z/Z/Z M1DQ3 M1DQ3/M0DQ35/Reserved* Z/Z/Z M1DQ4 M1DQ4/M0DQ36/Reserved*...
  • Page 67 RZ/G1M 4. Pin Multiplexing During Default Default Pin Name (Function 1) Default Pin Function State Pull-up VDDQ_M1DPLL2 VDDQ_M1DPLL2/VDDQ_M0DPLL6/VDDQ_M0DPLL6* VSSQ_M1DPLL2 VSSQ_M1DPLL2/VSSQ_M0DPLL6/VSSQ_M0DPLL6* M1VREFDQ1 M1VREFDQ1/M0VREFDQ3/M0VREFDQ3* M1DQ24 M1DQ24/M0DQ56/Reserved* Z/Z/Z M1DQ25 M1DQ25/M0DQ57/Reserved* Z/Z/Z M1DQ26 M1DQ26/M0DQ58/Reserved* Z/Z/Z M1DQ27 M1DQ27/M0DQ59/Reserved* Z/Z/Z M1DQ28 M1DQ28/M0DQ60/Reserved* Z/Z/Z M1DQ29 M1DQ29/M0DQ61/Reserved* Z/Z/Z...
  • Page 68 RZ/G1M 4. Pin Multiplexing During Default Default Pin Name (Function 1) Default Pin Function State Pull-up AL24 RIDN1_SATA RIDN1_SATA/RIDN1_PCIe* AL25 TODP1_SATA TODP1_SATA/TODP1_PCIe* AL26 TODN1_SATA TODN1_SATA/TODN1_PCIe* AJ26 CICREFP1_SATA CICREFP1_SATA/CICREFP1_PCIe* AJ25 CICREFN1_SATA CICREFN1_SATA/CICREFN1_PCIe* AE23 VSS_SATA1 VSS_SATA1/VSS_PCIe* AF24 VDDA_SATA1 VDDA_SATA1/VDDA_PCIe* AG24 VDDA_SATA1 VDDA_SATA1/VDDA_PCIe*...
  • Page 69 RZ/G1M 4. Pin Multiplexing During Default Default Pin Name (Function 1) Default Pin Function State Pull-up AG31 USB0_DP USB0_DP AH31 USB0_DM USB0_DM AG29 USB0_RREF USB0_RREF AE27 VD331 VD331 AD26 VD181 VD181 AB24 AVDD AVDD AC24 AVSS AVSS AF31 USB0_PWEN USB0_PWEN...
  • Page 70 RZ/G1M 4. Pin Multiplexing During Default Default Pin Name (Function 1) Default Pin Function State Pull-up D7/GP0_7* D8/GP0_8* D9/GP0_9* D10/GP0_10* D11/GP0_11* D12/GP0_12* D13/GP0_13* D14/GP0_14* D15/GP0_15* A0/GP0_16* I(MD28) A1/GP0_17* I(MD23) A2/GP0_18* I(MD13) A3/GP0_19* I(MD24) A4/GP0_20* A5/GP0_21* A6/GP0_22* I(MD27) A7/GP0_23* A8/GP0_24* A9/GP0_25*...
  • Page 71 RZ/G1M 4. Pin Multiplexing During Default Default Pin Name (Function 1) Default Pin Function State Pull-up EX_CS4# GP1_16 EX_CS5# I(MD8) GP1_17 I(MD10) BS#/GP1_18* I(MD12) RD#/GP1_19* RD/WR# GP1_20 WE0# I(MD6) WE0#/GP1_21* WE1# I(MD4) WE1#/GP1_22* EX_WAIT0 EX_WAIT0/GP1_23* DREQ0 GP1_24 DACK0 I(MD7) GP1_25...
  • Page 72 RZ/G1M 4. Pin Multiplexing During Default Default Pin Name (Function 1) Default Pin Function State Pull-up AL16 AE30 IRQ0 GP7_10 AE29 IRQ1 GP7_11 AD29 IRQ2 GP7_12 AD28 IRQ3 GP7_13 AC29 IRQ4 GP7_14 AC28 IRQ5 GP7_15 AC27 IRQ6 GP7_16 AB26 IRQ7...
  • Page 73 RZ/G1M 4. Pin Multiplexing During Default Default Pin Name (Function 1) Default Pin Function State Pull-up DU1_DISP I(MD1) GP3_30 DU1_CDE I(MD0) GP3_31 VI0_CLK GP4_0 VI0_CLKENB GP4_1 VI0_FIELD GP4_2 VI0_HSYNC# GP4_3 VI0_VSYNC# GP4_4 VI0_DATA0/VI0_B0 GP4_5 VI0_DATA1/VI0_B1 GP4_6 VI0_DATA2/VI0_B2 GP4_7 VI0_DATA3/VI0_B3 GP4_8...
  • Page 74 RZ/G1M 4. Pin Multiplexing During Default Default Pin Name (Function 1) Default Pin Function State Pull-up VI1_DATA7 GP5_12 ETH_MDIO GP5_13 ETH_CRS_DV GP5_14 ETH_RX_ER GP5_15 ETH_RXD0 GP5_16 ETH_RXD1 GP5_17 ETH_LINK GP5_18 ETH_REFCLK GP5_19 ETH_TXD1 GP5_20 ETH_TX_EN GP5_21 ETH_MAGIC GP5_22 ETH_TXD0 GP5_23...
  • Page 75 RZ/G1M 4. Pin Multiplexing During Default Default Pin Name (Function 1) Default Pin Function State Pull-up AK13 SD3_CD GP6_22 AJ13 SD3_WP GP6_23 AD13 VCCQ_SD3 VCCQ_SD3 MSIOF0_SCK GP6_24 MSIOF0_SYNC GP6_25 MSIOF0_TXD GP6_26 MSIOF0_RXD GP6_27 MSIOF0_SS1 GP6_28 MSIOF0_SS2 GP6_29 SIM0_RST I(MDT1) GP4_29...
  • Page 76 RZ/G1M 4. Pin Multiplexing During Default Default Pin Name (Function 1) Default Pin Function State Pull-up VDD_MLBPPLL1 VDD_MLBPPLL1 VSS_MLBPPLL1 VSS_MLBPPLL1 VCCQ18_MLBP VCCQ18_MLBP VCCQ18_MLBP VCCQ18_MLBP VCCQ33_MLBP VCCQ33_MLBP VCCQ33_MLBP VCCQ33_MLBP VTHSENSE0 VTHSENSE0 VTHREF0 VTHREF0 Notes: 1. No.94, 95, 98 to 106 and 108 to 129: Default Pin Function...

  • Page 77: Handling Of Unused Pins

    4. Pin Multiplexing Handling of Unused Pins Table 4.3 shows a handling of unused pins of the RZ/G1M. "Unused pin" means all modules that are multiplexed to the pin should be disable and unused in this section. For handling of some unused pin which belongs to the enable module should be handled following the notification of the module manual.
  • Page 78 RZ/G1M 4. Pin Multiplexing Table 4.3 Handling of Unused Pins Default Mode Default Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use M0CKE0 Open M0CKE1 Open Must be used M0BKPRST# Pulled-up to VDDQ_M0BKUP or pulled-down to VSS...
  • Page 79 RZ/G1M 4. Pin Multiplexing Default Mode Default Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use M0DQ4 Open M0DQ5 Open M0DQ6 Open M0DQ7 Open M0DQS0 Open M0DQS0# Open M0DM0 Open VDDQ_M0DPLL0 Must be used VSSQ_M0DPLL0 Must be used...
  • Page 80 RZ/G1M 4. Pin Multiplexing Default Mode Default Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use M0DQ30 Open M0DQ31 Open M0DQS3 Open M0DQS3# Open M0DM3 Open VDDQ_M0DPLL3 Must be used VSSQ_M0DPLL3 Must be used VDDQ_M0BKUP Must be used...
  • Page 81 RZ/G1M 4. Pin Multiplexing Default Mode Default Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use M1BA2 Open VDDQ_M1APLL Must be used VSSQ_M1APLL Must be used VDDQ_M1MPLL Must be used VSSQ_M1MPLL Must be used M1DQ0 Open...
  • Page 82 RZ/G1M 4. Pin Multiplexing Default Mode Default Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use VDDQ_M1DPLL2 Must be used VSSQ_M1DPLL2 Must be used M1VREFDQ1 Must be used M1DQ24 Open M1DQ25 Open M1DQ26 Open M1DQ27 Open...
  • Page 83 RZ/G1M 4. Pin Multiplexing Default Mode Default Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use AL24 RIDN1_SATA Open AL25 TODP1_SATA Open AL26 TODN1_SATA Open AJ26 CICREFP1_SATA Fixed to VSS_SATA1 AJ25 CICREFN1_SATA Fixed to VSS_SATA1 AE23...
  • Page 84 RZ/G1M 4. Pin Multiplexing Default Mode Default Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use AG31 USB0_DP Open AH31 USB0_DM Open AG29 USB0_RREF Must be used AE27 VD331 Must be used AD26 VD181 Must be used...
  • Page 85 RZ/G1M 4. Pin Multiplexing Default Mode Default Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use Area 0* Open Area 0* Open Area 0* Open Area 0* Open Area 0* Open Area 0* Open Area 0*...
  • Page 86 RZ/G1M 4. Pin Multiplexing Default Mode Default Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use EX_CS5# Pulled-up to VCCQ or pulled-down to VSS MD10 Area 0* Pulled-up to VCCQ or pulled-down to VSS MD12 Area 0*...
  • Page 87 RZ/G1M 4. Pin Multiplexing Default Mode Default Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use AE30 IRQ0 Open AE29 IRQ1 Open AD29 IRQ2 Open AD28 IRQ3 Open AC29 IRQ4 Open AC28 IRQ5 Open AC27 IRQ6...
  • Page 88 RZ/G1M 4. Pin Multiplexing Default Mode Default Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use DU1_CDE Pulled-up to VCCQ or pulled-down to VSS VI0_CLK Open VI0_CLKENB Open VI0_FIELD Open VI0_HSYNC# Open VI0_VSYNC# Open VI0_DATA0/VI0_B0 Open...
  • Page 89 RZ/G1M 4. Pin Multiplexing Default Mode Default Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use ETH_MDIO Open ETH_CRS_DV Open ETH_RX_ER Open ETH_RXD0 Open ETH_RXD1 Open ETH_LINK Open ETH_REFCLK Open ETH_TXD1 Open ETH_TX_EN Open ETH_MAGIC Open...
  • Page 90 RZ/G1M 4. Pin Multiplexing Default Mode Default Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use AJ13 SD3_WP Pulled-up to VCCQ_SD3 or pulled-down to VSS AD13 VCCQ_SD3 Must be used MSIOF0_SCK Open MSIOF0_SYNC Open MSIOF0_TXD Open...
  • Page 91 RZ/G1M 4. Pin Multiplexing Default Mode Default Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use VSS_MLBPPLL1 Must be used VCCQ18_MLBP Must be used VCCQ18_MLBP Must be used VCCQ33_MLBP Must be used VCCQ33_MLBP Must be used...

  • Page 92: Pin Function Controller (Pfc)

    • Module selection Enable and disable the functions of RZ/G1M LSI pins to which pin functions from multiple pin groups are assigned by setting the registers in the PFC module. (Selection is handled by the module select register (MOD_SEL), module select register 2 (MOD_SEL2), module select register 3 (MOD_SEL3) and module register4 (MOD_SEL4).

  • Page 93: Register Configuration

    RZ/G1M 5. Pin Function Controller (PFC) Register Configuration All the registers in the PFC are mapped into the APB bus space. Table 5.1 shows the configuration of the registers provided in the PFC. For details on the registers of the PFC, see section 5.3, Register Description.
  • Page 94 RZ/G1M 5. Pin Function Controller (PFC) Access Name Abbr. Initial Value Address Size Condition Peripheral function select IPSR8 H'0000 0000 H'E606 0040 — register 8 Peripheral function select IPSR9 H'0000 0000 H'E606 0044 — register 9 Peripheral function select IPSR10...
  • Page 95 RZ/G1M 5. Pin Function Controller (PFC) Access Name Abbr. Initial Value Address Size Condition DDR3 general port output DDR3GPOD H'0000_0000 H'E606 0248 — data register DDR3 general port input DDR3GPID H'XXXX_XXX0 H'E606 024C — data register R01UH0626EJ0100 Rev.1.00 Sep 30,2016...

  • Page 96: Register Description

    RZ/G1M 5. Pin Function Controller (PFC) Register Description [Legend] Initial value: Register value after a reset Undefined value R/W: Readable/writable. The written value can be read. Read-only. The write value should always be 0. R/WC0: Readable/writable. Writing 0 initializes the bit. Writing 1 is ignored.

  • Page 97: Lsi Multiplexed Pin Setting Mask Register (Pmmr)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.1 LSI Multiplexed Pin Setting Mask Register (PMMR) Function: PMMR enables/disables writing to the multiplexed pin setting registers. Bit: PMPM Initial value: R/W: Bit: PMPM Initial value: R/W: Bit Name Initial Value Description 31 to 0...

  • Page 98: Gpio/Peripheral Function Select Register 0 (Gpsr0)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.2 GPIO/Peripheral Function Select Register 0 (GPSR0) Function: GPSR0 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...
  • Page 99 RZ/G1M 5. Pin Function Controller (PFC) Bit Name GPIO (Set Value = 0) Peripheral Function (Set Value = 1) GP0[21] GP-0-21 Peripheral function selected by IP0[28:27] GP0[22] GP-0-22 Peripheral function selected by IP0[30:29] GP0[23] GP-0-23 Peripheral function selected by IP1[1:0]...

  • Page 100: Gpio/Peripheral Function Select Register 1 (Gpsr1)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.3 GPIO/Peripheral Function Select Register 1 (GPSR1) Function: GPSR1 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...
  • Page 101 RZ/G1M 5. Pin Function Controller (PFC) Bit Name GPIO (Set Value = 0) Peripheral Function (Set Value = 1) GP1[21] GP-1-21 Peripheral function selected by IP3[13:12] GP1[22] GP-1-22 Peripheral function selected by IP3[15:14] GP1[23] GP-1-23 Peripheral function selected by IP3[17:16]...

  • Page 102: Gpio/Peripheral Function Select Register 2 (Gpsr2)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.4 GPIO/Peripheral Function Select Register 2 (GPSR2) Function: GPSR2 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...
  • Page 103 RZ/G1M 5. Pin Function Controller (PFC) Bit Name GPIO (Set Value = 0) Peripheral Function (Set Value = 1) GP2[25] GP-2-25 Peripheral function selected by IP5[25:24] GP2[26] GP-2-26 Peripheral function selected by IP5[28:26] GP2[27] GP-2-27 Peripheral function selected by IP5[31:29]...

  • Page 104: Gpio/Peripheral Function Select Register 3 (Gpsr3)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.5 GPIO/Peripheral Function Select Register 3 (GPSR3) Function: GPSR3 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...
  • Page 105 RZ/G1M 5. Pin Function Controller (PFC) Bit Name GPIO (Set Value = 0) Peripheral Function (Set Value = 1) GP3[25] GP-3-25 Peripheral function selected by IP9[7] GP3[26] GP-3-26 Peripheral function selected by IP9[10:8] GP3[27] GP-3-27 Peripheral function selected by IP9[11]...

  • Page 106: Gpio/Peripheral Function Select Register 4 (Gpsr4)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.6 GPIO/Peripheral Function Select Register 4 (GPSR4) Function: GPSR4 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...
  • Page 107 RZ/G1M 5. Pin Function Controller (PFC) Bit Name GPIO (Set Value = 0) Peripheral Function (Set Value = 1) GP4[25] GP-4-25 Peripheral function selected by IP10[31:29] GP4[26] GP-4-26 Peripheral function selected by IP11[2:0] GP4[27] GP-4-27 Peripheral function selected by IP11[5:3]...

  • Page 108: Gpio/Peripheral Function Select Register 5 (Gpsr5)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.7 GPIO/Peripheral Function Select Register 5 (GPSR5) Function: GPSR5 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...
  • Page 109 RZ/G1M 5. Pin Function Controller (PFC) Bit Name GPIO (Set Value = 0) Peripheral Function (Set Value = 1) GP5[25] GP-5-25 Peripheral function selected by IP12[26:24] GP5[26] GP-5-26 Peripheral function selected by IP12[29:27] GP5[27] GP-5-27 Peripheral function selected by IP13[2:0]...

  • Page 110: Gpio/Peripheral Function Select Register 6 (Gpsr6)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.8 GPIO/Peripheral Function Select Register 6 (GPSR6) Function: GPSR6 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...
  • Page 111 RZ/G1M 5. Pin Function Controller (PFC) Bit Name GPIO (Set Value = 0) Peripheral Function (Set Value = 1) GP6[25] GP-6-25 Peripheral function selected by IP14[19:17] GP6[26] GP-6-26 Peripheral function selected by IP14[22:20] GP6[27] GP-6-27 Peripheral function selected by IP14[25:23]...

  • Page 112: Gpio/Peripheral Function Select Register 7 (Gpsr7)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.9 GPIO/Peripheral Function Select Register 7 (GPSR7) Function: GPSR7 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...
  • Page 113 RZ/G1M 5. Pin Function Controller (PFC) Bit Name GPIO (Set Value = 0) Peripheral Function (Set Value = 1) GP7[25] GP-7-25 USB1_PWEN GP7[26] GP-7-26 — GP7[27] GP-7-27 — GP7[28] GP-7-28 — GP7[29] GP-7-29 — GP7[30] GP-7-30 — GP7[31] GP-7-31 —...

  • Page 114: Peripheral Function Select Register 0 (Ipsr0)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.10 Peripheral Function Select Register 0 (IPSR0) Function: IPSR0 selects the functions of the multiplexed LSI pins. Bit: — [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 115: Peripheral Function Select Register 1 (Ipsr1)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.11 Peripheral Function Select Register 1 (IPSR1) Function: IPSR1 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 116: Peripheral Function Select Register 2 (Ipsr2)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.12 Peripheral Function Select Register 2 (IPSR2) Function: IPSR2 selects the functions of the multiplexed LSI pins. Bit: — — [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 117: Peripheral Function Select Register 3 (Ipsr3)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.13 Peripheral Function Select Register 3 (IPSR3) Function: IPSR3 selects the functions of the multiplexed LSI pins. Bit: — [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 118: Peripheral Function Select Register 4 (Ipsr4)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.14 Peripheral Function Select Register 4 (IPSR4) Function: IPSR4 selects the functions of the multiplexed LSI pins. Bit: — [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 119: Peripheral Function Select Register 5 (Ipsr5)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.15 Peripheral Function Select Register 5 (IPSR5) Function: IPSR5 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 120: Peripheral Function Select Register 6 (Ipsr6)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.16 Peripheral Function Select Register 6 (IPSR6) Function: IPSR6 selects the functions of the multiplexed LSI pins. Bit: — — [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 121: Peripheral Function Select Register 7 (Ipsr7)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.17 Peripheral Function Select Register 7 (IPSR7) Function: IPSR7 selects the functions of the multiplexed LSI pins. Bit: — — [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 122: Peripheral Function Select Register 8 (Ipsr8)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.18 Peripheral Function Select Register 8 (IPSR8) Function: IPSR8 selects the functions of the multiplexed LSI pins. Bit: — [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 123: Peripheral Function Select Register 9 (Ipsr9)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.19 Peripheral Function Select Register 9 (IPSR9) Function: IPSR9 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 124: Peripheral Function Select Register 10 (Ipsr10)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.20 Peripheral Function Select Register 10 (IPSR10) Function: IPSR10 selects the functions of the multiplexed LSI pins. Bit: IP10 IP10 IP10 IP10 IP10 IP10 IP10 IP10 IP10 IP10 IP10 IP10 IP10 IP10 IP10 IP10...

  • Page 125: Peripheral Function Select Register 11 (Ipsr11)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.21 Peripheral Function Select Register 11 (IPSR11) Function: IPSR11 selects the functions of the multiplexed LSI pins. Bit: IP11 IP11 IP11 IP11 IP11 IP11 IP11 IP11 IP11 IP11 IP11 IP11 IP11 IP11 IP11 IP11...

  • Page 126: Peripheral Function Select Register 12 (Ipsr12)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.22 Peripheral Function Select Register 12 (IPSR12) Function: IPSR12 selects the functions of the multiplexed LSI pins. Bit: IP12 IP12 IP12 IP12 IP12 IP12 IP12 IP12 IP12 IP12 IP12 IP12 IP12 IP12 — —...

  • Page 127: Peripheral Function Select Register 13 (Ipsr13)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.23 Peripheral Function Select Register 13 (IPSR13) Function: IPSR13 selects the functions of the multiplexed LSI pins. Bit: IP13 IP13 IP13 IP13 IP13 IP13 IP13 IP13 IP13 IP13 IP13 IP13 IP13 IP13 IP13 —...

  • Page 128: Peripheral Function Select Register 14 (Ipsr14)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.24 Peripheral Function Select Register 14 (IPSR14) Function: IPSR14 selects the functions of the multiplexed LSI pins. Bit: IP14 IP14 IP14 IP14 IP14 IP14 IP14 IP14 IP14 IP14 IP14 IP14 IP14 IP14 IP14 IP14...

  • Page 129: Peripheral Function Select Register 15 (Ipsr15)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.25 Peripheral Function Select Register 15 (IPSR15) Function: IPSR15 selects the functions of the multiplexed LSI pins. Bit: IP15 IP15 IP15 IP15 IP15 IP15 IP15 IP15 IP15 IP15 IP15 IP15 IP15 IP15 — —...

  • Page 130: Peripheral Function Select Register 16 (Ipsr16)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.26 Peripheral Function Select Register 16 (IPSR16) Function: IPSR16 selects the functions of the multiplexed LSI pins. Bit: — — — — — — — — — — — — — — — —...
  • Page 131 RZ/G1M 5. Pin Function Controller (PFC) Table 5.2 shows the correspondence between the function signals and the bit settings in the GPIO/peripheral function select registers and peripheral function selecting registers. Table 5.2 Correspondence between Function Signals and Register Bit Settings...
  • Page 132 RZ/G1M 5. Pin Function Controller (PFC) Peripheral-Module-(GP-Set-Value-=-1) GPIO/ Function-Selected-by-IP-Bits GPIO Peripheral Peripheral- (GP-Set- Function-1 Function-2 Function-3 Function-4 Function-5 Function-6 Function-7 Function-8 -Function- Function- Value-=- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- Selecting- Selecting- Value-=-0) Value-=-1) Value-=-2) Value-=-3) Value-=-4) Value-=-5)
  • Page 133 RZ/G1M 5. Pin Function Controller (PFC) Peripheral-Module-(GP-Set-Value-=-1) GPIO/ Function-Selected-by-IP-Bits GPIO Peripheral Peripheral- (GP-Set- Function-1 Function-2 Function-3 Function-4 Function-5 Function-6 Function-7 Function-8 -Function- Function- Value-=- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- Selecting- Selecting- Value-=-0) Value-=-1) Value-=-2) Value-=-3) Value-=-4) Value-=-5)
  • Page 134 RZ/G1M 5. Pin Function Controller (PFC) Peripheral-Module-(GP-Set-Value-=-1) GPIO/ Function-Selected-by-IP-Bits GPIO Peripheral Peripheral- (GP-Set- Function-1 Function-2 Function-3 Function-4 Function-5 Function-6 Function-7 Function-8 -Function- Function- Value-=- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- Selecting- Selecting- Value-=-0) Value-=-1) Value-=-2) Value-=-3) Value-=-4) Value-=-5)
  • Page 135 RZ/G1M 5. Pin Function Controller (PFC) Peripheral-Module-(GP-Set-Value-=-1) GPIO/ Function-Selected-by-IP-Bits GPIO Peripheral Peripheral- (GP-Set- Function-1 Function-2 Function-3 Function-4 Function-5 Function-6 Function-7 Function-8 -Function- Function- Value-=- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- Selecting- Selecting- Value-=-0) Value-=-1) Value-=-2) Value-=-3) Value-=-4) Value-=-5)
  • Page 136 RZ/G1M 5. Pin Function Controller (PFC) Peripheral-Module-(GP-Set-Value-=-1) GPIO/ Function-Selected-by-IP-Bits GPIO Peripheral Peripheral- (GP-Set- Function-1 Function-2 Function-3 Function-4 Function-5 Function-6 Function-7 Function-8 -Function- Function- Value-=- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- Selecting- Selecting- Value-=-0) Value-=-1) Value-=-2) Value-=-3) Value-=-4) Value-=-5)
  • Page 137 RZ/G1M 5. Pin Function Controller (PFC) Peripheral-Module-(GP-Set-Value-=-1) GPIO/ Function-Selected-by-IP-Bits GPIO Peripheral Peripheral- (GP-Set- Function-1 Function-2 Function-3 Function-4 Function-5 Function-6 Function-7 Function-8 -Function- Function- Value-=- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- Selecting- Selecting- Value-=-0) Value-=-1) Value-=-2) Value-=-3) Value-=-4) Value-=-5)

  • Page 138: Module Select Register (Mod_Sel)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.27 Module Select Register (MOD_SEL) Function: MOD_SEL selects the group for multiple LSI pins with multiplexed pin functions. Each input or input/output signal of the SCIF, HSCIF, SSI, QSPI, VI , TMU, LBSC, TSIF and MSIOF are assigned to two or more groups of pins.
  • Page 139 RZ/G1M 5. Pin Function Controller (PFC) Function 5 Function 1 Function 1 * Function 2 Function 3 Function 4 (Set Value = Bit Name (Set Value = H'0) (Set Value = H'0) (Set Value = H'1) (Set Value = H'2)
  • Page 140 RZ/G1M 5. Pin Function Controller (PFC) Function 5 Function 1 Function 1 * Function 2 Function 3 Function 4 (Set Value = Bit Name (Set Value = H'0) (Set Value = H'0) (Set Value = H'1) (Set Value = H'2)

  • Page 141: Module Select Register 2 (Mod_Sel2)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.28 Module Select Register 2 (MOD_SEL2) Function: MOD_SEL2 selects the group for multiple LSI pins with multiplexed pin functions. Each input or input/output signal of the SCIF, RCAN, ADG and SSI is assigned to two or more groups of pins. Select one of these groups when using these signals.
  • Page 142 RZ/G1M 5. Pin Function Controller (PFC) Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Bit Name (Set Value = H'0) (Set Value = H'1) (Set Value = H'2) (Set Value = H'3) (Set Value = H'4)

  • Page 143: Module Select Register 3 (Mod_Sel3)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.29 Module Select Register 3 (MOD_SEL3) Function: MOD_SEL3 selects the group for multiple LSI pins with multiplexed pin functions. Each input or input/output signal of the SCIF, RCAN, I2C, IIC and MMC is assigned to two or more groups of pins.
  • Page 144 RZ/G1M 5. Pin Function Controller (PFC) Function 1 Function 2 Function 3 Function 4 Function 5 Bit Name (Set Value = H'0) (Set Value = H'1) (Set Value = H'2) (Set Value = H'3) (Set Value = H'4) sel_scif5 RX5 of the VI0_VSYNC# pin RX5_B of the SD3_WP pin —...

  • Page 145: Module Select Register 4 (Mod_Sel4)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.30 Module Select Register 4 (MOD_SEL4) Function: MOD_SEL4 selects the group for multiple LSI pins with multiplexed pin functions. Each input or input/output signal of the MSIOF, HSCIF, DU, and SSI is assigned to two or more groups of pins. Select one of these groups when using these signals.
  • Page 146 RZ/G1M 5. Pin Function Controller (PFC) Function 1 Function 2 Function 3 Function 4 Function 5 Bit Name (Set Value = H'0) (Set Value = H'1) (Set Value = H'2) (Set Value = H'3) (Set Value = H'4) sel_ssi0 SSI_SCK0129 of the SSI_SCK0129 SSI_SCK0129_B of the DU1_DR2 pin —...

  • Page 147: Lsi Pin Pull-Up Control Register 0 (Pupr0)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.31 LSI Pin Pull-Up Control Register 0 (PUPR0) Function: PUPR0 performs on/off control of the pull-up resistors. Bit: PUPR0 PUPR0 PUPR0 PUPR0 PUPR0 PUPR0 PUPR0 PUPR0 PUPR0 PUPR0 PUPR0 PUPR0 PUPR0 PUPR0 PUPR0 PUPR0...
  • Page 148 RZ/G1M 5. Pin Function Controller (PFC) Bit Name Set Value = 1 PUPR0[6] D0 pin is pulled up PUPR0[5] DU0_DOTCLKIN pin is pulled up PUPR0[4] A24 pin is pulled up PUPR0[3] A23 pin is pulled up PUPR0[2] A22 pin is pulled up...

  • Page 149: Lsi Pin Pull-Up Control Register 1 (Pupr1)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.32 LSI Pin Pull-Up Control Register 1 (PUPR1) Function: PUPR1 performs on/off control of the pull-up resistors. Bit: PUPR1 PUPR1 PUPR1 PUPR1 PUPR1 PUPR1 PUPR1 PUPR1 PUPR1 PUPR1 PUPR1 PUPR1 PUPR1 PUPR1 PUPR1 PUPR1...
  • Page 150 RZ/G1M 5. Pin Function Controller (PFC) Bit Name Set Value = 1 PUPR1[6] A16 pin is pulled up PUPR1[5] A15 pin is pulled up PUPR1[4] A14 pin is pulled up PUPR1[3] A13 pin is pulled up PUPR1[2] A12 pin is pulled up...

  • Page 151: Lsi Pin Pull-Up Control Register 2 (Pupr2)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.33 LSI Pin Pull-Up Control Register 2 (PUPR2) Function: PUPR2 performs on/off control of the pull-up resistors. Bit: PUPR2 PUPR2 PUPR2 PUPR2 PUPR2 PUPR2 PUPR2 PUPR2 PUPR2 PUPR2 PUPR2 PUPR2 PUPR2 PUPR2 PUPR2 PUPR2...
  • Page 152 RZ/G1M 5. Pin Function Controller (PFC) Bit Name Set Value = 1 PUPR2[6] SSI_SDATA2 pin is pulled up PUPR2[5] SSI_WS2 pin is pulled up PUPR2[4] SSI_SCK2 pin is pulled up PUPR2[3] SSI_SDATA1 pin is pulled up PUPR2[2] SSI_WS1 pin is pulled up...

  • Page 153: Lsi Pin Pull-Up Control Register 3 (Pupr3)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.34 LSI Pin Pull-Up Control Register 3 (PUPR3) Function: PUPR3 performs on/off control of the pull-up resistors. Bit: PUPR3 PUPR3 PUPR3 PUPR3 PUPR3 PUPR3 PUPR3 PUPR3 PUPR3 PUPR3 PUPR3 PUPR3 PUPR3 PUPR3 PUPR3 PUPR3...
  • Page 154 RZ/G1M 5. Pin Function Controller (PFC) Bit Name Set Value = 1 PUPR3[6] IRQ8 pin is pulled up PUPR3[5] IRQ7 pin is pulled up PUPR3[4] IRQ6 pin is pulled up PUPR3[3] IRQ5 pin is pulled up PUPR3[2] IRQ4 pin is pulled up...

  • Page 155: Lsi Pin Pull-Up Control Register 4 (Pupr4)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.35 LSI Pin Pull-Up Control Register 4 (PUPR4) Function: PUPR4 performs on/off control of the pull-up resistors. Bit: PUPR4 PUPR4 PUPR4 PUPR4 PUPR4 PUPR4 PUPR4 PUPR4 PUPR4 PUPR4 PUPR4 PUPR4 PUPR4 PUPR4 PUPR4 PUPR4...
  • Page 156 RZ/G1M 5. Pin Function Controller (PFC) Bit Name Set Value = 1 PUPR4[6] DU1_DISP pin is pulled up PUPR4[5] DU1_EXODDF_DU1_ODDF_DISP_CDE pin is pulled up PUPR4[4] DU1_EXVSYNC_DU1_VSYNC pin is pulled up PUPR4[3] DU1_EXHSYNC_DU1_HSYNC pin is pulled up PUPR4[2] DU1_DOTCLKOUT1 pin is pulled up...

  • Page 157: Lsi Pin Pull-Up Control Register 5 (Pupr5)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.36 LSI Pin Pull-Up Control Register 5 (PUPR5) Function: PUPR5 performs on/off control of the pull-up resistors. Bit: PUPR5 PUPR5 PUPR5 PUPR5 PUPR5 PUPR5 PUPR5 PUPR5 PUPR5 PUPR5 PUPR5 PUPR5 PUPR5 PUPR5 PUPR5 PUPR5...
  • Page 158 RZ/G1M 5. Pin Function Controller (PFC) Bit Name Set Value = 1 PUPR5[6] VI1_VSYNC# pin is pulled up PUPR5[5] VI1_HSYNC# pin is pulled up PUPR5[4] VI0_R7 pin is pulled up PUPR5[3] VI0_R6 pin is pulled up PUPR5[2] VI0_R5 pin is pulled up...

  • Page 159: Lsi Pin Pull-Up Control Register 6 (Pupr6)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.37 LSI Pin Pull-Up Control Register 6 (PUPR6) Function: PUPR6 performs on/off control of the pull-up resistors. Bit: PUPR6 PUPR6 PUPR6 PUPR6 PUPR6 PUPR6 PUPR6 PUPR6 PUPR6 PUPR6 PUPR6 PUPR6 PUPR6 PUPR6 PUPR6 PUPR6...
  • Page 160 RZ/G1M 5. Pin Function Controller (PFC) Bit Name Set Value = 1 PUPR6[6] SD0_DATA0 pin is pulled up PUPR6[5] SD0_CMD pin is pulled up PUPR6[4] SD0_CLK pin is pulled up PUPR6[3] STP_OPWM_0 pin is pulled up PUPR6[2] STP_ISSYNC_0 pin is pulled up...

  • Page 161: Lsi Pin Pull-Up Control Register 7 (Pupr7)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.38 LSI Pin Pull-Up Control Register 7 (PUPR7) Function: PUPR7 performs on/off control of the pull-up/down* resistors. Bit: PUPR7 PUPR7 PUPR7 PUPR7 PUPR7 PUPR7 PUPR7 PUPR7 PUPR7 PUPR7 PUPR7 PUPR7 PUPR7 PUPR7 PUPR7 PUPR7...
  • Page 162 RZ/G1M 5. Pin Function Controller (PFC) Bit Name Set Value = 1 PUPR7[7] GPS_MAG pin is pulled up PUPR7[6] GPS_SIGN pin is pulled up PUPR7[5] GPS_CLK pin is pulled up PUPR7[4] SIM0_D pin is pulled up PUPR7[3] SIM0_CLK pin is pulled up...

  • Page 163: Sd Control Register 0 (Ioctrl0)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.39 SD Control Register 0 (IOCTRL0) Function: IOCTRL0 controls the driving abilities of pins in use for the SD0 interfaces. Bit: drv2_st drv1_st — — — — — — — — — — —...

  • Page 164: Sd Control Register 1 (Ioctrl1)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.40 SD Control Register 1 (IOCTRL1) Function: IOCTRL1 controls the driving abilities of pins in use for the SD2 and SD3 interfaces. Bit: drv2_sd drv1_sd drv2_sd drv1_sd drv2_sd drv1_sd drv2_sd drv1_sd drv2_sd drv1_sd drv2_sd...
  • Page 165 RZ/G1M 5. Pin Function Controller (PFC) Initial Bit Name Value Description drv2_sd3d0 SD3_DATA0 Setting. The value of these bits must be 11. drv1_sd3d0 Note: To enable this register to be set, appropriately set the multiplexed pin setting mask register (PMMR) immediately before setting this register.

  • Page 166: Tdsel Control Register 4 (Ioctrl4)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.41 TDSEL Control Register 4 (IOCTRL4) Function: IOCTRL4 controls the delay of returned clock of in pins of IRQ, DU and Ethernet interfaces. Bit: — — — — — — — — — —...

  • Page 167: Tdsel Control Register 5 (Ioctrl5)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.42 TDSEL Control Register 5 (IOCTRL5) Function: IOCTRL5 controls the delay of returned clock in pins of SDHI, LBSC, SSI and ADG interfaces. Bit: audio_t audio_t ssisck5 ssisck5 excs1_t excs1_t sd0tdse sd0tdse sd2tdse sd2tdse...

  • Page 168: Sd Control Register 6 (Ioctrl6)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.43 SD Control Register 6 (IOCTRL6) Function: IOCTRL6 controls the IO voltage of pins in use for the SD interfaces. Bit: poc_sd poc_sd poc_sd poc_sd poc_sd poc_sd poc_sd poc_sd poc_sd poc_sd poc_sd poc_sd poc_sd...
  • Page 169 RZ/G1M 5. Pin Function Controller (PFC) Initial Bit Name Value Description poc_sd2dat1 Selecting IO voltage for the pin SD2_DATA1 0: 1.8 V 1: 3.3 V poc_sd2dat2 Selecting IO voltage for the pin SD2_DATA2 0: 1.8 V 1: 3.3 V poc_sd2dat3 Selecting IO voltage for the pin SD2_DATA3 0: 1.8 V...

  • Page 170: Iic3 (Dvfs) And Tdbg Io Cell Control Register (Ioctrl7)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.44 IIC3 (DVFS) and TDBG IO Cell Control Register (IOCTRL7) Function: IOCTRL controls the driving abilities of pins in use for the IIC and IIC3 (DVFS) interfaces. This register is internal use and reserved; the value of this register should not be changed.

  • Page 171: Ddr3 General Port Io Enable Register (Ddr3Gpen)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.45 DDR3 General Port IO Enable Register (DDR3GPEN) Function: DDR3GPEN is used to write values to enable DDR3 general port function. Bit: DDR3EN[31:16] Initial value: R/W: Bit: DDR3EN[15:0] Initial value: R/W: Initial Bit Name...

  • Page 172: Ddr3 General Port Output Enable Register (Ddr3Gpoe)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.46 DDR3 General Port Output Enable Register (DDR3GPOE) Function: DDR3GPOE is use to enable output of DDR3 general port function. Bit: DDR3OE[31:16] Initial value: R/W: Bit: DDR3OE[15:0] Initial value: R/W: Initial Bit Name Value...
  • Page 173 RZ/G1M 5. Pin Function Controller (PFC) Initial Bit Name Value Description DDR3OE[16] Enabling output of DDR3 general port function bit 16 0: Disabled. 1: Enabled. DDR3OE[15] Enabling output of DDR3 general port function bit 15 0: Disabled. 1: Enabled. DDR3OE[14] —...

  • Page 174: Ddr3 General Port Output Data Register (Ddr3Gpod)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.47 DDR3 General Port Output Data Register (DDR3GPOD) Function: DDR3GPOD is use to write data to DDR3 general port. Bit: DDR3OD[31:16] Initial value: R/W: Bit: DDR3OD[15:0] Initial value: R/W: Initial Bit Name Value Description DDR3OD[31] —...
  • Page 175 RZ/G1M 5. Pin Function Controller (PFC) Initial Bit Name Value Description DDR3OD[1] For writing values to DDR3 general port bit 1 DDR3OD[0] — Note: To enable this register to be set, appropriately set the multiplexed pin setting mask register (PMMR) immediately before setting this register.

  • Page 176: Ddr3 General Port Input Data Register (Ddr3Gpid)

    RZ/G1M 5. Pin Function Controller (PFC) 5.3.48 DDR3 General Port Input Data Register (DDR3GPID) Function: DDR3GPID is use to read input data from DDR3 general port. Bit: DDR3ID[31:16] Initial value: — — — — — — R/W: Bit: DDR3ID[15:0] Initial value: —...
  • Page 177 RZ/G1M 5. Pin Function Controller (PFC) Bit Name Initial Value Description DDR3ID[0] — R01UH0626EJ0100 Rev.1.00 5-86 Sep 30,2016...

  • Page 178: Operation

    RZ/G1M 5. Pin Function Controller (PFC) Operation 5.4.1 Function Setting for Multiplexed Pins Setting the LSI multiplexed pin setting mask register (PMMR) is necessary before setting each of the GPIO/peripheral function select registers 0 to 7 (GPSR0 to GPSR7) and peripheral function select registers 0 to 16 (IPSR0 to IPSR16).
  • Page 179 RZ/G1M 5. Pin Function Controller (PFC) Procedure for changing pin function from peripheral function to GPIO Clock (CP φ ) Set the LSI multiplexed pin setting mask register Peripheral function select value Set the GPIO/peripheral function select register to GPIO...

  • Page 180: Setting Pull-Up/Down Resistors

    RZ/G1M 5. Pin Function Controller (PFC) In case that one of the pin function in the following list is selected, make sure to disable the data reception of corresponding SCIFAn channel before performing the sequence in the Figure 5.3. LSI Pin...

  • Page 181: Main Revisions And Additions In This Edition

    Main Revisions and Additions in this Edition Minor revisions such as corrections of errors in spelling and modifications of wording are not included in the revision history. Description Rev. Page Contents Summary 1.00 — First edition issued R01UH0626EJ0100 Rev.1.00 Sep 30,2016...
  • Page 182 RZ/G1M User’s Manual: Hardware Publication Date: Rev.1.00 Sep 30, 2016 Published by: Renesas Electronics Corporation...
  • Page 183 SALES OFFICES SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. Renesas Electronics America Inc. 2801 Scott Boulevard Santa Clara, CA 95050-2549, U.S.A.
  • Page 184 RZ/G1M R01UH0626EJ0100...

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