NXP Semiconductors MCXN 4 Series Hardware Design Manual
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NXP Semiconductors MCXN 4 Series Hardware Design Manual

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UG10092
MCXNx4x Hardware Design Guide
Rev. 1 — 19 January 2024
Document information
Information
Keywords
Abstract
Content
UG10092, MCXNx4x, MCX N, MCX N Series, MCX N94x, MCX N54x, High-Performance
MCU, eIQ Neutron NPU, EdgeLock Secure Enclave, Dual-Core MCU, 150 MHz MCU, Artificial
Intelligence, Machine Learning, Advanced Security MCU, Secure MCU, Neural Processing Unit,
Low-Power MCU, General Purpose MCU, Arm Cortex-M33 MCU
This document aims to help hardware engineers design and test their MCXNx4x MCU-based
designs.
User guide

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  • Page 1 UG10092 MCXNx4x Hardware Design Guide Rev. 1 — 19 January 2024 User guide Document information Information Content Keywords UG10092, MCXNx4x, MCX N, MCX N Series, MCX N94x, MCX N54x, High-Performance MCU, eIQ Neutron NPU, EdgeLock Secure Enclave, Dual-Core MCU, 150 MHz MCU, Artificial Intelligence, Machine Learning, Advanced Security MCU, Secure MCU, Neural Processing Unit, Low-Power MCU, General Purpose MCU, Arm Cortex-M33 MCU Abstract...

  • Page 2: Introduction

    UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide 1 Introduction This document aims to help hardware engineers design and test their MCXNx4x MCU-based designs. It provides information about board layout recommendations and design checklists to ensure first-pass success and avoid board bring-up problems. For the relevant device-specific hardware documentation, see...

  • Page 3: Power Configurations

    UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide Table 1. Power domain operating requirements ...continued Power domain Voltage range Package pin Remarks VDD_P2 1.71 V – 3.60 V VDD_P2 The extended voltage range of 1.14 V – 1.32 V is allowed, provided this rail ramps after the system 1.14 V –...

  • Page 4: Mixed Supply Configuration

    UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide VDD_ANA Analog domain LDO_CORE USB FS PHY USB HS PHY VOUT_SYS 1.8/2.5 V VBAT domain LDO_SYS VDD_LDO_SYS VBAT Dig. switch Core domain System domain 1.71 - 3.6 V VDD_BAT Anal. VDD_DCDC Retention DCDC_CORE...

  • Page 5: Bulk And Decoupling Capacitance

    UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide VDD_ANA Analog domain LDO_CORE USB FS PHY USB HS PHY VOUT_SYS 1.8/2.5 V Supply A VBAT domain LDO_SYS VDD_LDO_SYS VBAT Dig. switch VDD_BAT Supply B Core domain System domain Anal. VDD_DCDC Retention DCDC_CORE...

  • Page 6: Package Details, Route-Out, And Special Considerations

    UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide In general, NXP recommends that each power pin have one decoupling capacitor of 0.1 µF and each power domain have one bulk capacitor of 1 µF. The decoupling and bulk capacitors must be placed as close to their respective MCU pins as possible.

  • Page 7: Package Outline

    UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide 5.1.1 Package outline This section provides the details about the outline of the 84-pin VFBGA package, see Figure 184VFBGA 9 x 9 x 0.86 mm 0.5 mm Package drawing: SOT2172-1 aaa-054008 Figure 4. 184-pin VFBGA package drawing 5.1.2 VFBGA placement...

  • Page 8: Bulk And Decoupling Capacitor Placement

    UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide P1_8 P1_8 P1_7 P1_7 P1_4 P1_4 P0_25 P0_21 P0_17 P0_9 P0_5 P0_1 P0_0 P1_9 P1_9 P1_6 P1_6 P1_5 P1_5 P1_3 P1_3 P0_24 P0_23 P0_22 P0_16 P0_11 P0_10 P0_4 P0_3 P0_2 P3_0 ENET P1_10...

  • Page 9: Vfbga Routing

    UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide Figure 6. Example decoupling and bulk capacitor layout for VFBGA package 5.1.3 VFBGA routing The MCXNx4x VFBGA is designed to allow for routing all 184-pins externally in a four-layer design using 4 mil trace widths and Via-In-Pad (VIP) technology. The recommended route-out is shown in...

  • Page 10: Pcb Stack-Up For Vfbga

    UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide Figure 7. Recommended VFBGA escape routing 5.1.4 PCB stack-up for VFBGA As per NXP recommendations, MCXNx4x VFBGA is designed to be routed on a minimum of four layers. Less may be possible, but it may require special toolings and/or a nonoptimal design. It may also not be possible to route out all of the connections.
  • Page 11 UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide Signal Signal aaa-054011 Figure 9. Example four-layer stack-up #2 An example six-layer stack-up is shown in Figure 10. This stack-up is used in the MCX-N9XX-EVK. Subclass name Type Material Thickness (MIL) SURFACE CONDUCTOR COPPER_1OZ 1.200000...

  • Page 12: 100-Pin Hlqfp Package

    UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide L2 and L5 are solid ground planes that provide the reference planes: • L1 and L3 are tightly coupled to L2 as the reference plane • L4 and L6 are tightly coupled to L5 as the reference plane 5.2 100-pin HLQFP package...

  • Page 13: Hlqfp Routing

    UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide ENET FlexSPI_A N5XX P1_7 P1_7 P1_6 P1_6 P1_5 P1_5 P1_4 P1_4 P1_3 P1_2 P1_1 P1_0 P0_23 P0_22 P0_21 P0_20 P0_19 P0_18 P0_17 P0_16 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 N5XX N3XX P1_7...

  • Page 14: Dcdc

    UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide 6 DCDC The MCXNx4x includes an on-chip DCDC converter to regulate the VDD_CORE domain voltage. The DCDC regulator is required to achieve optimal power performance of the MCXNx4x devices. An external inductor is needed for the use of the DCDC converter. The inductor must be placed between the DCDC_LX pin and the VDD_CORE pin.

  • Page 15: Digital Interfaces

    UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide The schematics for the two oscillator modules are shown in Figure 15 Figure Clock XTAL32K P5_1/XTAL32K EXTAL32K P5_0/EXTAL32K C144 C145 12 pF 12 pF 32.768 KHz SC32S-12.5PF20PPM aaa-053999 Figure 15. 32 kHz oscillator schematic...

  • Page 16: General High-Speed Design Recommendations

    UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide 8.1 General high-speed design recommendations NXP recommends using high-speed design techniques for most of the digital interfaces. While the interface speeds are only up to 100 MHz, and some interfaces are slow enough that these recommendations do not need to be strictly followed.

  • Page 17: High-Speed Usb

    UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide The MCX-N9XX-EVK also includes ESD diodes for the critical pin connections. It is recommended but optional. The trace signals TRACE_CLKOUT, TRACE_D0, TRACE_D1, TRACE_D2, and TRACE_D3 should be treated as the data/signaling lines and must be routed with the recommendations detailed in Section 8.1.

  • Page 18: Full-Speed Usb

    UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide If using the HS USB in ISP mode, a 24 MHz crystal must be used in at least the first access of the device. It is possible to change the security fuse configuration to allow for a different crystal, but it must be configured by the user, for example, factory configuration requires a 24 MHz crystal for HS USB ISP operation.

  • Page 19: Rmii

    UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide 8.5.1 RMII This section provides information about Reduced Media Independent Interface (RMII), Ethernet schematic, and layout recommendations. 8.5.1.1 Ethernet schematic recommendations When implementing the Ethernet in a design, sourcing the clock for the Ethernet Phy is a major concern due to specific timing requirements of the Ethernet standard.

  • Page 20: Ethernet Layout Recommendations

    UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide is not 0x0. As shown by the blue arrows in Figure 19, pin P1_4 accepts the RMII clock from the Phy when the P1_4 digital input buffer is enabled ENET_PHY_INTF_SEL[PHY_SEL] selects the RMII clock.

  • Page 21: Analog Interfaces

    UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide In addition, given the high-speed capabilities of the FlexSPI interface, high-speed design techniques must be incorporated. The SSx, SCLK, DQS, DATAx signals should be treated as the data/signaling lines and must be routed with the recommendations detailed in Section 8.1.

  • Page 22: Pull-Ups And Pull-Downs Resistors

    UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide In addition, there are restrictions on the amount of current that individual pins can source and limits to the ports collectively. Individual pins cannot source or sink more than +/- 25 mA, and the sum of the currents of all pins on a port cannot exceed 100 mA.

  • Page 23: Tsi

    UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide and the user application cannot run until a valid ISP interface successfully command the device to run the user application. Therefore, it is important that hardware designs appropriately handle this pin. How this pin is handled is application-dependent, but hardware designs must ensure that the use of this pin is understood and that it is not inadvertently pulled down as this enters ISP mode.

  • Page 24: Pcb Trace Routing

    UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide The recommended mutual key shape is shown in Figure 23. The electrode of the TX wraps the electrode of the RX, which can prevent the RX channel from being affected by noise. The number of fingers has a great impact on touch sensitivity.

  • Page 25: Ground Plane

    UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide Figure 24. Bottleneck routing maintaining adequate clearance for a touch sensing trace 10.2.5 Ground plane A proper ground plane prevents the coupling of external electromagnetic interference to the touch-sensing electrodes. It also acts as a shield for undesired electric fields. X-hatch pattern ground is recommended instead of solid-filled ground to use around and under touch electrodes.

  • Page 26: Acronyms And Abbreviations

    UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide Table 3. Unused pin recommendations ...continued Module Pin/pad types Recommendation Supply VDD_LDO_CORE, Tie to the regulator’s respective output, VDD_CORE and VDD_SYS respectively VDD_LDO_SYS DCDC VDD_DCDC, DCDC_LX Tie to the ground through a 10 k ohm resistor...

  • Page 27: Revision History

    UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide Table 5. Acronyms and abbreviations ...continued Acronym Definition Inter-Integrated Circuit Input/Output IEEE Institute of Electrical and Electronics Engineers In-System Programming JTAG Joint Test Access Group Local Area Network Low Drop-out Media Access Controller Microcontroller Unit...

  • Page 28: Legal Information

    NXP Semiconductors. In the event that customer uses the product for design-in and use in In no event shall NXP Semiconductors be liable for any indirect, incidental, automotive applications to automotive specifications and standards, punitive, special or consequential damages (including - without limitation - customer (a) shall use the product without NXP Semiconductors’...
  • Page 29 UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Intel, the Intel logo, Intel Core, OpenVINO, and the OpenVINO logo — Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, are trademarks of Intel Corporation or its subsidiaries.

  • Page 30: Table Of Contents

    UG10092 NXP Semiconductors MCXNx4x Hardware Design Guide Contents Introduction ............2 Acronyms and abbreviations ....... 26 Architecture overview ........2 Revision history ..........27 Power configurations ........3 Legal information ...........28 Single supply configuration ........3 Mixed supply configuration ........ 4 Bulk and decoupling capacitance ....5 Package details, route-out, and special considerations ..........

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