Cypress CY62167DV18 Specification Sheet

Features
• Very high speed: 55 ns
• Wide voltage range: 1.65V–1.95V
• Ultra low active power
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 15 mA @ f = f
• Ultra low standby power
• Easy memory expansion with CE
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in Pb-free 48-ball VFBGA package
Functional Description
The CY62167DV18 is a high performance CMOS static RAM
organized as 1M words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. Placing the device into standby mode reduces power
Logic Block Diagram
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Power Down
Circuit
Note
1. For best practice recommendations, refer to the Cypress application note "System Design Guidelines" at http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05326 Rev. *C
max
, CE , and OE features
1 2
[1]
®
) in
DATA IN DRIVERS
1M × 16
RAM Array
COLUMN DECODER
BHE
BLE
• 198 Champion Court
CY62167DV18 MoBL
16-Mbit (1M x 16) Static RAM
consumption by more than 99% when deselected (CE
or CE LOW or both BHE and BLE are HIGH). The input and
2
output pins (IO through IO
0 15
state when:
• Deselected (CE HIGH or CE
1
• Outputs are disabled (OE HIGH)
• Both Byte High Enable (BHE) and Byte Low Enable (BLE)
are disabled (BHE, BLE HIGH)
• Write operation is active (CE
LOW)
To write to the device, take Chip Enables (CE
HIGH) and Write Enable (WE) input LOW. If BLE is LOW, then
data from IO pins (IO through IO
0
specified on the address pins (A
then data from IO pins (IO
8
location specified on the address pins (A
To read from the device, take Chip Enables (CE
CE HIGH) and OE LOW while forcing the WE HIGH. If BLE
2
is LOW, then data from the memory location specified by the
address pins appear on IO
0
from memory appears on IO
page 9 for a complete description of read and write modes.
IO –IO
0
IO –IO
8
BYTE
BHE
WE
OE
BLE
CE
2
CE
1
,
• San Jose CA 95134-1709
HIGH
1
) are placed in a high impedance
LOW)
2
LOW, CE HIGH and WE
1 2
LOW and CE
1
) is written into the location
7
through A ). If BHE is LOW
0 19
through IO ) is written into the
15
through A ).
0 19
LOW and
1
to IO . If BHE is LOW, then data
7
to IO . See the "Truth Table" on
8 15
7
15
CE
2
CE
1
• 408-943-2600
Revised April 25, 2007
®
2
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