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Infineon XDP XDPP1100A Reference Manual

Infineon XDP XDPP1100A Reference Manual

Digital power controller

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XDP™ XDPP1100, XDPP1100A reference manual

Digital power controller

About this document

Scope and purpose

This document focuses on the XDPP1100 hardware (HW) implementation, and it can be used as a reference

document for firmware (FW) developers. The aim is to describe high-level functions and provide block diagram

illustrations of the implemented HW. Furthermore, the purpose is to demonstrate how the XDPP1100 interacts

with external components within applications, and show how the sensed information from the analog input

pins is processed by the HW.

This document describes both the XDPP1100 and XDPP1100A versions of the HW. References to XDPP1100

apply to both the XDPP1100 and XDPP1100A versions of the product, while references to XDPP1100A

specifically refer to the XDPP1100A version of the product. The main difference between these two versions is

that the XDPP1100A includes VDD undervoltage lockout (UVLO) as an optional shutdown fault mechanism.

Intended audience

Power supply design and FW engineers, isolated digital brick module designers, telecom and server power

system designers.

User manual

Please read the Important Notice and Warnings at the end of this document

V 1.2

www.infineon.com/xdpp1100

page 1

2024-02-22

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Summary of Contents for Infineon XDP XDPP1100A

Page 1: About This Document
Intended audience Power supply design and FW engineers, isolated digital brick module designers, telecom and server power system designers. User manual Please read the Important Notice and Warnings at the end of this document V 1.2 www.infineon.com/xdpp1100 page 1 2024-02-22...
Page 2: Table Of Contents
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Table of contents Table of contents About this document ........................1 Table of contents ..........................2 Introduction .......................... 8 Applications ............................. 8 Control registers and PMBus commands ....................8 Naming conventions ..........................9 1.3.1 Loops and phases ..........................
Page 3 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Table of contents TS input mux and sequencing ......................67 Telemetry sense current DAC ........................ 70 Telemetry sense processor ........................70 4.4.1 Sequencer ............................71 4.4.2 Gain and offset correction ....................... 71 4.4.3 computation ..........................
Page 4 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Table of contents 7.3.4 Forced duty cycle T1, T2 ........................ 142 Burst mode ............................143 Fast-transient response ........................144 7.5.1 Fast-transient response – load step ....................144 7.5.2 Fast-transient response – load release ..................146 PWM interrupts ............................
Page 5 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Table of contents Fault PMBus commands ........................272 Current sharing (I ) ......................286 SHARE 10.1 Current sharing circuit ........................286 10.2 Current sharing PI filter ........................288 10.3 Current sharing FW override ....................... 289 10.4 Current sharing pin, DAC and ADC configuration ................
Page 6 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Table of contents 15.3.3 Reset generator unit ........................380 15.3.3.1 Reset sources ..........................381 15.3.3.2 Software power-down ......................382 15.3.3.3 Software reset ........................... 383 15.3.3.4 RGU registers ..........................383 15.4 Memory ..............................391 15.4.1 Read-only memory .........................
Page 7 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Table of contents 15.13 UART ..............................544 15.13.1 UART block diagram ........................544 15.13.2 UART registers ..........................545 15.14 Debugger port ............................. 560 15.14.1 Serial wire debugger interface ....................... 560 Revision history........................... 564 Disclaimer...........................
Page 8: Introduction
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Introduction Introduction This document focuses on XDPP1100 HW implementation, and it can be used as a reference document by FW developers. The aim is to describe high-level functions and provide block diagram illustrations of the implemented HW.
Page 9: Naming Conventions
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Introduction stored in the NVM. The XDPP1100 controllers support multiple reprogramming cycles, and this is easily accomplished with the XDPP1100 GUI. In addition to supporting multiple reprogramming cycles, the XDPP1100 controllers also support storing multiple configurations in NVM, where the initialization setting is selected from one of these stored configurations depending on the value of an external resistor connect to the XADDR pin.
Page 10 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Introduction GPIO General-purpose input output Graphical user interface Half-bridge HBCT Half-bridge center tap High impedance High-pass filter Hardware IADC Current sense analog-to-digital converter IBAL Current balance Input output Integrated power stage IS AFE Current sense analog front end ISHARE Current sharing...
Page 11 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Introduction VSADC Voltage sense analog-to-digital converter Voltage sense processor X-valent Latin characters Magnetic flux density BVREF_BVRREF XDPP1100 input pin BVSEN_BVRSEN XDPP1100 input pin Output voltage, Loop 1 BIREF XDPP1100 input pin for current sensing BISEN XDPP1100 input pin for current sensing Capacitor...
Page 12: Binary Number Format Convention
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Introduction Off-time On-time Switching period Voltage across the body diode body Internal reference voltage control Error voltage errn Voltage at the IMON pin IMON Inductor voltage Input voltage Output voltage, Loop 0 Primary-side voltage PRIMARY Rectified voltage...
Page 13: Structure Of This Document
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Introduction Structure of this document The remaining document is divided into 14 chapters, which describe the implemented HW of XDPP1100. Each chapter presents an independent part of the HW functionality. At the end of each chapter, relevant registers and PMBus commands related to the described functionality are summarized.
Page 14: Voltage Sense
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage sense Voltage sense This chapter describes the VS module and its submodules, voltage sense ADC (VSADC) and voltage sense processor (VSP) in detail. In addition, the user-programmable settings for configuring the features of the sensed voltages are described and relevant registers provided.
Page 15: Vs Module Configuration
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage sense VS module configuration The XDPP1100 controller contains three VS modules, VS0, VS1 and VS2. Each of them is connected to the above- mentioned analog input pin pairs as follows: Input pin pair VSEN/VREF is connected to VS0 •...
Page 16 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage sense Loop 0 V telemetry, faults VSEN VSP0 PID0 VREF Loop 0 V VRSEN VSP1 telemetry, RECT VRREF faults Phase 1 (ISEN) current sense, flux balance Phase 2 BVRSEN (BISEN) VSP2 RECT BVRREF current sense,...
Page 17 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage sense Loop 0 V telemetry, faults VSEN VSP0 PID0 VREF Loop 0/1 V VRSEN or V VSP1 telemetry, RECT VRREF faults Phase 1/2 current sense BVSEN VSP2 PID1 BVREF Loop 1 V telemetry, faults Figure 4...
Page 18: Voltage Sense Analog-To-Digital Converter
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage sense VSADC VSEN Tracking vout VREF vsadc Figure 5 VS module block diagram while processing V VSADC vrs_track vrs_hold vout V(R)SEN vsadc Tracking V(R)REF vrect vrs_comp vrs_comp_ref Figure 6 VS module block diagram while processing V RECT Voltage sense analog-to-digital converter This section discusses the VSADC and its relevant submodules in more detail.
Page 19: Analog Front End And Front-End Compensation
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage sense Level vsen_ls VSEN vsen_buf 0-2.1V shift Tracking vsadc vref_ls VREF Level vref_buf (0V) shift Figure 7 VSADC block diagram 2.2.1 Analog front end and front-end compensation AFE is composed of: A pair of level shifters connected to the sense and reference input pins (e.g., VSEN/VREF in the case of VS0) •...
Page 20 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage sense A simplified block diagram of the tracking ADC is shown in Figure 8. The summing amplifier amplifies the difference between the buffered differential sensed voltage and the DAC output voltage. The output of the summing amplifier drives the comparator, whose output determines the size and direction of the next step for the tracking integrator.
Page 21: Voltage Sense Processor
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage sense Voltage sense processor The VSP receives the tracking ADC output (the digitized sensed voltage) as its input. Depending on the assignment of the specific module, it processes the incoming data in order to produce: Output and error voltages •...
Page 22: Rectification Voltage Processing
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage sense It should be noted that the VCM output, V , has higher resolution than the V , thus resulting in an error control voltage with the resolution of 156.25 µV. Programmable clamp (register vsp_verrn_clamp_thresh) is applied to limit the maximum error seen by the compensation filter.
Page 23: Vrect Timing For Single Pwm Signal
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage sense • RECT Therefore, while operating in V mode, the tracking ADC only tracks the input when the input voltage is RECT reflected to the secondary-side V . This occurs when the primary-side PWM signal is high or “on”. Note that RECT the identification of the PWM and SR FET PWM outputs is through registers: ce_on_mask0...
Page 24: Deglitcher
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage sense 2.3.2.2 watchdog timer RECT For correct V measurement, the input voltage needs to have certain minimum value in order to trip the RECT vrs_comp comparator. Therefore, a watchdog timer (WDT) is started on the PWM rising edge. This timer monitors the quality of the V signal.
Page 25: Vrect Timing For Two Pwm Signals
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage sense The minimum pulse width (PW) of the deglitcher is programmable via register vrs_min_pw. If this deglitch pulse is wider than the noise ringing pulse width, the false triggering is avoidable. It should be noted that if a non-zero PW is programmed, the comparator output is delayed by the same amount and the tracking start timer should be increased accordingly via register vrs_track_start_thr.
Page 26: Vrect Start-Up Programming
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage sense VRSEN Hold Time Tracking Window Tracking ADC DAC Output Figure 14 sense transient RECT 2.3.2.6 start-up programming RECT At start-up, prior to the first PWM pulse, there is no V pulse on the secondary to be measured.
Page 27: Same Cycle Response
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage sense The terms utilized in the equations are defined as follows: Vin_init is the initial input voltage (i.e., 48 V for a 36 V to 72 V system), and it must be greater than the PMBus •...
Page 28: Vrect Delay Counters
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage sense VRSEN Tracking Window Same Cycle Window vrect output same cycle disabled vrect output same cycle enabled Figure 16 Same cycle mode 2.3.2.8 delay counters RECT The V processing function includes a set of counters. They measure the delay between: RECT Falling (rising) PWM edge driving the synchronous rectification (SR) FETs •...
Page 29: Vs Registers
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage sense VRSEN vrs_comp_ref vrs_comp vspX_cnt_srf2vrsr vspX_cnt_vrscomp_e vspX_cnt_vrsf2srr vspX_cnt_srf_avg vspX_cnt_vrscomp_o vspX_cnt_srr_avg Figure 17 Dead time counters If the counter detects the incoming waveform edges in the incorrect order, it will indicate this through the following status registers: For VS module 1: vsp1_vrsr_b4_srf indicates VRSEN detected VRS comp rising edge before SR FET falling •...
Page 30 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage sense Peripheral Field name Access Address Bits Description 1: Use vs0_step[2:0] (recommended for VSEN) analog vs1_step 7000_0400h [6:4] VS1 (VRSEN) tracking loop step size when automatic step size disabled. Recommended setting is 1 for highest resolution.
Page 31 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage sense Peripheral Field name Access Address Bits Description 7000_1000h (BVSEN) vsen vsp_mode_fe_1p25m 7000_0800h [17] (VSEN) Defines VS FEC DAC LSB weight. 7000_0C00h 0: 0.625 mV (VRSEN) 1: 1.250 mV 7000_1000h (BVSEN) vsen vsp_count_fe_cmp 7000_0800h...
Page 32 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage sense Peripheral Field name Access Address Bits Description on the rising edge of the PWMs indicated in ceX_on_mask0 and ceX_on_mask1 (where X = 0, 1). When the timer exceeds this threshold the V sense moves RECT from its hold phase to its tracking...
Page 33 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage sense Peripheral Field name Access Address Bits Description 2: 16 samples 3: 32 samples common VRS comparator threshold select. vrs_cmp_ref_sel 7000_3018h [27] This threshold is shared by the VRSEN and BVRSEN sense paths. When the rectification voltage exceeds this threshold, the VRS enters its hold phase of operation.
Page 34 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage sense Peripheral Field name Access Address Bits Description will begin vrs_meas_start_thr samples after entering tracking mode for faster FF response. Otherwise V is only updated on RECT the falling PWM edge. 0: Same cycle mode disabled 1: Same cycle mode enabled common...
Page 35 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage sense Peripheral Field name Access Address Bits Description common vsp1_cnt_srf2vrsr 7000_3060h [23:16] Non-averaged VRSEN SR FET falling edge to VRS comp rising edge measurement result. LSB = 5 ns, range = 0 to 1275 ns common vsp1_cnt_vrsf2srr 7000_3060h...
Page 36 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage sense Peripheral Field name Access Address Bits Description common vsp2_cnt_vrsf2srr 7000_3068h [31:24] Non-averaged BVRSEN VRS comp falling edge to SR FET rising edge measurement result. LSB = 5 ns, range = 0 to 1275 ns common vsp2_cnt_vrscomp_e 7000_306Ch [10:0]...
Page 37 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage sense Peripheral Field name Access Address Bits Description when sharing Loop 0 V sense RECT 6: VRSEN: non-pulsed/primary V sense 7: BVSEN_BVRSEN, non- pulsed/primary V sense User manual V 1.2 2024-02-22...
Page 38: Current Sense (Is)
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) Current sense (IS) This chapter describes the current sense module and its submodules in detail. In addition, the user- programmable settings for configuring different current sense features are described and relevant registers provided.
Page 39: Current Sense Module Configuration
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) Driver RECT Driver Driver Copper Driver BIREF PWM2 PWM1 BISEN IREF ISEN SMBALERT# VRSEN SYNC VRREF XDPP1100 VSEN PWRGD VREF To System Aux supply: controller V primary-side drive secondary-side drive Figure 18 PCMC FBFB rectifier with primary and secondary current sensing Current sense module configuration...
Page 40 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) Current sense ADC Current sense Current Current sense To telemetry, fault ISEN estimator processor processor, load-line IREF (CE0) (ISP0) Current sense ADC Current sense Current Current sense To telemetry, fault BISEN estimator processor...
Page 41: Current Sense Analog To Digital Converter
The main requirement for using the integrated current sensing of IPS is to have 1.2 V reference voltage for current sense. An example of supported integrated power stage is Infineon’s IR3555A. Depending on the selected sensing method, the IADC resolution as well as the reference level need to be adjusted, as will be discussed in the following sections.
Page 42: Current Sense Analog Front End
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) error tracking (B)ISEN DELAY pwm_state (B)IREF quantizer (from Dig PWM) Ltrace 9.25 bits compensation synth_i Analog front end (to ISP, Dig PWM) slope estimation vrect vout Current estimator Figure 20 Simplified block diagram of the IADC 3.2.1 Current sense analog front end...
Page 43: Current Estimator
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) based gain stage or IPS. All other applications require the reference level to be ground, except IPS. High-gain mode refers to smaller LSB size and finer resolution. This implies higher noise susceptibility, whereas low-gain mode means higher LSB size and lower noise sensitivity.
Page 44: Pwm State
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) The reconstructed current from the CE drives the AFE DAC in order to center the quantizer at the currently estimated current value. It is also processed downstream by the ISP to be used by the telemetry and fault processing functions.
Page 45 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) Depending on the application, there are different number of FETs that define the on- and off-times in a certain topology. Each FET is controlled by a PWM signal, and for current reconstruction purposes the FETs contributing to the PWM state are relevant for the state programming.
Page 46 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) Figure 22 Buck topology FET naming Table 7 Buck topology PWM state programming example FET PWM Register programming Register value output PWM1 Set bit field values corresponding PWM1 to 1 and other bit ceX_on_mask0 = 001h fields to 0 in ceX_on_mask0 and ceX_on_mask1 ceX_on_mask1 = 001h...
Page 47 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) Figure 24 HBCT topology FET naming Table 9 HBCT PWM state programming example Register programming Register value output PWM1 Set bit field values corresponding PWM1 to 1 and other bit fields ceX_on_mask0 = to 0 in ceX_on_mask0 001h...
Page 48 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) Table 10 HBCD PWM state programming example Register programming Register value output PWM1 Set bit field values corresponding PWM1 to 1 and other bit fields ceX_on_mask0 = to 0 in ceX_on_mask0 001h PWM2 Set bit field values corresponding PWM2 to 1 and other bit fields...
Page 49: Slope Estimator
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) Register programming Register value output PWM11 Set bit field values corresponding PWM9 and PWM11 to 1 and other ceX_off_mask1 = bit fields to 0 in ceX_off_mask1 500h PWM12 Set bit field values corresponding PWM10 and PWM12 to 1 and ceX_off_mask0 = other bit fields to 0 in ceX_off_mask0 A00h...
Page 50 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) Table 13 CE V source ceX_vout_sel CE0 (ISEN) associated V CE1 (BISEN) associated V Loop 0 V Loop 0 V Loop 0 V Loop 0 V Loop 0 V Loop 1 V Loop 0 V Loop 1 V...
Page 51 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) Therefore, assuming L is the inductance at zero current, the parameter ceX_dt_l_slope is computed according to Equation (3.5). �� (3.5) ��_��_��_�� = �� (2 ∗ (( ) − 1) ∗ ��...
Page 52: Error Tracking
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) SECONDARY PRIMARY Figure 28 Primary-side and secondary-side current waveforms While determining the slope for the slope estimator, besides L the magnetizing inductance must also be considered. Therefore, Equation (3.3) is modified to consider the transformer turns ratio by computing the parameter kslope_real according to Equation (3.6).
Page 53: Trace Inductance Of The Pcb Current Sensing
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) ceX_ktrack_on, for on-state • ceX_ktrack_off, for off-state • ceX_ktrack_hiz, for high impedance state • In addition, register ceX_iterm defines an integral coefficient which is applied across all states if set to a non- zero value.
Page 54: Adc Codes To Amps
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) Tracking isp_track_fault_en fault isp_err_ratio_sel is_track_fault (To fault block) ierr (from AFE quantizer) Peak ce_current_limit pcl_fault current limit (To digital PWM) Short circuit isp_scp_thresh scp_fault fault (To fault block) Negative isp_ncl_thresh ncl_fault current limit...
Page 55: Peak Current Limiting
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) The selection over which switching cycle the current is averaged is done via register isp_fsw_sync_sel. The user can decide whether the switching cycle is averaged over Loop 0 or Loop 1. The averaged current is further processed downstream in the telemetry and fault blocks.
Page 56: Error Tracking Fault Detection
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) 3.3.5 Error tracking fault detection Error tracking fault detects the inability of the IADC tracking mechanism to track the input. This fault typically indicates a board-level problem, for instance one of the ISEN/IREF inputs is not connected properly. The tracking fault detection is enabled by setting ispX_track_fault_en to 1.
Page 57: Current Sense Registers
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) Lower-valued settings of ispX_err_ratio_sel are very sensitive and may cause false fault declaration, particularly in noisy current sense environments. Therefore, it is recommended to use only the higher-valued ispX_err_ratio_sel settings of 6 or 7. Current sense registers The relevant current sense registers and their descriptions are provided in Table...
Page 58 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) Peripheral Field name Access Address Bits Description current sense and for the boost topology. LSB = 1/16 V/V, range = 0 to 15/16 V/V ce_ktrack_on 7000_2400h [11:8] Current sense tracking gain in the isen (ISEN) on-state.
Page 59 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) Peripheral Field name Access Address Bits Description (e.g., primary FETs in a bridge topology). In bridge topologies there are two on-states per switching cycle. ce_on_mask0 defines the first (even) on-state and ce_on_mask1 defines the second (odd) on-state.
Page 60 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) Peripheral Field name Access Address Bits Description Q2, Q4 Buck HSFET isen ce_dt_l_slope 7000_2404h [31:24] Defines the slope of the output (ISEN) inductance dependence on current. 7000_2804h Although actual inductor variation with current is non-linear, this (BISEN) compensation introduces a linear...
Page 61 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) Peripheral Field name Access Address Bits Description && !ON where [0] corresponds to PWM1, [11] corresponds to PWM12 and on is defined by ce_on_mask0 and ce_on_mask1 Secondary topology set: ce_off_mask0 bits corresponding SR2, SR4 Buck...
Page 62 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) Peripheral Field name Access Address Bits Description 7000_2808h Computed as follows: (BISEN) ce_ltrace = L / (R * dt) trace trace where = parasitic trace inductance trace being compensated = current sense trace trace resistance...
Page 63 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) Peripheral Field name Access Address Bits Description ADC feedback if the falling PWM edge causes noise on the current sense signal. LSB = 40 ns, range = 0 to 280 ns isen ce_blank_pe_dly 7000_240Ch...
Page 64 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) Peripheral Field name Access Address Bits Description 4: V (VRSEN/VRREF) RECT 5: BV (BVRSEN/BVRREF) RECT 6: pid_ff_vrect_override 7: PRISEN CE1 (BISEN): 0: V (VRSEN/VRREF) RECT 1: BV (BVRSEN/BVRREF) RECT 2: pid_ff_vrect_override 3: PRISEN 4: Loop 0 V...
Page 65: Current Sense Pmbus Commands
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) Peripheral Field name Access Address Bits Description isp_err_ratio_sel 7000_2414h [3:1] Current sense tracking fault error isen (ISEN) ratio select. 7000_2814h 0: 4 (11.1 percent threshold) (BISEN) 1: 8 (20.0 percent threshold) 2: 12 (27.3 percent threshold) 3: 16 (33.3 percent threshold) 4: 24 (42.9 percent threshold)
Page 66 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sense (IS) Command name Access Length Address Bits Description [15:0] Current sense APC. MFR_IOUT_APC Word Linear11 format with suggested exponent -8 or -9 depending on magnitude. Unit = amps User manual V 1.2 2024-02-22...
Page 67: Telemetry Sense
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry sense Telemetry sense This chapter introduces the telemetry sense (TS) functionality and the relevant registers. The TS module performs analog-to-digital conversion for the following modules: Temperature telemetry • Input voltage telemetry •...
Page 68 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry sense mux2_sel 0.6 V PRISEN IMON 2 MHz LPF (A)TSEN 2 MHz LPF MUX2 TSADC Input BTSEN 2 MHz LPF XADDR1 XADDR2 mux1_sel Int. Temp 60k Res 2 MHz LPF MUX1 Figure 32 TS input muxes The TS module contains eight timing slots with sequencing defined by the register ts_muxmode as provided in...
Page 69 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry sense Table 20 MUX2 selection ts_muxctrl2 MUX2 output 0.6 V reference (test only) PRISEN IMON ATSEN BTSEN XADDR1 XADDR2 MUX1 output In addition to ts_muxmode, ts_muxctrl1 and ts_muxctrl2, the following registers are required to enable an input for ADC conversion: PRISEN •...
Page 70: Telemetry Sense Current Dac
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry sense ts_muxctrl1 0 (ITSEN) ts_muxctrl2 1 (PRISEN) 7 (MUX1) 6 (XADDR2) clk_25mhz clk_tsadc sample sample sample PRISEN ITSEN convert PRISEN ts_adc[9:0] ATSEN ADC output (mux_mode=7) PRISEN ADC output prisen_adc[13:0] Previous PRISEN ADC output Current PRISEN ADC output prisen_update Previous V...
Page 71: Sequencer
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry sense clk_25mhz clk_tsadc ts_mux1_sel[1:0] mux1_sel[1:0] ts_mux2_sel[2:0] mux2_sel[2:0] ts_muxmode[2:0] prisen_update Sequencer imon_update atsen_update btsen_update itsen_update xaddr1_update xaddr2_update demux_sel[2:0] prisen_adc[13:0] imon_adc[13:0] atsen_adc[13:0] Gain and offset btsen_adc[13:0] ts_adc[9:0] correction itsen_adc[13:0] xaddr1_adc[13:0] xaddr2_adc[13:0] vin[11:0] compute Int.
Page 72: Internal Temperature (Itsen) Computation
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry sense 4.4.3 computation When V is measured using the PRISEN input, the TSP can compute V from the ADC codes. This is performed based on the following registers and according to Equation (4.1): vin_pwl_slope •...
Page 73: X-Valent Measurement
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry sense ptat_temp_trim = 0 • A register, temp_min, is provided to clamp the minimum computed internal temperature. The default setting for this parameter is -128°C. After the clamp, the internal temperature is low-pass filtered at a fixed BW of 0.48 kHz.
Page 74: Telemetry Sense Registers
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry sense XADDR resistance (Ω) 16-value XADDR decode 4700 6070 8000 10200 13200 17200 22470 29200 39000 56000 The decoded results are available on read-only registers tlm_xaddr1_pinset and tlm_xaddr2_pinset. Alternatively, a user-defined FW patch may be used to measure the XADDR1, two-resistor programming. The following settings should be used: HW measurement is disabled by setting registers xv_pinset1_meas = 0 and xv_pinset2_meas = 0 •...
Page 75 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry sense Peripheral Field name Access Address Bits Description IMON measurement will occur, even if selected by ts_muxmode and ts_muxctrl2. 0: Disabled 1: Enabled tsen atsen_meas_en 7000_4C00h TSADC ATSEN input measurement enable. When enabled, the TSADC will measure the ATSEN input when selected by ts_muxmode and tx_muxctrl2.
Page 76 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry sense Peripheral Field name Access Address Bits Description temperature sense element. The current source may be disabled to use the BTSEN input as a general- purpose ADC input. 0: Disabled 1: Enabled tsen ts_tsidac_imon_sel 7000_4C00h...
Page 77 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry sense Peripheral Field name Access Address Bits Description measure the internal temperature of the controller. 0: ITSEN 1: 60 K resistor (test only) 2: XADDR1 filtered 3: XADDR2 filtered tsen ts_muxctrl2 7000_4C00h [19:17] TSADC MUX2 input source select.
Page 78 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry sense Peripheral Field name Access Address Bits Description tsen ptat_0c_code 7000_4C08h [10:0] ITSEN 0°C code. Internal temperature computed as: Int. temp. = (ADC - 0C_code) * pwl_slope + temp_trim LSB = 0.25 ADC codes, range = 0.0 to 511.75 ADC codes tsen temp_min...
Page 79 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry sense Peripheral Field name Access Address Bits Description LSB = 0.0625 ADC code, range = 0.0 to 1023.9375 ADC codes tsen ts_btsen_adc 7000_4C20h [13:0] Gain and offset corrected BTSEN TSADC output. LSB = 0.0625 ADC code, range = 0.0 to 1023.9375 ADC codes tsen...
Page 80 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry sense Peripheral Field name Access Address Bits Description output 1: Use idac_fw_frc User manual V 1.2 2024-02-22...
Page 81: Voltage Control
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage control Voltage control This chapter introduces the voltage control module and its submodules, as well as describing the relevant registers and PMBus commands. The purpose of the voltage control module is to set the control or reference voltage with respect to which the output voltage is regulated.
Page 82: Pmbus Commands To Hw Parameters
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage control PMBus commands to HW parameters The voltage control module implements the PMBus reference voltage generation model from a high-level perspective, as described in the PMBus Specification, Part II, Revision 1.3.1, section 9.2 and shown in Figure PMBus commands are converted to module input parameters by FW, as shown in Figure...
Page 83 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage control A simplified block diagram of the ramp generator is shown in Figure 40, where the target output voltage consists of the sum of the following registers: vc_vramp_target, which is the VSEN referenced target voltage computed by FW from PMBus commands •...
Page 84: Interrupts
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage control Care should be taken if using this feature during active regulation, because the power stage may not be capable of tracking large steps in the target voltage without significant overshoot/undershoot. The ramp generator also provides the following read-only status registers: vc_vcontrol_at_target indicates vcontrol_ramp is at the target voltage and is no longer slewing •...
Page 85: Droop Voltage Computation
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage control VOUT_MAX MFR_RDROOP_RLL_NEG VOUT_DROOP (SEG1) VOUT_COMMAND MFR_RDROOP_RLL_SEG2 MFR_RDROOP_RLL_SEG3 VOUT_MIN Figure 42 Multi-segment droop: V vs. I The first positive segment (SEG1) is the standard operating droop, which is programmed through the PMBus command VOUT_DROOP.
Page 86 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage control ��_��_��_��∗��_��_�� (5.12) ��_��_��_�� = (��+9) (5.13) �� = −1 ∗ ��11 �� _��_��_�� It should be noted that the vc_vavp_rll_xxx registers are relative to VSEN while the PMBus droop commands are relative to the output voltage.
Page 87: Droop Voltage Filtering
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage control Table 24 Computed droop voltage by segment at high BW and low BW LPF inputs Segment Current range vdroop_hibw vdroop_lobw I < 0 I * rll_neg seg1 0 < I < ithr_seg2 I * rll seg2 ithr_seg2 <...
Page 88: Output Summation And Clamping
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage control vc_vavp_kfp kfp kfp_real F3db (kHz) vc_vavp_kfp kfp kfp_real F3db (kHz) 0.0001 0.43 0.0017 6.81 0.0001 0.49 0.0020 7.79 0.0002 0.61 0.0024 9.74 0.0002 0.73 0.0029 11.69 0.0002 0.85 0.0034 13.65 0.0002 0.97 0.0039...
Page 89: Voltage Control Registers
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage control ��_��∗��_��_��∗50 (5.15) ��_��_��_�� = (24) Read-only registers vc_over_vout_max and vc_under_vout_min indicate when these clamp voltages are exceeded at the summation output and the clamp is applied. Additionally, they go to the fault module for reporting on STATUS_VOUT.
Page 90 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage control Peripheral Field name Access Address Bits Description F3db(MHz) = [kfp/(1-kfp)] * 25 MHz / 2 * pi vcontrol vc_vramp_target 7000_1404h [14:0] Ramp target value referenced to (vcontrol0) VSEN input (i.e., after scaling by 7000_1804h VOUT_SCALE_LOOP).
Page 91 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage control Peripheral Field name Access Address Bits Description vcontrol vc_vramp_on 7000_1404h [24] When high, indicates the ramp (vcontrol0) should respond to target changes 7000_1804h and that that loop is actively (vcontrol1) regulating.
Page 92 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage control Peripheral Field name Access Address Bits Description LSB = 20 ns, range = 0.0 to 1.3107 ms vcontrol vc_vavp_itot_delta 7000_140Ch [12:0] Total current offset term applied to (vcontrol0) droop computations only. Allows 7000_180Ch FW to apply offset to HW computed (vcontrol1)
Page 93 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage control Peripheral Field name Access Address Bits Description vcontrol vc_vcontrol_vout_min 7000_1418h [15:8] min. limit referenced to VSEN (vcontrol0) input (i.e., after scaling by 7000_1818h VOUT_SCALE_LOOP. Target (vcontrol1) voltages (including droop) below this limit will be clamped to this level.
Page 94 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage control Peripheral Field name Access Address Bits Description vcontrol vc_vcontrol_at_target 7000_1424h Status flag indicating the V control (vcontrol0) ramp is at the target voltage. 7000_1824h 0: Ramp not at target voltage (vcontrol1) 1: Ramp at target voltage vcontrol...
Page 95 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage control Peripheral Field name Access Address Bits Description commands as follows: vc_vavp_rll_seg3(U9.1) = MFR_RDROOP_RLL_SEG3(Ux.y) * VOUT_SCALE_LOOP(U0.16) / (2^y * 2^(16-1)) where y = -1 * LINEAR11 exponent of MFR_RDROOP_RLL_SEG3 LSB = 0.5 mΩ, range = 0.0 to 511.5 mΩ...
Page 96: Voltage Control Pmbus Commands
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage control Peripheral Field name Access Address Bits Description +vc_vavp_itot_delta 1: vc_vavp_otpt_uc_sel Voltage control PMBus commands The relevant voltage control-related PMBus commands are given in Table Table 28 Voltage control-related PMBus commands Command name Access Length Address Bits Description...
Page 97 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage control Command name Access Length Address Bits Description Format is ULINEAR16 with the exponent defined by VOUT_MODE[4:0]. VOUT_MARGIN_LOW Word [15:0] Defines the output voltage when selected by the OPERATION command. Format is ULINEAR16 with the exponent defined by VOUT_MODE[4:0].
Page 98 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Voltage control Command name Access Length Address Bits Description than MFR_RDROOP_ITHR_SEG3. Format is LINEAR11. [63:48] MFR_RDROOP_RLL_SEG3: Sets the V droop rate in mV/A when I exceeds MFR_RDROOP_ITHR_SEG3. Format is LINEAR11. [79:64] MFR_RDROOP_RLL_NEG: Sets the V droop rate in mV/A when I negative.
Page 99: Compensator
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Compensator Compensator This chapter describes in more detail the XDPP1100 compensator implementation and main functionality. The relevant user-programmable parameters and corresponding registers are discussed as well as the input FF term and its relevant settings. Most of this chapter assumes that compensator output is directly the duty cycle as in VMC, and in section 6.3 PCMC and its relevant compensator-related register settings are shown.
Page 100: Pre-Filter
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Compensator pid_kp_index_1ph for K • pid_ki_index_1ph for K • pid_kd_index_1ph for K • The PID provides a pole in the origin and two mid-band zeros while the LPFs present two high-frequency poles. This corresponds to the Type III compensation response which can provide up to 180 degrees of phase boost.
Page 101 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Compensator The filter coefficient parameters use an exponent mantissa format to provide an extended range utilizing fewer total bits. The upper three bits of kfp1_index represent the exponent and the lower three bits represent the mantissa.
Page 102 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Compensator kfp_index kfp_real 0.0063 0.0068 0.0073 0.0078 0.0088 0.0098 0.0107 0.0117 0.0127 0.0137 0.0146 0.0156 0.0176 0.0195 0.0215 0.0234 0.0254 0.0273 0.0293 0.0313 0.0352 0.0391 0.0430 0.0469 0.0508 0.0547 0.0586 0.0625 0.0703 0.0781 0.0859 0.0938...
Page 103: Pid Term Computation
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Compensator Compensator pre- and post-filter bandwidth (kHz) 1000.00 100.00 10.00 1.00 kfp_index Figure 48 Pre- and post-filter BW as a function of kfp_index 6.1.2 PID term computation The PID coefficients are computed based on the pre-filter output signals: Proportional (P_term) and integral (I_term) terms are obtained from the filtered error signal verrn_filt •...
Page 104 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Compensator U-4.15 Clamp verrn_filt S4.19 S4.16 S8.4 p_term pd_term S8.16 U8.10 d_term Clamp verrn_slope S7.16 S7.7 S15.17 S1.16 U-14.25 S1.16 Clamp S-6.29 i_term accum S1.16 Figure 49 PID computation block diagram Similarly to the pre-filter, the PID parameters use an exponent mantissa format to provide an extended range using fewer total bits: The upper three bits of K _index and K...
Page 105 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Compensator _index _real 0.0005 0.0005 0.0005 0.0006 0.0007 0.0007 0.0008 0.0009 0.0009 0.0010 0.0011 0.0012 0.0013 0.0015 0.0016 0.0017 0.0018 0.0020 0.0022 0.0024 0.0027 0.0029 0.0032 0.0034 0.0037 0.0039 0.0044 0.0049 0.0054 0.0059 0.0063 0.0068...
Page 106 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Compensator _index _real 0.0146 0.0156 0.0176 0.0195 0.0215 0.0234 0.0254 0.0273 0.0293 1024 0.0313 1152 0.0352 1280 0.0391 1408 0.0430 1536 0.0469 1664 0.0508 1792 0.0547 1920 0.0586 Correspondingly, the integer and real number representations of K are computed as given in Equations (6.11) to (6.14).
Page 107 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Compensator _index _real 5.96E-07 6.56E-07 7.15E-07 7.75E-07 8.34E-07 8.94E-07 9.54E-07 1.07E-06 1.19E-06 1.31E-06 1.43E-06 1.55E-06 1.67E-06 1.79E-06 1.91E-06 2.15E-06 2.38E-06 2.62E-06 2.86E-06 3.10E-06 3.34E-06 3.58E-06 3.81E-06 4.29E-06 4.77E-06 5.25E-06 5.72E-06 6.20E-06 6.68E-06 7.15E-06 7.63E-06 8.58E-06...
Page 108 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Compensator _index _real 1.91E-05 2.10E-05 2.29E-05 2.48E-05 2.67E-05 2.86E-05 1024 3.05E-05 1152 3.43E-05 1280 3.81E-05 1408 4.20E-05 1536 4.58E-05 1664 4.96E-05 1792 5.34E-05 1920 5.72E-05 The integer and real number representations of K are computed as provided in Equations (6.15) to (6.18).
Page 109 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Compensator _index _real 0.0273 0.0293 0.0313 0.0352 0.0391 0.0430 0.0469 0.0508 0.0547 0.0586 0.0625 0.0703 0.0781 0.0859 0.0938 0.1016 0.1094 0.1172 0.1250 0.1406 0.1563 0.1719 0.1875 0.2031 0.2188 0.2344 0.2500 0.2813 0.3125 0.3438 0.3750 0.4063...
Page 110 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Compensator _index _real 0.8750 0.9375 1024 1.0000 1152 1.1250 1280 1.2500 1408 1.3750 1536 1.5000 1664 1.6250 1792 1.7500 1920 1.8750 2048 2.000 2304 2.250 2560 2.500 2816 2.750 3072 3.000 3328 3.250 3584 3.500...
Page 111: Post-Filter And Summation
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Compensator _index _real 28672 28.000 30720 30.000 32768 32.000 36864 36.000 40960 40.000 45056 44.000 49152 48.000 53248 52.000 57344 56.000 61440 60.000 65536 64.000 73728 72.000 81920 80.000 90112 88.000 98304 96.000 106496 104.000...
Page 112 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Compensator The compensator duty cycle output is created by adding the post-filtered output to: Integral term output, I_term • Voltage FF term, ff_duty • The implementation of the post-filter is illustrated in Figure U-3.13 U-3.13...
Page 113: Input/Output Clamping Of The Compensation Filter
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Compensator 6.1.4 Input/output clamping of the compensation filter The input and the output of the PID filter can be clamped. The input clamp is user-programmable through register vsp_verrn_clamp_thresh, as discussed in section 2.3.1, and it limits the maximum error seen by the compensation filter.
Page 114: Freeze, Reset Accumulator
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Compensator 6.1.7 Freeze, reset accumulator Undesired integrator “windup” could occur in the following operating conditions: Burst mode (BM) operation, when PID is not controlling the output duty cycle. • Duty cycle output is 0 and a negative V input is received.
Page 115: Output Voltage Target Computation
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Compensator 6.2.1 Output voltage target computation The target output voltage is required for the FF computation. In order to use the representation of the true V the internal reference voltage, V , needs to be scaled. The target output voltage can be computed as given control in Equation (6.28).
Page 116: Override And Adjustment Options For Ff
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Compensator Primary side: The sensed input voltage needs to be scaled by the transformer turns ratio. This is performed • through register pid_ff_i82_div_trans_scale_loop. This value is computed automatically by the FW based on the PMBus command MFR_TRANSFORMER_SCALE.
Page 117 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Compensator (6.29) �� _�� = ��_��_��_��[4: 2] �� (6.30) �� _�� = 4 + ��_��_��_��[1: 0] �� _�� −9 (6.31) �� = �� _�� ∗ 2 ∗ 2 �� ...
Page 118: Control Mode Selection - Peak Current Mode
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Compensator Control mode selection – peak current mode This section describes the selection of control mode in more detail, focusing on the compensator-related register settings for PCMC. However, most PCMC-related circuitry and detailed functionality is discussed in the PWM chapter that follows.
Page 119: Compensation Filter Registers
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Compensator Both the duty cycle and FF must be above their corresponding thresholds, pid_osp_duty_thr and pid_osp_ff_thr, in order to prevent false fault detection at low voltages during start-up, when duty cycle is much larger than the FF (e.g., at V = 0 V).
Page 120 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Compensator Peripheral Field name Access Address Bits Description OP - V(VSEN) 0: Clamp range = -40 to 40 mV 1: Clamp range = -80 to 80 mV 2: Clamp range = -120 to 120 mV 3: Clamp range = -160 to 160 mV 4: Clamp range = -200 to 200 mV 5: Clamp range = -240 to 240 mV...
Page 121 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Compensator Peripheral Field name Access Address Bits Description pid_ff_override (e.g., to override the HW-computed FF with a FW computation appropriate for boost or buck-boost derived topologies). 0: VS1 (VRSEN) V RECT 1: VS2 (BVSEN_BVRSEN) V RECT 2: TS V (e.g., PRISEN)
Page 122 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Compensator Peripheral Field name Access Address Bits Description 7000_2004h ki_man = 8 + pid_ki_index_1ph[2:0] (pid1) ki = ki_man * 2^ki_exp * 2^-25 pid_kd_index_1ph 7000_1C04h [30:24] PID derivative coefficient index. (pid0) Note that index settings greater 7000_2004h than 119 are clamped to 119.
Page 123 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Compensator Peripheral Field name Access Address Bits Description 7000_201Ch BVRSEN). Used only when selected by pid_ff_vrect_sel. If computing (pid1) from V pid_ff_vrect_override(U12.0) = (V) * 800 * MFR_VRECT_SCALE(U0.12) * MFR_TRANSFORMER_SCALE(U0.12) / (2^12 * 2^12) LSB = 1.25 mV, range = 0.0 to 5.11875 V pid_ff_override...
Page 124 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Compensator Peripheral Field name Access Address Bits Description MFR_TRANSFORMER_SCALE[9:0] pid_ff_i82_div_trans_scale_loop(U- 4.23) = quot1(U5.7) * 82 (U-9.16) LSB = 2^-23, range = 0.0 to 0.0625 pid_kp_eff 7000_1C28h [5:0] PID K coefficient value after V RECT (pid0) scaling.
Page 125 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Compensator Peripheral Field name Access Address Bits Description 1: PCMC on secondary 2: PCMC on primary 3: Reserved ramp0_force_duty 7000_2C34 [7:0] Forced duty-cycle value overrides ramp0 input when selected by ramp0_force_duty_en. Because this force is applied at the ramp input, upstream adjustments to the duty cycle such as current balance...
Page 126: Digital Pulse Width Modulator
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Digital pulse width modulator This chapter discusses the digital pulse width modulator (PWM) and its implementation in more detail. Applicable feedback control modes and BM, as well as the fast-transient operation, are described and the relevant register settings are provided.
Page 127: Pwm Ramp Generator
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator pwm_force_hi[0] pwm1_loop_map[1] pwm_force_lo[0] pwm1_rise_sel pwm1_dr pwm1_fall_sel pwm1_df additional control signals Pulse Gen 1 Interpolator 1 PWM1 ramp0_tswitch pidX_duty Ramp Gen 0 pidX_ftr_mode pidX_ovs_mode ce0_synth_i Pulse Gen 2 Interpolator 2 internal sync external sync PWM2...
Page 128 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Table 35 Typical settings of the register rampX_pid_sel Topology ramp0_pid_sel ramp1_pid_sel Single loop, single-phase Single loop, interleaved Dual loop In order to generate the PWM pulses, the ramp generator produces the timing information based on a timing ramp.
Page 129: Pwm Ramp Modulation Schemes
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator In bridge mode, the two halves of the switching cycle are identified as either the even half-cycle or the odd half- cycle, as shown in the bottom part of Figure 55.
Page 130 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator ramp count = ramp_max Ramp Count ramp count = 0 t1 = 0 t1 = 0 t1 = 0 t1 = 0 a) t1, t2 placement using trailing edge modulation ramp count = ramp_max Ramp Count ramp count = 0...
Page 131: Pwm Ramp Synchronization
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator The pulse width, t2 – t1, for all modulation schemes is given in Equation (7.2): (7.2) �� − �� = �� ∗ ��_�� D is the duty-cycle output of the compensation filter in the case of VMC. It should be noted that the pulse generator is also capable of creating a pulse with LE at t2 and TE at t1.
Page 132 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator ramp0 ramp1 SYNC ramp0_phase ramp1_phase a) External sync on non-bridge topology (rampX_half_mode = 0) ramp0 ramp1 SYNC ramp0_phase ramp1_phase b) External sync on bridge topology (rampX_half_mode = 1) Figure 57 External sync phase programming for non-bridge and bridge topologies In order to synchronize to the external signal, various IO pins of the XDPP1100 can be used.
Page 133: Pwm Pulse Generator
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator When a selected IO pin is mapped as an input, the sync function synchronizes to the rising edge of the provided sync pulse. A 40 ns deglitcher is available on the sync input and it is enabled by setting register sync_deglitch_en to 1.
Page 134: Ramp Selection (Loop/Phase)
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Low-side FETs in a non-isolated buck topology • SR FETs in non-isolated boost or buck-boost topologies • In both masks, bit [0] corresponds to PWM1 and bit [11] corresponds to PWM12. In addition, during the diode emulation operating mode (e.g., during diode emulation start-up), the mask pwm_srfet_mask[11:0] identifies for the FW which PWM outputs should be disabled.
Page 135 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator pwmY_rise_sel PWM rising edge selection VRSEN falling edge 9 - 15 BVRSEN falling edge The selection for the rising edge depends on the topology. Typical selections are for: Non-bridge topologies: t1 or t2, creates an edge on every t1 or t2 event •...
Page 136: Dead Time Programming
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Ramp 0 ramp0_t1 t1 even t1 odd t1 even ramp0_t2 t2 even t2 odd t2 even Ramp 1 programmed with 180 degree shift ramp1_t1 t1 even t1 odd t1 even ramp1_t2 t2 odd...
Page 137 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator ramp count = ramp_max Ramp ramp count = 0 PWMY pwmY_dr pwmY_df Figure 59 Dead time programming Table 40 PMBus command PWM_DEADTIME mapping to pwmY_dr and pwmY_df PWM_DEADTIME[7:0] pwm1_df[7:0] PWM_DEADTIME[103:96] pwm7_df[7:0]...
Page 138: Force High Force Low
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator It should be noted that I polling for this FW-based function occurs at a 1 ms rate. More complex dead time adjustment algorithms are additionally possible using a user-written FW patch. It is important to note that in order to synchronously and simultaneously update all the dead time changes, an update to any of the dead time parameters (pwmY_dr or pwmY_df) becomes effective only after the register containing pwm12_dr and pwm12_df is written.
Page 139 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator ramp_force_t1, ramp_force_t1_en ramp_force_t2, ramp_force_t2_en Ramp ramp_half_mode even_cycle ramp_max ramp ibal_duty_adj pulse ramp t1_val pw_even t1_crossing pid_duty width cross ramp_pw detect ramp_force_duty t1,t2 pw_odd t2_val t2_crossing ramp_force_duty_en Hold flux_duty_adj ramp_m_flavor ramp_dutyc_lock ramp_max...
Page 140: Peak Current Mode Control
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator 7.3.2 Peak current mode control PCMC is based on current information and it can be selected by setting the register value mode_control_loopX to 1 for secondary-side PCMC or to 2 for primary-side PCMC. In the case of PCMC the compensator output represents the control current, whereas for VMC it was directly the duty cycle.
Page 141: Maximum And Minimum Pulse Width Enforcement
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator determine the convergence rate of these two signals, the PCMC cross-detect function uses the slope information from both the slope compensation ramp and the CE. This convergence rate information is used to: predict the t2 crossing in the next clock cycle •...
Page 142: Forced Duty Cycle T1, T2
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator 7.3.4 Forced duty cycle T1, T2 The XDPP1100 provides several methods through different registers for overriding the HW computed duty cycle or PW. The registers used for overriding the duty cycle are: pid_force_duty and pid_force_duty_en •...
Page 143: Burst Mode
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator It should be noted that for DE modulation (if the pulse on and off times allow), it is possible to use interrupts on t1 and t2 (see section 7.6) in order to change rampX_force_duty between edges.
Page 144: Fast-Transient Response
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator −16 ��_��_��∗��_��_��∗2 (7.11) ��_��_��_��_��ℎ�� = 1.25�� Where Vout_burst_err is the amount (in volts) that the output voltage must drop in order to trigger the start of the next burst and VOUT_SCALE_LOOP is the PMBus command defining the V resistor divider ratio.
Page 145 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator PRIMARY LOAD LOAD verr_slope_entry_thrs verr_slope_exit_thrs verr_entry_thrs verr_exit_thrs Figure 63 Fast-transient response waveform Two registers control the entry into the fast-transient response mode. These are: pid_verr_entry_thrs, which defines the error voltage (V = target voltage –...
Page 146: Fast-Transient Response - Load Release
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator On converter disable it is reset again to 0. • The register value does not need to be stored in OTP to be effective and, like most other registers, changes while regulating are permitted (e.g., to fine-tune response).
Page 147: Pwm Interrupts
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator PRIMARY SWITCH LOAD LOAD ovs_exit_thrs ovs_slope_exit_thrs ovs_entry_thrs ovs_slope_entry_thrs Figure 64 Fast-overshoot response waveform The fast-overshoot response mode is enabled by setting the register pid_ovs_entry_thrs to any non-zero value. While programming this register, it should be noted that: At the system boot the FW reads and saves the setting of pid_ovs_entry_thrs and then sets it to 0.
Page 148: Pwm Registers
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator In addition to setting an interrupt on t1 and t2: Register rampX_t1_irq_sel may also select an arbitrary phase location within the ramp for an interrupt. The • phase location is defined by the register rampX_irq_phase. Its value is defined according to Equation (7.14). Register rampX_t2_irq_sel may also select the falling edge of V to generate the interrupt.
Page 149 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description topologies and disabled otherwise. 0: Half-mode disabled (non-bridge topology) 1: Half-mode enabled (bridge topology) ramp0_min_pw_stat 7000_2C00h Selects pulse generator response when PW computed from PID duty cycle is less than ramp0_pw_min.
Page 150 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description half of T , otherwise it is equal to switch . Half-mode should be enabled switch for bridge type primary-side topologies and disabled otherwise. 0: Half-mode disabled (non-bridge topology) 1: Half-mode enabled (bridge...
Page 151 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description compensation_slope 7000_2C00h [19:18] Defines the compensation ramp slope when PCMC selected as modulation type by mode_control_loop0 or mode_control_loop1. This single register applies to both loops in the case of a dual-loop system.
Page 152 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description designations are for use with bridge topologies to distinguish between half-cycles. The VRSEN and BVRSEN options allow a PWM output to be set high after detection of the falling transition of the rectification voltage.
Page 153 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description 0.5 * T and T for bridge switch switch topologies) and t1 is modulated. When using DE modulation, t1 and t2 are centered around 0.5 * T switch (or 0.25 * T and 0.75 * T...
Page 154 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description pwm3_rise_sel 7000_2C04h [20:17] Topology-driven PWM3 rising edge select. t1 and t2 refer to the modulated edges created by the ramp. When using TE modulation, t1 is fixed at time 0 and t2 is modulated.
Page 155 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description 1: t2 2: t1 even cycle 3: t2 even cycle 4: t1 odd cycle 5: t2 odd cycle 6: t1 delay 7: t2 delay pwm4_rise_sel 7000_2C04h...
Page 156 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description (or 0.25 * T and 0.75 * T switch switch bridge topologies) and both are modulated. Odd and even cycle designations are for use with bridge topologies to distinguish between half-cycles.
Page 157 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description t1 is fixed at time 0 and t2 is modulated. When using LE modulation, t2 is fixed at T switch 0.5 * T and T for bridge switch...
Page 158 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description 7: t2 delay 8: VRSEN neg. edge 9 to 15: BVRSEN neg. edge pwm7_fall_sel 7000_2C08h [16:14] Topology-driven PWM7 falling edge select. t1 and t2 refer to the modulated edges created by the ramp.
Page 159 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description 0: t1 1: t2 2: t1 even cycle 3: t2 even cycle 4: t1 odd cycle 5: t2 odd cycle 6: t1 delay 7: t2 delay 8: VRSEN neg.
Page 160 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description topologies to distinguish between half-cycles. The VRSEN and BVRSEN options allow a PWM output to be set high after detection of the falling transition of the rectification voltage.
Page 161 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description topologies) and t1 is modulated. When using DE modulation, t1 and t2 are centered around 0.5 * T switch (or 0.25 * T and 0.75 * T switch switch...
Page 162 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description pwm10_rise_sel 7000_2C0Ch [13:10] Topology-driven PWM10 rising edge select. t1 and t2 refer to the modulated edges created by the ramp. When using TE modulation, t1 is fixed at time 0 and t2 is modulated.
Page 163 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description 1: t2 2: t1 even cycle 3: t2 even cycle 4: t1 odd cycle 5: t2 odd cycle 6: t1 delay 7: t2 delay pwm11_rise_sel 7000_2C0Ch...
Page 164 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description (or 0.25 * T and 0.75 * T switch switch bridge topologies) and both are modulated. Odd and even cycle designations are for use with bridge topologies to distinguish between half-cycles.
Page 165 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description 2: Loop 1, phase 0 3: Loop 0, phase 1 pwm2_loop_map 7000_2C10h [3:2] Defines the loop and phase mapping of the PWM2 output. 0: PWM not in use 1: Loop 0, phase 0 2: Loop 1, phase 0...
Page 166 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description 2: Loop 1, phase 0 3: Loop 0, phase 1 pwm10_loop_map 7000_2C10h [19:18] Defines the loop and phase mapping of the PWM10 output. 0: PWM not in use 1: Loop 0, phase 0 2: Loop 1, phase 0...
Page 167 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description max. duty-cycle limit is scaled with respect to the V reference defined by parameter pid1.pid_vrect_ref as shown below. Max. duty = ramp1_dc_max_nom * pid_vrect_ref/V RECT A setting of 0 will disable the scaled...
Page 168 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description ramp1_phase 7000_2C20h [7:0] ramp1 phase alignment with respect to sync signal selected with ramp1_sync_sel. Computed by FW from PMBus command as follows: ramp1_phase = 2^8 * PAGE1.INTERLEAVE[3:0]/ PAGE1.INTERLEAVE[7:4]...
Page 169 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description determined by the setting of ramp0_pw_min_state. Computed by FW from PMBus as follows: ramp0_pw_min = MFR_MIN_PW LSB = 5 ns, range = 0 to 1275 ns ramp0_force_duty 7000_2C34h [7:0]...
Page 170 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description ramp0_force_t2_en 7000_2C3Ch [11] PWM ramp0 t2 force enable. 0: t2 determined by modulation scheme and duty cycle 1: t2 set by ramp0_force_t2 tswitch1 7000_2C40h [8:0]...
Page 171 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description ramp1_force_duty_e 7000_2C48h PWM ramp1 forced duty-cycle select. 0: Use PID computed duty cycle 1: Use ramp1_force_duty ramp1_force_t1 7000_2C4Ch [10:0] PWM ramp1 forced t1 setting selected by ramp1_force_t1_en.
Page 172 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description LSB = 1.25 ns, range = 0.0 to 318.75 ns pwm1_df 7000_2C54h [15:8] PWM1 falling edge delay (dead) time from t1 or t2. Mapping of the falling edge to t1 or t2 defined by pwm1_fall_sel.
Page 173 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description LSB = 1.25 ns, range = 0.0 to 318.75 ns pwm3_dr 7000_2C5Ch [7:0] PWM3 rising edge delay (dead) time from t1 or t2. Mapping of the rising edge to t1 or t2 defined by pwm3_rise_sel.
Page 174 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description pwm4_df 7000_2C60h [15:8] PWM4 falling edge delay (dead) time from t1 or t2. Mapping of the falling edge to t1 or t2 defined by pwm4_fall_sel.
Page 175 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description pwm6_dr 7000_2C68h [7:0] PWM6 rising edge delay (dead) time from t1 or t2. Mapping of the rising edge to t1 or t2 defined by pwm6_rise_sel.
Page 176 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description pwm7_df 7000_2C6Ch [15:8] PWM7 falling edge delay (dead) time from t1 or t2. Mapping of the falling edge to t1 or t2 defined by pwm7_fall_sel.
Page 177 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description pwm9_dr 7000_2C74h [7:0] PWM9 rising edge delay (dead) time from t1 or t2. Mapping of the rising edge to t1 or t2 defined by pwm9_rise_sel.
Page 178 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description pwm10_df 7000_2C78h [15:8] PWM10 falling edge delay (dead) time from t1 or t2. Mapping of the falling edge to t1 or t2 defined by pwm10_fall_sel.
Page 179 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description pwm12_dr 7000_2C80h [7:0] PWM12 rising edge delay (dead) time from t1 or t2. Mapping of the rising edge to t1 or t2 defined by pwm12_rise_sel.
Page 180 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description ramp0_t2_irq_sel 7000_2C8Ch [5:3] PWM ramp0 t2 IRQ source select. 0: t2 IRQ disabled 1: t2 2: t2 even 3: t2 odd 4 to 7: V falling edge RECT...
Page 181 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description 0: Every T switch 1: Every 2 T switch 2: Every 4 T switch 3: Every 8 T switch 4: Every 16 T switch 5: Every 32 T switch...
Page 182 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description pid_verr_slope_exit_ 7000_1C0Ch [13:7] FTR mode error voltage (V ) slope thrs (pid0) exit threshold where the error 7000_200Ch voltage is defined as (pid1) = (target voltage - sense voltage) When (V...
Page 183 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description undershoot. LSB = 1.25 mV/clk, range = 0.0 to 158.75 mV/clk at VSEN pid_ftr_lpf 7000_1C0Ch [30:28] FTR mode LPF BW applied to the (pid0) prior to comparing against the 7000_200Ch...
Page 184 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description 7000_2010h (pid1) = (target voltage - sense voltage) When (V is less than pid_ovs_entry_thrs) AND (V slope is less than pid_ovs_slope_entry_thrs) the control loop enters OVS mode.
Page 185 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description voltage. LSB = 1.25 mV, range = 0.0 to 18.75 mV at VSEN pid_burst_mode_ith 7000_1C14h [9:4] BM entry current threshold. When (pid0) BM is enabled 7000_2014h...
Page 186: Pwm Pmbus Commands
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description common sync_in_range 7000_30A8h [24] Digital sync “in range” status. The sync input can make initial lock to an incoming signal within +/-6.25 percent of the internal clock frequency.
Page 187 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Command name Access Length Address Bits Description PAGE1.INTERLEAVE[7:4] = 2d (two phases in group) PAGE1.INTERLEAVE[3:0] = 1d (position 1 in group 180 degrees) The FW_CONFIG_PWM command FW_CONFIG_PWM Block [31:0] maps PWM outputs as either primary- side or secondary-side FETs assigned...
Page 188 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Command name Access Length Address Bits Description pwm5_df [79:72]: PWM5 rising edge dead time, pwm5_dr [87:80]: PWM6 falling edge dead time, pwm6_df [95:88]: PWM6 rising edge dead time, pwm6_dr [103:96]: PWM7 falling edge dead time, pwm7_df [111:104]: PWM7 rising edge dead...
Page 189 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Command name Access Length Address Bits Description pwm4_df [63:56]: PWM4 rising edge dead time, pwm4_dr [71:64]: PWM5 falling edge dead time, pwm5_df [79:72]: PWM5 rising edge dead time, pwm5_dr [87:80]: PWM6 falling edge dead time, pwm6_df...
Page 190 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Digital pulse width modulator Command name Access Length Address Bits Description ramp1 even in the case that both PWM ramps are used by Loop 0. User manual V 1.2 2024-02-22...
Page 191: Telemetry
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Telemetry This chapter discusses the telemetry module and its submodules and their operation. The relevant register settings and PMBus commands are also provided. The main function of the telemetry module is to provide source selection and low-pass filtering of HW-sensed parameters (V , temperature, duty cycle and frequency) for use by the FW in generating the equivalent PMBus READ commands (READ_VOUT, READ_IOUT, etc.).
Page 192: Input Voltage
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry tlm_kfp_vout kfp kfp_real F3db (kHz) tlm_kfp_vout kfp kfp_real F3db (kHz) 0.0015 11.67 0.0234 190.99 0.0017 13.62 0.0273 223.71 The LPF output is subsampled to the F rate and it is available as read-only register tlmX_vout_fsw. This switch version of V is in VSADC format with binary point at 1.25 mV and is used by the V...
Page 193 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry tlm_vin_src_sel Source Comments VRSEN Non-pulsed/primary V sense via VSADC BVRSEN Non-pulsed/primary V sense via VSADC When Loop 0 V is selected as the V source for Loop 1, it is important to note that scaling by register tlm1_vin_convert_factor will apply.
Page 194: Output Current
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry If secondary-side sense is selected as the input source, several registers are provided to fine-tune the V to V RECT computation. There registers are: tlmX_vrect_voffset, which is a constant offset correction term added directly to V voltage coming from •...
Page 195 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Input current (I ) telemetry The I telemetry submodule block diagram is shown in Figure 68. Multiple input sources are capable of providing the input current telemetry. These are: ISEN and BISEN, which can be selected individually to provide I , or input CE (section 8.5) is provided to...
Page 196: Output And Input Power Telemetry
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry one_div_vin[13:0] U0.14 tlmX_vout_div_vin[11:0] U0.12 tlmX_vout_fsw_1v[15:0] U6.10, 1v tlmX_duty_fsw[15:4] tlmX_iin_est[12:0] U0.12 U6.7 tlmX_transformer_scale_loop[11:0] tlmX_iin_est_alpha[5:0] tlmX_iout_fsw[12:0] RW parameters U0.12 U0.6 S9.4 RO parameters Figure 69 Input current estimation block diagram Output and input power telemetry Output and input power telemetry are computed in FW based on the HW-computed voltages and currents.
Page 197 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry tlm_kfp_tsen[5:0] ts_atsen_adc[13:0] tlm_atsen_lpf[9:0] U10.4 U10.0 ts_atsen_adc_update 25 MHz ts_btsen_adc[13:0] tlm_btsen_lpf[9:0] U10.4 U10.0 ts_btsen_adc_update 25 MHz ts_itsen_adc[13:0] tlm_itsen_lpf[9:0] U10.4 U10.0 ts_itsen_adc_update 25 MHz RW parameters RO parameters Figure 70 Temperature telemetry block diagram Table 55 Temperature and general-purpose ADC LPF BW programming, where LSB = 0.0001221 and = 0.125 MHz...
Page 198: Duty-Cycle Telemetry
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry The conversion from ADC codes to temperature is performed in FW using a user-defined LUT. A default LUT is provided in ROM based on a 47 k NTC sense element. Both NTC and PTC LUTs are allowed. The following PMBus commands are supported for both loops with mapping from ATSEN, BTSEN and ITSEN: READ_TEMPERATURE_1 •...
Page 199: General-Purpose Adc Telemetry
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Figure 72 Switching frequency telemetry block diagram 8.10 General-purpose ADC telemetry The general-purpose TSADC outputs are low-pass filtered as illustrated in the block diagram in Figure 73. The IMON and XADDR BWs are programmed via registers tlm_kfp_imon and tlm_kfp_xaddr according to the following definition: tlm_kfp_xaddr follows the BW programming given in Table 55...
Page 200 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Table 57 PRISEN ADC LPF BW programming, where LSB = 0.0001221 and F = 0.25 MHz. Applicable sample to PRISEN when ts_muxmode = 6, 7 and IMON when ts_muxmode = 4, 6. F3dB F3dB tlm_kfp_prisen K...
Page 201: Telemetry Interrupts
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry tlm_kfp_prisen tlm_kfp_prisen F3dB F3dB (ts_muxmode = kfp_real (ts_muxmode kfp_real (kHz) (kHz) 4, 5) = 4, 5) 0.0034 0.273 0.1094 9.773 0.0039 0.312 1024 0.1250 11.368 0.0049 0.390 1280 0.1563 14.737 0.0059 0.469 1536 0.1875...
Page 202: Telemetry High/Low Watermark Detect
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry tlm_irq_thr_src_sel Source Loop 0 F switch Loop 1 F switch ATSEN_ADC BTSEN_ADC Internal temperature IMON_ADC PRISEN_ADC XADDR1_ADC XADDR2_ADC 19 - 31 Unused The following registers can be used for IRQ definition: tlm_irq_gereric_thr_Y defines the threshold against which the input source is compared;...
Page 203: Telemetry Registers
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry tlm_hilo_mark_sel Source Register tlmX_hilo_mark_Y_clr is used to clear current high and low stored values. Upon a clear: The high register is reset to its minimum setting based on the format of the selected input; 0000h for •...
Page 204 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description 7000_3800h to 9. Set to 63 to bypass filter. kfp_exp = tlm_kfp_iin[5:2]" (Loop 1) kfp_man = 4 + tlm_kfp_iin[1:0] kfp = kfp_man * 2^kfp_exp * 2^-13 F3db(kHz) = [kfp / (1 - kfp)] * (kHz) / 2*pi switch...
Page 205 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description LINEAR11 format for correct scaling of V telemetry. telem tlm_kfp_vin 7000_3404h [5:0] Input voltage telemetry LPF (Loop 0) coefficient index. Note that exp. 7000_3804h settings greater than 9 are clamped (Loop 1) to 9.
Page 206 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description should enter the diode drop as seen at the V prior to the sense RECT resistor divider. 0: 480 mV 1: 640 mV 2: 800 mV 3: 960 mV 4: 0 mV 5: 1280 mV...
Page 207 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description telem tlm_iin_est 7000_3414h [12:0] Unfiltered result of estimated input (Loop 0) current computation based on I 7000_3814h and duty-cycle values. (Loop 1) LSB = 7.8125 mA, range = 0.0 to 63.9922 A telem tlm_vout_div_vin...
Page 208 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description quot1(U7.8) = 2^22 / prod1(U0.14), clamp to 2^15-1 tlm_vin_convert_factor(U-2.24) = quot1(U7.8) * 82(U-9.16) LSB = 2^-24, range = 0.0 to 0.2500 telem tlm_vin_lpf 7000_342Ch [10:0] Low-pass filtered input voltage (Loop 0)
Page 209 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description referenced voltage. PMBus command computed by FW as follows: READ_VOUT(U16-X.X) = (tlm_vout_fsw(U12.3) / 800) * (2^16 / VOUT_SCALE_LOOP(U0.16)) * 2^(X-3) where X = negative of VOUT_MODE exponent LSB = 0.15625 mV, range = 0.0 to 5.11875 V...
Page 210 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description (exp + 12) LSB = 2^-12, range = 0.0 to 0.99976 telem tlm_vout_scale_loop 7000_3444h [15:0] sense resistor scale value. (Loop 0) Computed by FW from PMBus as 7000_3844h follows: (Loop 1)
Page 211 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description : Signed, LSB = 62.5 mA, range = -256 to +255.9375 A telem tlm_out_hi_B 7000_3458h [12:0] High watermark detector B output. (Loop 0) Format depends on input selected 7000_3858h by tlm_hilo_mark_B_sel.
Page 212 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description clamped to 9. Set to 63 to bypass filter. kfp_exp = tlm_kfp_imon[5:2] kfp_man = 4 + tlm_kfp_imon[1:0] kfp = kfp_man * 2^kfp_exp * 2^-13 F3db(kHz) = [kfp / (1 - kfp)] * 125 kHz / 2*pi tlmcom...
Page 213 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description 5: Loop 1 I 6: Loop 0 V 7: Loop 1 V 8: Loop 0 duty 9: Loop 1 duty 10: Loop 0 F switch 11: Loop 1 F switch...
Page 214 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description 8: Loop 0 duty 9: Loop 1 duty 10: Loop 0 F switch 11: Loop 1 F switch 12: ATSEN 13: BTSEN 14: Internal temp. 15: IMON 16: PRISEN 17: XADDR1...
Page 215 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description 11: Loop 1 F switch 12: ATSEN 13: BTSEN 14: Internal temp. 15: IMON 16: PRISEN 17: XADDR1 18: XADDR2 19 to31: Unused tlmcom tlm_irq_gereric_thr_3 7000_5010h [15:0]...
Page 216 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description 14: Internal temp. 15: IMON 16: PRISEN 17: XADDR1 18: XADDR2 19 to 31: Unused tlmcom tlm_irq_gereric_thr_4 7000_5014h [15:0] Telemetry IRQ 4 threshold. Compared against signal selected by tlm_irq_thr_src_sel_4.
Page 217 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description 17: XADDR1 18: XADDR2 19 to 31: Unused tlmcom tlm_irq_gereric_thr_5 7000_5018h [15:0] Telemetry IRQ 5 threshold. Compared against signal selected by tlm_irq_thr_src_sel_5. Format based on selected source. : S9.4, LSB = 62.5 mA, range = -256 to +255.9375 A : U12.3, LSB = 156.25 µV, range =...
Page 218 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description tlmcom tlm_irq_gereric_thr_6 7000_501Ch [15:0] Telemetry IRQ 6 threshold. Compared against signal selected by tlm_irq_thr_src_sel_6. Format based on selected source. : S9.4, LSB = 62.5 mA, range = -256 to +255.9375 A : U12.3, LSB = 156.25 µV, range = 0.0 to 5.11984375 V...
Page 219 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description based on selected source. : S9.4, LSB = 62.5 mA, range = -256 to +255.9375 A : U12.3, LSB = 156.25 µV, range = 0.0 to 5.11984375 V : U6.7, LSB = 7.8125 mA, range = 0.0 to 63.9922 A...
Page 220 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description : U12.3, LSB = 156.25 µV, range = 0.0 to 5.11984375 V : U6.7, LSB = 7.8125 mA, range = 0.0 to 63.9922 A : U7.4, LSB = 62.5 mV, range = 0.0 to 127.9375 V Duty: U0.16, LSB = 2^-16, range =...
Page 221 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description 0.0 to 63.9922 A : U7.4, LSB = 62.5 mV, range = 0.0 to 127.9375 V Duty: U0.16, LSB = 2^-16, range = 0.0 to 0.99998 : U11.0, LSB = 1 kHz, range = 0 switch to 2047 kHz...
Page 222 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description Duty: U0.16, LSB = 2^-16, range = 0.0 to 0.99998 : U11.0, LSB = 1 kHz, range = 0 switch to 2047 kHz ATSEN, BTSEN, ITSEN: U10.0, LSB = 1 ADC code, range = 0 to 1023 ADC codes IMON, PRISEN, XADDR1, XADDR2:...
Page 223 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description to 2047 kHz ATSEN, BTSEN, ITSEN: U10.0, LSB = 1 ADC code, range = 0 to 1023 ADC codes IMON, PRISEN, XADDR1, XADDR2: U10.4, LSB = 0.0625 ADC code, range = 0.0 to 1023.9375 ADC codes tlmcom tlm_irq_thr_src_sel_11...
Page 224 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description codes IMON, PRISEN, XADDR1, XADDR2: U10.4, LSB = 0.0625 ADC code, range = 0.0 to 1023.9375 ADC codes tlmcom tlm_irq_thr_src_sel_12 7000_5034h [20:16] Telemetry IRQ 12 source select. Selects signal to compare against tlm_irq_gereric_thr_12 for IRQ generation.
Page 225 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description U10.4, LSB = 0.0625 ADC code, range = 0.0 to 1023.9375 ADC codes tlmcom tlm_irq_thr_src_sel_13 7000_5038h [20:16] Telemetry IRQ 13 source select. Selects signal to compare against tlm_irq_gereric_thr_13 for IRQ generation.
Page 226 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description tlmcom tlm_irq_thr_src_sel_14 7000_503Ch [20:16] Telemetry IRQ 14 source select. Selects signal to compare against tlm_irq_gereric_thr_14 for IRQ generation. 0: Loop 0 I 1: Loop 1 I 2: Loop 0 V 3: Loop 1 V 4: Loop 0 I...
Page 227 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description generation. 0: Loop 0 I 1: Loop 1 I 2: Loop 0 V 3: Loop 1 V 4: Loop 0 I 5: Loop 1 I 6: Loop 0 V 7: Loop 1 V 8: Loop 0 duty...
Page 228 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description tlmcom tlm_itsen_lpf 7000_5054h [9:0] Low-pass filtered ITSEN telemetry output. Note that the format of this register is ADC codes. The ADC code to temperature conversion is implemented in FW.
Page 229: Pmbus
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description tlmcom tlm_xaddr1_adc_lpf 7000_5074h [13:0] Low-pass filtered XADDR1 telemetry output when used as a general-purpose ADC. LSB = 0.0625 ADC code, range = 0 to 1023.9375 ADC codes tlmcom tlm_xaddr2_adc_lpf...
Page 230 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Command name Access Length Address Bits Description .Read_Temperature_1_Read_Tempera ture_2_source_select. READ_TEMPERATURE_2 Word [15:0] Returns the temperature at sensor 2 in degrees Celsius in the LINEAR11 format. The temperature source for sensor 2 is defined by MFR_SELECT_TEMPERATURE_SENSOR .Read_Temperature_1_Read_Tempera ture_2_source_select.
Page 231 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Command name Access Length Address Bits Description Note: When tlm1_vin_src_sel = 2 (Loop 0 V ), set PAGE 1 MFR_VRECT_SCALE = PAGE 0 VOUT_SCALE_LOOP converted to LINEAR11 format for correct scaling of telemetry.
Page 232 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Telemetry Command name Access Length Address Bits Description MFR_SELECT_TEMPERATU Byte [2:0] Read_Temperature_1_Read_Temper RE_SENSOR ature_2_source_select: Defines the temp. sense input source selection for READ_TEMPERATURE_1 and READ_TEMPERATURE_2 commands. 0: READ_TEMPERATURE_1 = ATSEN, READ_TEMPERATURE_2 = BTSEN 1: READ_TEMPERATURE_1 = ATSEN, READ_TEMPERATURE_2 = ITSEN 2: READ_TEMPERATURE_1 = BTSEN,...
Page 233: Fault Handler
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Fault handler This chapter discusses the fault handler module and its main functionalities and relevant registers programming. All the PMBus commands mentioned within the chapter are described in section 9.8. The fault module is responsible for detecting faults and reporting them to the FW as well as initiating fault- based shutdown.
Page 234: Output Voltage Faults
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler vspX_vout_fs vout_ov_fault faultX_vout_ov_fault_thresh faultX_vout_ov_fault_cnt vout_ov_warn faultX_vout_ov_warn_thresh faultX_vout_ov_warn_cnt faults vout_uv_fault faultX_vout_uv_fault_thresh faultX_vout_uv_fault_cnt vout_uv_warn faultX_vout_uv_warn_thresh faultX_reg_loop[31:0] faultX_vout_uv_warn_cnt fault_loop_bus[31:0] Fault latching faultX_vout_fault_hyst Note: Bus connections faultX_status_loop[31:0] tlmX_vin_lpf not shown tied to logic 0. vin_ov_fault faultX_vin_ov_fault_thresh faultX_vin_ov_fault_cnt...
Page 235 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler referenced to VSEN and is computed by FW based on PMBus commands VOUT_OV_FAULT_LIMIT and VOUT_SCALE_LOOP. Output overvoltage warning The output overvoltage warning is asserted when the VSP output in register vspX_vout_fs exceeds the warning threshold (fault_vout_ov_warn_thresh) for the number of samples (fault_vout_ov_warn_cnt) without falling below the threshold defined in Equation (9.2).
Page 236: Input Voltage Faults
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler The time unit for the delay portion of the output voltage RESPONSE commands is defined by PMBus command FW_CONFIG_FAULTS bits [7:6]. All of these PMBus commands are described in section 9.8.
Page 237: Output Current Faults
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Input voltage fault-related PMBus commands The input voltage faults and warnings are reported on the following PMBus commands: STATUS_BYTE • STATUS_WORD • STATUS_INPUT • It should be noted that VIN_OV_FAULT and VIN_UV_FAULT remain asserted in the PMBus STATUS command until VIN_OV_WARNING and VIN_UV_WARNING are deasserted.
Page 238 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler (9.11) ��ℎ��ℎ�� = ��_��_��_��_��_��ℎ��ℎ − ��_��_��_��_ℎ�� The samples for the fast overcurrent fault do not need to be consecutive, but a single sample below the value in Equation (9.11) will reset the count and deassert the fault. The register fault_mfr_iout_oc_fast_thresh is computed by FW based on PMBus command MFR_IOUT_OC_FAST_FAULT_LIMIT.
Page 239: Input Current Faults
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler 9.1.4 Input current faults The input current fault submodule is responsible for detection of input overcurrent fault and warning. Input overcurrent fault The input overcurrent fault is asserted when the filtered telemetry output in register tlmX_iin_lpf exceeds the fault threshold (fault_iin_oc_fault_thresh) for the number of samples (fault_iin_oc_fault_cnt) without falling below the threshold defined in Equation (9.13).
Page 240: Temperature Faults
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler All of these PMBus commands and their programming are described in section 9.8. 9.1.6 Temperature faults The temperature fault submodule is responsible for the detection of: Overtemperature fault and warning •...
Page 241: Current Sharing Fault
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler o Deasserted when temp. is less than (fault_ut_fault_thresh - fault_temp_fault_hyst) Register fault_temp_fault_hyst should be set to a negative value for PTC sensors and a positive value for NTC sensors. The above-mentioned registers are computed by FW as follows: fault_ot_fault_thresh based on OT_FAULT_LIMIT and the FW-implemented temperature LUT •...
Page 242: Loop Fault Latching
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler TON_MAX_FAULT_LIMIT sets an upper limit on how long the XDPP1100 attempts to power up the output • without reaching the output undervoltage limit. If this limit is exceeded the response defined by PMBus command TON_MAX_FAULT_RESPONSE is taken.
Page 243: Common Faults
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Fault Fault VOUT_OV_WARN [14] IIN_OC_FAULT VOUT_UV_FAULT [15] IIN_OC_WARN VOUT_UV_WARN [16] OT_FAULT VIN_OV_FAULT [17] OT_WARN VIN_OV_WARN [18] UT_FAULT VIN_UV_FAULT [19] UT_WARN VIN_UV_WARN [20] POWER_LIMIT_MODE IOUT_OC_FAULT [21] ISHARE_FAULT [10] IOUT_OC_LV_FAULT [22] VOUT_MAX_MIN_WARN [11] IOUT_OC_WARN [23]...
Page 244: Peak Current Limit Fault
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler 9.2.2 Peak current limit fault The XDPP1100 supports a PCL fault as described in section 3.3.2. The PCL fault is bitwise ORed with all common faults and reported on STATUS_MFR_SPECIFIC bit [4]. The individual fault can be determined by reading the register fault_status_com.
Page 245: Common Fault Latching
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler 9.2.6 Common fault latching The common fault latching submodule is responsible for registering and holding the occurrence of common faults for use by the shutdown submodule and reporting to the FW. As was shown in Figure 79, the fault inputs to the common fault submodule are gathered together to form the fault_com_bus signal, which is the data...
Page 246: Fault Interrupts (Irq)
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Fault Fault BISEN SCP fault Fault interrupts (IRQ) The fault interrupt generation is shown in Figure 81. From the figure it can be observed that three fault status registers: fault0_status_loop •...
Page 247: Fault Shutdown
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler { fault_status_com[31:0], fault1_status_loop[31:0], fault0_status_loop[31:0] } fault_encode[7:0] 00000000000000000000000000000000_00000000000000000000000000000000_00000000000000000000000000000000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX_XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX_XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX1 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX_XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX_XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX10 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX_XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX_XXXXXXXXXXXXXXXXXXXXXXXXXXXXX100 … XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX_XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX_XX100000000000000000000000000000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX_XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX_X1000000000000000000000000000000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX_XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX_10000000000000000000000000000000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX_XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX1_00000000000000000000000000000000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX_XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX10_00000000000000000000000000000000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX_XXXXXXXXXXXXXXXXXXXXXXXXXXXXX100_00000000000000000000000000000000 … XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX_XX100000000000000000000000000000_00000000000000000000000000000000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX_X1000000000000000000000000000000_00000000000000000000000000000000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX_10000000000000000000000000000000_00000000000000000000000000000000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX1_00000000000000000000000000000000_00000000000000000000000000000000 224d XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX10_00000000000000000000000000000000_00000000000000000000000000000000 225d XXXXXXXXXXXXXXXXXXXXXXXXXXXXX100_00000000000000000000000000000000_00000000000000000000000000000000 226d … XX100000000000000000000000000000_00000000000000000000000000000000_00000000000000000000000000000000 253d X1000000000000000000000000000000_00000000000000000000000000000000_00000000000000000000000000000000 254d 10000000000000000000000000000000_00000000000000000000000000000000_00000000000000000000000000000000...
Page 248: Fault Pin Mapping
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler PWM Ramp PWM FET SR FET Shutdown Fault Non-t2 shutdown timing t2 shutdown timing Figure 84 Immediate (non-t2) vs. t2 aligned shutdown timing The immediate shutdown is enabled through the following registers: fault0_shut_mask_loop for the Loop 0 faults •...
Page 249: Fault Registers
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler By default GPIO0[2] is assigned to FAULT1 and it outputs Loop 0 faults as selected through PMBus page 0 FW_CONFIG_FAULTS[71:8]. Correspondingly, the GPIO1[2] is assigned to FAULT2 and it outputs Loop 1 faults as selected through PMBus Page 1 FW_CONFIG_FAULTS[71:8].
Page 250 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description 2: 4 samples 3: 8 samples fault fault_iout_oc_fault_cnt 7000_3C00h [12:8] Output overcurrent fault count. (Loop 0) Defines the number of consecutive 7000_4000h switching cycles (T ) the low- switch (Loop 1)
Page 251 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description 1: 2 T switch 2: 4 T switch 3: 8 T switch fault fault_vin_uv_fault_cnt 7000_3C04h [5:4] Input undervoltage fault count. (Loop 0) Defines the number of consecutive 7000_4004h switching cycles (T ) the input...
Page 252 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description fault_vin_fault_hyst) will reset the count. For the typical case this parameter should be set to a positive voltage. This hysteresis parameter applies to all V faults and warnings as shown below.
Page 253 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description below (VOUT_OV_FAULT_LIMIT- fault_vout_fault_hyst) will reset the count. For the typical case this parameter should be set to a positive voltage. This hysteresis parameter applies to all V faults and warnings as shown below.
Page 254 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description should be set to a positive current. This hysteresis parameter applies to all I faults and warnings as shown below. IIN_OC_FAULT: Asserted when I is greater than IIN_OC_FAULT_LIMIT Deasserted when I...
Page 255 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description Asserted when I is greater than MFR_IOUT_OC_FAST_FAULT_LIMIT Deasserted when I is less than or equal to (MFR_IOUT_OC_FAST_FAULT_LIMI T-fault_iout_oc_fault_hyst) LSB = 0.25 A, range = -8.0 to +7.75 A fault_iout_uc_fault_hyst 7000_3C08h [21:16] Output undercurrent (IOUT_UC)
Page 256 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description temperature faults and warnings, as shown below. PTC OT_FAULT: Asserted when temp. is greater than fault_ot_fault_thresh Deasserted when temp. is less than (fault_ot_fault_thresh + fault_temp_fault_hyst) PTC OT_WARN: Asserted when temp.
Page 257 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description LSB = 1 TSADC code, range = -16 to +15 TSADC codes fault_shut_mask_loop 7000_3C0Ch [31:0] Shutdown mask for Loop faults. fault (Loop 0) Individual faults are enabled for 7000_400Ch shutdown when their...
Page 258 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description fault_t2_shut_mask_loop are set to 1, the immediate shutdown behavior of fault_shut_mask_loop is implemented. This register should not be written directly but rather through PMBus command FW_CONFIG_FAULTS bits [199:168], which have a 1 to 1 mapping with bits [31:0] of this...
Page 259 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description 5: VIN_OV_FAULT 6: VIN_OV_WARN 7: VIN_UV_FAULT 8: VIN_UV_WARN 9: IOUT_OC_FAULT 10: IOUT_OC_LV_FAULT 11: IOUT_OC_WARN 12: IOUT_UC_FAULT 13: MFR_IOUT_OC_FAST 14: IIN_OC_FAULT 15: IIN_OC_WARN 16: OT_FAULT 17: OT_WARN 18: UT_FAULT 19: UT_WARN...
Page 260 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description fault fault_vout_uv_fault_thr 7000_3C20h [9:0] Output undervoltage fault (Loop 0) threshold. Note that this threshold 7000_4020h is defined with respect to the (Loop 1) voltage at the VSEN pin, after the sense resistor divider.
Page 261 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description 7000_4030h command as follows: fault_vin_uvp_fault_thresh = (Loop 1) Int(VIN_UV_FAULT_LIMIT[10:0] * 2^(VIN_UV_FAULT_LIMIT[15:11] + LSB = 125 mV, range = 0.0 to 127.875 V fault fault_vin_uv_warn_thre 7000_3C34h [9:0]...
Page 262 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description fault fault_iout_uc_fault_thre 7000_3C44h [7:0] Output undercurrent fault (Loop 0) threshold. Fault asserted when the 7000_4044h cycle-averaged output current is (Loop 1) below this threshold. Computed by FW from PMBus command as follows: fault_iout_uc_fault_thresh =...
Page 263 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description to temperature LUT. LSB = 1 TSADC code, range = 0.0 to 1023 AD codes fault fault_ut_fault_thresh 7000_3C5Ch [9:0] Undertemperature fault threshold (Loop 0) in TSADC codes.
Page 264 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description 1: VOUT_OV_FAULT 2: VOUT_OV_WARN 3: VOUT_UV_FAULT 4: VOUT_UV_WARN 5: VIN_OV_FAULT 6: VIN_OV_WARN 7: VIN_UV_FAULT 8: VIN_UV_WARN 9: IOUT_OC_FAULT 10: IOUT_OC_LV_FAULT 11: IOUT_OC_WARN 12: IOUT_UC_FAULT 13: MFR_IOUT_OC_FAST 14: IIN_OC_FAULT 15: IIN_OC_WARN...
Page 265 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description 20: POWER_LIMIT_MODE 21: ISHARE_FAULT 22: VOUT_MAX_MIN_WARN 23: SYNC_FAULT 24: VDD_UVLO (XDPP1100A only) 25 to 31: Unused fault fault_clear_loop 7000_3C74h [31:0] Fault force clear register. When the (Loop 0) bit corresponding to a 7000_4074h...
Page 266 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description 5: VIN_OV_FAULT 6: VIN_OV_WARN 7: VIN_UV_FAULT 8: VIN_UV_WARN 9: IOUT_OC_FAULT 10: IOUT_OC_LV_FAULT 11: IOUT_OC_WARN 12: IOUT_UC_FAULT 13: MFR_IOUT_OC_FAST 14: IIN_OC_FAULT 15: IIN_OC_WARN 16: OT_FAULT 17: OT_WARN 18: UT_FAULT 19: UT_WARN...
Page 267 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description 24: VDD_UVLO (XDPP1100A only) 25 to 31: Unused fault fault_iout_cc_mode 7000_3C80h Status flag indicating I constant (Loop 0) current mode operation. 7000_4080h 0: Normal operation (Loop 1) 1: Constant current mode fault...
Page 268 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description 15: VRSEN open fault 16: Unused 17: BVREF_BVRREF open fault 18: BVSEN_BVRSEN open fault 19 to 31: Unused faultcom fault_block_on_shut 7000_5404h Defines whether faults continued to be reported after an initial shutdown fault had occurred and triggered shutdown.
Page 269 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description faultcom fault_shut_clr_all 7000_540Ch Clears shutdown faults in fault_reg_com and both fault_reg_loop registers when high. This field should not be written until after FW has completed shutdown-related cleanup (e.g., target returned to 0, control...
Page 270 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description 18: BVSEN_BVRSEN open fault 19 to 31: Unused faultcom fault_clear_com 7000_541Ch [31:0] Fault force clear register. When the bit corresponding to a fault or warning is set to 1, that fault or warning is cleared in the fault_status_loop and...
Page 271 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description 13: Unused 14: VRREF open fault 15: VRSEN open fault 16: Unused 17: BVREF_BVRREF open fault 18: BVSEN_BVRSEN open fault 19 to 31: Unused faultcom fault_encode 7000_5424h...
Page 272: Fault Pmbus Commands
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Fault PMBus commands Table 67 Fault-related PMBus command descriptions Command name Access Length Address Bits Description VOUT_SCALE_LOOP Word [15:0] Scales VOUT_COMMAND and other V related commands for the external resistor divider between V and VSEN.
Page 273 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Command name Access Length Address Bits Description VOUT_UV_FAULT_LIMIT Word [15:0] Sets the value of the output voltage that causes an output undervoltage fault. The data bytes are formatted according to the setting of the VOUT_MODE command.
Page 274 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Command name Access Length Address Bits Description specified by delay bits [2:0] then if still operating in current limiting, shut down and respond according to retry bits [5:3] 3: Shut down and respond according to retry bits [5:3] [5:3]: Retry setting 0: Remain disabled until fault cleared...
Page 275 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Command name Access Length Address Bits Description 3: Shut down SR until fault condition removed [5:3]: Retry setting 0: Remain disabled until fault cleared 1 to 6: Attempt to restart [5:3] times with delay [2:0] between restarts 7: Attempt to restart continuously until commanded OFF...
Page 276 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Command name Access Length Address Bits Description UT_FAULT_RESPONSE Byte [7:0] Instructs the device on what action to take in response to an overtemperature fault. [7:6]: Response 0: Continue operation without interruption 1: Continue operation for time specified by delay bits [2:0] then if fault condition...
Page 277 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Command name Access Length Address Bits Description between restart attempts, unit defined by FW_CONFIG_FAULTS command VIN_OV_WARN_LIMIT Word [15:0] Sets the value of the input voltage that causes an input overvoltage warning. The format is LINEAR11.
Page 278 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Command name Access Length Address Bits Description 0: Continue operation without interruption 1: Continue operation for time specified by delay bits [2:0] then if fault condition still present, shut down and respond according to retry bits [5:3] 2: Shut down and respond according to retry bits [5:3]...
Page 279 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Command name Access Length Address Bits Description between restart attempts, unit defined by FW_CONFIG_FAULTS command TOFF_MAX_WARN_LIMIT Word [15:0] Sets an upper limit, in ms, on how long the unit can attempt to power down the output without reaching 12.5 percent of the output voltage programmed at the time the unit is turned off.
Page 280 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Command name Access Length Address Bits Description [14] I : An output current or output power fault or warning has occurred. [13] INPUT: An input voltage, input current or input power fault of warning has occurred.
Page 281 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Command name Access Length Address Bits Description STATUS_TEMPERATURE Byte [7:0] Returns one data byte with contents as follows: [7]: OT_FAULT [6]: OT_WARNING [5]: UT_WARNING [4]: UT_FAULT [3]: Reserved [2]: Reserved [1]: Reserved [0]: Reserved STATUS_CML...
Page 282 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Command name Access Length Address Bits Description [3:2] Iout_Delay_Unit: Time unit for retry responses. 0: 1 ms 1: 4 ms 2: 16 ms 3: 256 ms [5:4] Vin_Delay_Unit: Time unit for retry responses.
Page 283 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Command name Access Length Address Bits Description 0: Reserved 1: Common fault 2: TON_MAX_FAULT 3: TOFF_MAX_WARN 4: PIN_OP_WARN 5: POUT_OP_WARN 6: VIN_INSUFFICIENT 7 to 31: Unused [103:72] Fault_enable_mask_loop_hw[31:0]: Masking for loop hardware faults. Set a bit to 1 to disable PMBus reporting on the corresponding fault.
Page 284 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Command name Access Length Address Bits Description [167:136] Fault_enable_mask_loop_common[31 :0]: Masking for common faults. Set a bit to 1 to disable PMBus reporting on the corresponding fault. 0: Unused 1: Unused 2: IS1 (ISEN) tracking fault 3: IS2 (BISEN) tracking fault 4: Fbal1 fault...
Page 285 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fault handler Command name Access Length Address Bits Description 15: IIN_OC_WARN 16: OT_FAULT 17: OT_WARN 18: UT_FAULT 19: UT_WARN 20: POWER_LIMIT_MODE 21: ISHARE_FAULT 22: VOUT_MAX_MIN_WARN 23: SYNC_FAULT 24: VDD_UVLO (XDPP1100A only) 25 to 31: Unused MFR_IOUT_OC_FAST_FAU Byte [7:0]...
Page 286: Current Sharing (Ishare )
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sharing (ISHARE) Current sharing (I SHARE This chapter discusses the current sharing feature in more detail as well as the relevant register settings related to current sensing. In order to increase power delivery to the load, multiple power supplies may be connected in parallel to drive a common output voltage.
Page 287 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sharing (ISHARE) The IMON pin is connected to: Current DAC output; in the current sharing mode it outputs a current proportional to the load current share • of the individual supply TSADC input;...
Page 288: Current Sharing Pi Filter
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sharing (ISHARE) supply current is given in amps. As an example, if an individual supply can handle 50 A, then the ishr_scale value is as given in Equation (10.4). (10.3) ��ℎ��_�� = �� (16 ∗ ��_��_��...
Page 289: Current Sharing Fw Override
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sharing (ISHARE) �� (10.6) �� | �� (��) | = √ �� 2��∙�� ∙�� (��ℎ��_��[5:3]−10) (10.7) �� = ( 8 + ��ℎ��_��[2: 0] ) ∙ 2 �� (��ℎ��_��[5:3]−12) (10.8) ��...
Page 290: Current Sharing Pin, Dac And Adc Configuration
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sharing (ISHARE) Similarly, the IMON current DAC inputs may be overridden through the registers: idac_fw_en • idac_fw_frc • These overrides could be used as part of a user-written FW patch to implement a different current sharing scheme.
Page 291: Current Sharing Registers
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sharing (ISHARE) For the second R connection with module sequencing, a FW patch is available. It drives the R negative ishare ishare connection to ground through a PWM output allowing the negative connection to float when the supply is not enabled.
Page 292 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sharing (ISHARE) Peripheral Field name Access Address Bits Description current sharing) 1: CMOS output common ishr_scale 7000_3020h [4:0] Used for current sharing, this register defines a pre-scale gain applied to the internal current telemetry before sending to the current output DAC on the IMON pin.
Page 293 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sharing (ISHARE) Peripheral Field name Access Address Bits Description 0: Use HW-computed current share adjust 1: Use ishr_fw_adj common idac_fw_frc 7000_3088h [9:0] When idac_fw_en is high, this register overrides the HW current DAC output with a FW-controlled setting.
Page 294 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sharing (ISHARE) Peripheral Field name Access Address Bits Description current sharing. The current DAC should be disabled otherwise. 0: Disabled 1: Enabled tsen ts_muxctrl2 7000_4C00h [19:17] TSADC MUX2 input source select. The output of MUX2 is connected to the TSADC input.
Page 295: Current Sharing Pmbus Commands
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current sharing (ISHARE) 10.7 Current sharing PMBus commands The relevant current sharing-related PMBus commands and their descriptions are provided in Table Table 71 Current sharing-related PMBus commands Command name Access Length Address Bits Description MFR_ISHARE_THRESHOLD Word...
Page 296: Current Balance
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current balance (IBAL) Current balance (I This chapter describes the current balance functionality and the relevant registers and their programming. Within interleaved topologies, different inductor currents may become imbalanced. This could be due to: Component mismatches •...
Page 297: Current Balance Pi Filter
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current balance (IBAL) isp2_iout_cavg BISEN, S8.4 PI Filter S9.4 ibal_duty_adj clk_fsw ibal_fw_adj S-1.9 S-1.9 To PWM Ramp 0 isp1_iout_cavg ISEN, S8.4 kp_ibal ibal_fw_en ki_ibal Figure 90 Simplified current balance block diagram The circuit receives as its input the cycle-averaged current outputs from ISP1 and ISP2, which correspond to the ISEN and BISEN sensed currents.
Page 298: Current Balance Fw Override
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current balance (IBAL) set in register ibal_en_thresh) the accumulated current error is held at its last value rather than being reset to Figure 91 shows an example magnitude response with the following values: kp_ibal = 48 •...
Page 299: Current Balance Registers
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Current balance (IBAL) 11.4 Current balance registers The relevant current balance registers and their descriptions are provided in Table Table 73 Current balance register descriptions Peripheral Field name Access Address Bits Description common kp_ibal 7000_3000h...
Page 300: Flux Balance
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Flux balance (FBAL) Flux balance (F This chapter discusses the flux balance feature as well as the relevant registers and their programming. Flux imbalance is a known problem within isolated FB converters (Figure 92).
Page 301 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Flux balance (FBAL) vbal_mode_sel fbal_max U-2.10 vsum vdt_plus_tdv vrs_vrect_even PI Filter Clamp U12.0 fbal_duty_adj S-1.11 fbal_fw_adj applied to odd vdiff vrs_vrect_odd kp_fbal half cycles only S-1.9 U12.0 ki_fbal fbal_fw_en tsum cnt_vrscomp_even U11.0 fbal_time_only tdiff cnt_vrscomp_odd...
Page 302: Flux Balance Pi Filter
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Flux balance (FBAL) o Loop 0 is operating (start-up or regulation) o interleave operation enabled via PMBus command PAGE0.FW_CONFIG_REGULATION.INTERLEAVE_ENABLE=1 If flux balance is not desired under the above conditions, the adjustment can be disabled by one of the following two methods: Setting fbal_max = 0 blocks the flux balance circuit from adjusting the PWM duty cycle (recommended •...
Page 303: Flux Balance Fw Override
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Flux balance (FBAL) Flux balance PI filter =250 kHz, kp_fbal=48, ki_fbal=32) switch 1000 10000 100000 Frequency (Hz) Figure 94 Example PI magnitude plot for kp_fbal = 48, ki_fbal = 32, F = 250 kHz switch 12.3 Flux balance FW override...
Page 304: Flux Balance Fault Detection
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Flux balance (FBAL) fbal_dcm_thresh, which sets the current threshold at which the flux balance function is disabled due to the • DCM operation; a setting of 63 disables this feature (not recommended) fbal_dcm_dis_cnt, which defines the number of consecutive current samples (at F rate) below •...
Page 305: Flux Balance Registers
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Flux balance (FBAL) In the case of absolute error method, register fbal_delta_abs_en selects where the absolute value of the error is applied, either before or after the LPF. The LPF BW programming is performed via register fbal_lpf_kpshift as shown in Table 75.
Page 306 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Flux balance (FBAL) Peripheral Field name Access Address Bits Description settings greater than 55 are clamped to 55. Note also that flux balancing requires that duty-cycle locking is enabled by rampX_dutyc_lock. ki_exp = ki_fbal[5:3] ki_man = 8 + ki_fbal[2:0] ki = ki_man * 2^ki_exp * 2^-22 common...
Page 307 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Flux balance (FBAL) Peripheral Field name Access Address Bits Description Kp = 2^-Kpshift F3db = [kp/(1-kp)] * F / 2pi switch common fbal_delta_abs_en 7000_3030h [13] In flux balance computation, determines whether absolute value applied to the error before or after the LPF.
Page 308 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Flux balance (FBAL) Peripheral Field name Access Address Bits Description common fbal1_fw_en 7000_307Ch Enables FW-controlled flux/voltage balance loop via fbal1_fw_adj. 0: Use HW-computed flux/voltage balance adjust 1: Use fbal1_fw_adj common fbal2_fw_adj 7000_3080h [7:0] When fbal2_fw_en is high, this register overrides the Loop 0, Phase...
Page 309: Fan Support
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fan support Fan support This chapter describes the fan support functionality and the relevant register settings. Fan support is provided through a combination of HW blocks and a FW patch. The HW blocks drive the fan PWM output and sense the fan speed tachometer input.
Page 310: Duty-Cycle Mode
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fan support Table 80 Fan PWM operating mode selection fan_mode Fan operating mode Duty-cycle mode Current mode 13.1.1 Duty-cycle mode In duty-cycle mode, the user directly programs the PWM duty cycle through one of the following methods: Register fan_duty programs the duty-cycle output in fractional duty cycle •...
Page 311: Fan Speed Input
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fan support Figure 97 Current mode duty cycle with fan_duty_min greater than (fan_imin/fan_imax) 13.2 Fan speed input The XDPP1100 provides HW support for up to two fan speed tachometer inputs, identified as: FAN1_TACH •...
Page 312: Fan Registers
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fan support Fan speed is reported on: Register fan_speed with range 0 to 32K RPM and 8 RPM resolution • PMBus commands: • o READ_FAN_SPEED_1 o READ_FAN_SPEED_2 These PMBus commands are in LINEAR11 format with exponent defined by PMBus command FW_CONFIG_TELEMETRY.READ_FAN_EXP.
Page 313 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fan support Peripheral Field name Access Address Bits Description fan_tach_ppr 7000_4400h [27:26] Tachometer pulses per revolution (Fan 1) (ppr). 7000_4800h 0: 1 ppr (Fan 2) 1: 2 ppr 2: 3 ppr 3: 4 ppr fan_mode 7000_4400h [28]...
Page 314: Fan Pmbus Commands
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fan support 13.4 Fan PMBus commands Table 84 Fan PMBus commands Peripheral Field name Access Address Bits Description FAN_CONFIG_1_2 Byte FAN1 enable. 0: FAN1 disabled 1: FAN1 enabled FAN1 control mode select. Not supported by default FW patch.
Page 315 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Fan support Peripheral Field name Access Address Bits Description register fan_mode. Format is LINEAR11 with exponent of -8 recommended. C000h = 0/256 = 0.0 percent C001h = 1/256 = 0.390625 percent C002h = 2/256 = 0.78125 percent …...
Page 316: Io Muxing
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller IO muxing IO muxing This chapter describes the programming of the multiple digital IO pins and describes the relevant register settings in more detail. The XDPP1100 contains several programmable multipurpose digital IO pins, and depending on the variant the pin numbers are: 21, for the Q040 variant •...
Page 317 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller IO muxing Table 85 Multipurpose IO pin function programming <pin_name>_func[2:0] XDPP1100-Q040 XDPP1100-Q024 Pin name Pin number Pin number FAULT1 FAULT1/GPIO0[2] GPIO0[2] GPIO1[2] External sync FAN2_PWM SDA2 UART_RX FAULT2 FAULT2/GPIO1[2] GPIO0[2] GPIO1[2] External sync FAN2_TACH SCL2 UART_TX...
Page 318: Digital Input Priority
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller IO muxing 14.2 Digital input priority Some functions on the XDPP1100 can be independently mapped to multiple IO pins. For the output functions this is generally not problematic, but for the input functions a priority must be assigned so that only one IO pin provides the actual input.
Page 319: Digital Io Buffer Programming
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller IO muxing Register gpio0_dben enables the deglitcher on GPIO0 and currently only the following settings are supported: 00h: GPIO0[0] deglitch disabled • 01h: GPIO0[0] deglitch enabled • Register gpio1_dben enables the deglitcher on GPIO1 and currently only the following settings are supported: 00h: GPIO1[0] deglitch disabled •...
Page 320 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller IO muxing Peripheral Field name Access Address Bits Description common ben_ppen 7000_3004h Pin BEN output buffer CMOS/open drain select. 0: Open drain output 1: CMOS output common bpwrgd_func 7000_3004h [8:6] Pin BPWRGD function definition. 0: BPWRGD (GPIO1[1]), digital IO 1: GPIO0[1], digital IO 2: GPIO1[1], digital IO...
Page 321 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller IO muxing Peripheral Field name Access Address Bits Description 6: UARTRXD, digital input 7: Not used common fault1_pd 7000_3004h [21] Pin FAULT1 weak pull-down enable. 0: Pull-down disabled 1: Pull-down enabled common fault1_pu_n 7000_3004h [22]...
Page 322 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller IO muxing Peripheral Field name Access Address Bits Description common imon_ppen 7000_3008h Pin IMON output buffer CMOS/open drain select. 0: Open drain output 1: CMOS output common pwrgd_func 7000_3008h [8:6] Pin PWRGD function definition. 0: PWRGD (GPIO0[1]), digital IO 1: GPIO0[1], digital IO 2: GPIO1[1], digital IO...
Page 323 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller IO muxing Peripheral Field name Access Address Bits Description common sync_pd 7000_3008h [21] Pin SYNC weak pull-down enable. 0: Pull-down disabled 1: Pull-down enabled common sync_pu_n 7000_3008h [22] Pin SYNC weak pull-up enable. 0: Pull-up enabled 1: Pull-up disabled common...
Page 324 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller IO muxing Peripheral Field name Access Address Bits Description common pwm2_func 7000_300Ch [8:6] Pin PWM2 function definition. 0: PWM2, digital output 1: GPIO0[7], digital IO 2: GPIO1[7], digital IO 3: SYNC, digital IO 4 to 7: Not used common pwm2_pd...
Page 325 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller IO muxing Peripheral Field name Access Address Bits Description common pwm4_ppen 7000_300Ch [23] Pin PWM4 output buffer CMOS/open drain select. 0: Open drain output 1: CMOS output common pwm5_func 7000_300Ch [26:24] Pin PWM5 function definition. 0: PWM5, digital output 1: GPIO0[3], digital IO 2: GPIO1[3], digital IO...
Page 326 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller IO muxing Peripheral Field name Access Address Bits Description common pwm7_pd 7000_3010h Pin PWM7 weak pull-down enable. 0: Pull-down disabled 1: Pull-down enabled common pwm7_pu_n 7000_3010h [10] Pin PWM7 weak pull-up enable. 0: Pull-up enabled 1: Pull-up disabled common...
Page 327 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller IO muxing Peripheral Field name Access Address Bits Description 1: GPIO0[5], digital IO 2: GPIO1[5], digital IO 3: SYNC, digital IO 4 to 7: Not used common pwm10_pd 7000_3010h [27] Pin PWM10 weak pull-down enable. 0: Pull-down disabled 1: Pull-down enabled common...
Page 328 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller IO muxing Peripheral Field name Access Address Bits Description 0: Open drain output 1: CMOS output common pwm12_func 7000_3014h [8:6] Pin PWM12 function definition. 0: PWM12, digital output 1: GPIO0[7], digital IO 2: GPIO1[7], digital IO 3: SYNC, digital IO 4: FAN1_TACH, digital input...
Page 329 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller IO muxing Peripheral Field name Access Address Bits Description 01h: GPIO0[0] deglitch enabled 02-FFh: Not allowed common gpio1_dben 7000_3028h [31:24] GPIO1 bus input deglitch enable. Due to an erratum, only bit [0] is currently functional.
Page 330: Central Processing Unit Subsystem
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Central processing unit subsystem This chapter describes the CPU subsystem (CPUS) and describes the relevant register settings in more detail. The XDPP1100 CPUS block and bus interconnections diagram is shown in Figure Figure 98 CPUS block diagram...
Page 331: Cpus Bus Matrix
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem AHB to APB Arm® bridges handle the protocol conversion between the two AMBA® layers. The CPUS includes a memory management unit (MMU) that can remap memory addresses based on a configurable scheme, allowing the implementation of a code-patching mechanism.
Page 332: Cpu Interrupt Sources
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem A simplified block diagram of the Cortex®-M0 is shown in Figure Power management interface Wakeup JTAG / interrupt serial-wire Connection controller debug to debugger (WIC) interface Nested Interrupt vector Processor Debug...
Page 333 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Table 89 Cortex®-M0 interrupt table Interrupt Description External index CMSYS interrupt Memory address source number RESET Reset – 0000_0004h 0000_0008h HARDFAULT Hard fault 0000_000Ch SVCALL SV call 0000_002Ch PENDSV Pend SV 0000_0038h...
Page 334: Cortex®-M0 Memory Map
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem INT31 UART 0000_00BCh Every interrupt INT31-INT0 can be programmed to be used as NMI, by configuring the NMI source-select register NMI_SRC_EN in SCU. 15.2.2 Cortex®-M0 memory map The memory map accessible by Cortex®-M0 is described in Table Table 90 Cortex®-M0 memory map (remap = 0)
Page 335: Remapping Feature
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Address range Size Peripheral Bus matrix master 3002_0000h - 3002_FFFFh 64 kB 3003_0000h - 3003_FFFFh 64 kB OTP (replica) 3004_0000h - 3FFF_FFFFh Reserved 4000_0000h - 400F_FFFFh 4010_0000h - 4FFF_FFFFh Reserved 5000_0000h - 500F_FFFFh OTP CONF, DMA CONF...
Page 336 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Table 91 Cortex®-M0 memory map (remap = 1) Address range Size Peripheral Bus matrix master 0000_0000h - 0000_3FFFh 16 kB RAM1 0000_4000h - 0000_7FFFh 16 kB RAM1 (replica) 0000_8000h - 0000_BFFFh 16 kB RAM1 (replica)
Page 337: Clock And System Controller
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Address range Size Peripheral Bus matrix master 6000_0000h - 600F_FFFFh WDT, DTIMER1/2/3, GPIO0/1 6010_0000h - 6FFF_FFFFh Reserved 7000_0000h - 7007_FFFFh BIF REGFILE (CONTROL) 7008_0000h - 700F_FFFFh PMBus/CRC/I 7010_0000h - DFFF_FFFFh Reserved E000_0000h - E00F_FFFFh Cortex®-M0 private peripherals...
Page 338 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CPUS_CFG EN_EXTWKUP 4000_0000h Enable external wakeup (WKUPIN) when the CPUS is in the hibernate state. 0: CPUS external wakeup is disabled 1: CPUS external wakeup is enabled CPUS_CFG...
Page 339 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CPUS_CFG SEL_SRC_DTIMER1 4000_0000h [17] Select the source of 1_KRN_CLK DTIMER11_KERNEL_CLK. 0: Internal CPUS clock source (required) 1: Invalid setting CPUS_CFG EN_AUX_EXTWKUP 4000_0000h [20]...
Page 340 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: No change to existing value 1: CPUS external wakeup is enabled CPUS_CFG_SE USR_CNFG0 4000_0004h Reserved CPUS_CFG_SE USR_CNFG1 4000_0004h Reserved CPUS_CFG_SE USR_CNFG2 4000_0004h...
Page 341 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CPUS_CFG_SE SEL_SRC_DTIMER1 4000_0004h [17] Select the source of 1_KRN_CLK DTIMER11_KERNEL_CLK. 0: No change to existing value 1: Invalid setting CPUS_CFG_SE EN_AUX_EXTWKUP 4000_0004h [20]...
Page 342 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CPUS_CFG_CL USR_CNFG1 4000_0008h Reserved CPUS_CFG_CL USR_CNFG2 4000_0008h Reserved CPUS_CFG_CL USR_CNFG3 4000_0008h Reserved CPUS_CFG_CL USR_CNFG4 4000_0008h Reserved CPUS_CFG_CL USR_CNFG5 4000_0008h Reserved CPUS_CFG_CL USR_CNFG6 4000_0008h...
Page 343 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CPUS_CFG_CL EN_AUX_EXTWKUP 4000_0008h [20] Enable auxiliary external wakeup source to wake up CPUS when in the power-down or hibernate state. 0: No change to existing value 1: CPUS EXT-3 wakeup source is disabled...
Page 344 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description NMI_SRC_EN EXT4_NMI_EN 4000_000Ch [9] External (EXT4_IRQn) NMI control. 0: Disabled 1: Enabled NMI_SRC_EN EXT5_NMI_EN 4000_000Ch [10] External (EXT5_IRQn) NMI control. 0: Disabled 1: Enabled NMI_SRC_EN...
Page 345: Clock Generator Unit
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: Disabled 1: Enabled NMI_SRC_EN VC1_VCONTROL_N 4000_000Ch [24] NMI control. CONTROL1 MI_EN 0: Disabled 1: Enabled NMI_SRC_EN TLM_NMI_EN 4000_000Ch [25] Telemetry NMI control.
Page 346 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem FCLK CPUS_EN & SCLK WKUPIN GATEHCLKs CortexM0IM & AUX_WKUPIN HCLK SLEEDPDEEP & Kill_me_hardly DCLK Ram1_clk HOSC_clk RAM1 & HOSC & Ram2_clk RAM2 & Kill_me_softly HOSC_clk_gated Rom_clk & Cnfg_clk CNFG AHB2APB Cnfg_otp1_w_clk...
Page 347: Clock Dividers
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem CPUS clock typical and maximum frequencies and related modules are shown in Table Table 93 CPUS clock domains Clock name Module name Typ. freq. (MHz) Max. freq. (MHz) hosc_clk alpha_clk cpu_clk...
Page 348: Clock Gating
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem The CPU clock divider scales the Cortex®-M0 microcontroller and the AMBA® bus infrastructure. The watchdog and timer clock dividers scale the counter clocks, keeping the interface on the AMBA® bus clock unchanged, and allowing the time constant of the counters to be extended to bigger time intervals.
Page 349: Primary-Source Clock Gating
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem DeepSleep mask Sleep mask SLEEPDEEP Clock enable reg GATEHCLK EN_CLK CLK_IN CLK_OUT Figure 101 Clock gating structure 15.3.2.3 Primary-source clock gating The primary-source clock gating has the structure shown in Figure 102, where the last stage of gating is controlled by the HOSC_SW_CLK_GATING_CTRL register or by the HOSC_HW_CLK_GATING_CTRL register while...
Page 350: Cgu Registers
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem DeepSleep mask Sleep mask (bit 0) (bit 0) SLEEPDEEP Clock enable reg (bit 0) GATEHCLK WKUPIN & Kill_me_softly Hosc SW clk gating control reg HRESETn Kill_me_hardly >=1 Hosc HW clk gating control reg SWEN_CLK HWEN_CLK CPUS_EN...
Page 351 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CPU_CLK_DIV_ cpuclk_div 4000_2004h [4:0] This register configures the divider of CTRL cpu_clk. The divide ratio is equal to cpuclk_div[4:0] + 1. For example, the reset setting cpuclk_div[4:0] = 0 generates a default clock frequency of cpu_clk = alpha_clk/1.
Page 352 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description KRN_CLK_DIV_ otp_kernel_clk_div 4000_2008h [29:2 This register configures the divider of CTRL the OTP kernel clock. The divide ratio is equal to otp_kernel_clk_div[4:0] + 1.
Page 353 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CLK_EN_CTRL cnfg_otp1_w_clk_g 4000_2010h Enable bit for the clock cnfg_otp1_w_clk and cnfg_clk. 0: Clock “cnfg_otp1_w_clk” is off 1: Clock “cnfg_otp1_w_clk” and cnfg_clk are live CLK_EN_CTRL cnfg_dma_clk_g...
Page 354 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CLK_EN_CTRL dtimer2_clk_g 4000_2010h [18] Enable bit for the clock dtimer2_clk and apb_per_clk. 0: Clock “dtimer2_clk” is off 1: Clock “dtimer2_clk” and apb_per_clk are live CLK_EN_CTRL dtimer3_clk_g...
Page 355 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: Clock “otp_kernel_clk” is off 1: Clock “otp_kernel_clk” is live CLK_SLEEP_M se_hosc_clk_g 4000_2014h Enable hosc_clk clock gating when SK_CNFG Cortex®-M0 enters sleep state, if the hosc_clk clock gating control has been enabled.
Page 356 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CLK_SLEEP_M se_cnfg_otp1_w_cl 4000_2014h Enable cnfg_otp1_w_clk clock gating SK_CNFG when Cortex®-M0 enters sleep state. 0: Clock “cnfg_otp1_w_clk” is not gated by CM0 power state status 1: Clock “cnfg_otp1_w_clk”...
Page 357 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: Clock “bif_per_uart_clk” is not gated by CM0 power state status 1: Clock “bif_per_uart_clk” is gated when CM0 is in sleep state CLK_SLEEP_M se_dtimer1_clk_g 4000_2014h...
Page 358 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description external reset assertion can remove clock gating if no external wakeup source has been enabled before! 0: Clock “hosc_clk” is not gated by CM0 power state status 1: Clock “hosc_clk”...
Page 359 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CLK_DEEP_SL dse_cnfg_otp1_w_c 4000_2018h Enable cnfg_otp1_w_clk2 clock EEP_MSK_CNF lk2_g gating when Cortex®-M0 enters deep sleep state. 0: Clock “cnfg_otp1_w_clk2” is not gated by CM0 power state status 1: Clock “cnfg_otp1_w_clk2”...
Page 360 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Clock “bif_per_i2c_clk” is gated when CM0 is in deep sleep state. CLK_DEEP_SL dse_bif_per_uart_c 4000_2018h [16] Enable bif_per_uart_clk clock gating EEP_MSK_CNF lk_g when Cortex®-M0 enters deep sleep...
Page 361 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: Clock “gpio1_clk” is not gated by CM0 power state status 1: Clock “gpio1_clk” is gated when CM0 is in deep sleep state HOSC_SW_CL kill_me_softly 4000_201Ch [0]...
Page 362 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CLK_EN_CTRL ram1_clk_g 4000_2030h Enable the ram1_clk clock. _SET 0: Status of “ram1_clk” clock is not affected 1: Enable “ram1_clk” clock CLK_EN_CTRL ram2_clk_g 4000_2030h...
Page 363 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: Status of “bif_per_i2c_clk” clock is not affected 1: Enable “bif_per_i2c_clk” clock CLK_EN_CTRL bif_per_uart_clk_g 4000_2030h [16] Enable the bif_per_uart_clk clock. _SET 0: Status of “bif_per_uart_clk”...
Page 364 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Enable “dtimer3_kernel_clk” clock CLK_EN_CTRL pmbus_kernel_clk_ 4000_2030h [26] Enable the pmbus_kernel_clk clock. _SET 0: Status of “pmbus_kernel_clk” clock is not affected 1: Enable “pmbus_kernel_clk”...
Page 365 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Disable “dma_clk” clock CLK_EN_CTRL cnfg_otp1_w_clk_g 4000_2034h Disable the cnfg_otp1_w_clk clock. _CLR 0: Status of “cnfg_otp1_w_clk” clock is not affected 1: Disable “cnfg_otp1_w_clk”...
Page 366 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Disable “dtimer2_clk” clock CLK_EN_CTRL dtimer3_clk_g 4000_2034h [19] Disable the dtimer3_clk clock. _CLR 0: Status of “dtimer3_clk” clock is not affected 1: Disable “dtimer3_clk”...
Page 367 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CLK_SLEEP_M se_hosc_clk_g 4000_2038h Enable hosc_clk clock gating when SK_CNFG_SET Cortex®-M0 will enter sleep state, if the hosc_clk clock gating control has been enabled.
Page 368 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: Clock “cnfg_otp1_w_clk” sleep state clock gating status unchanged 1: Enable clock “cnfg_otp1_w_clk” sleep state clock gating CLK_SLEEP_M se_cnfg_dma_clk_g 4000_2038h [10] Enable cnfg_dma_clk clock gating SK_CNFG_SET...
Page 369 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: Clock “bif_per_uart_clk” sleep state clock gating status unchanged 1: Enable clock “bif_per_uart_clk” sleep state clock gating CLK_SLEEP_M se_dtimer1_clk_g 4000_2038h [17] Enable dtimer1_clk clock gating SK_CNFG_SET...
Page 370 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CLK_SLEEP_M se_hosc_clk_g 4000_203Ch [0] Disable hosc_clk clock gating when SK_CNFG_CLR Cortex®-M0 will enter sleep state, if the hosc_clk clock gating control has been enabled.
Page 371 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: Clock “cnfg_otp1_w_clk” sleep state clock gating status unchanged 1: Disable clock “cnfg_otp1_w_clk” sleep state clock gating CLK_SLEEP_M se_cnfg_dma_clk_g 4000_203Ch [10] Disable cnfg_dma_clk clock gating SK_CNFG_CLR when the Cortex®-M0 enters sleep...
Page 372 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CLK_SLEEP_M se_bif_per_uart_clk 4000_203Ch [16] Disable bif_per_uart_clk clock gating SK_CNFG_CLR when the Cortex®-M0 enters sleep state. 0: Clock “bif_per_uart_clk” sleep state clock gating status unchanged 1: Disable clock “bif_per_uart_clk”...
Page 373 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Disable clock “gpio1_clk” sleep state clock gating CLK_DEEP_SL dse_hosc_clk_g 4000_2040h Enable hosc_clk clock gating when EEP_MSK_CNF Cortex®-M0 will enter the deep sleep G_SET state, if the hosc_clk clock gating control has been enabled.
Page 374 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CLK_DEEP_SL dse_dma_clk_g 4000_2040h Enable dma_clk clock gating when EEP_MSK_CNF the Cortex®-M0 enters deep sleep G_SET state. 0: Clock “dma_clk” deep sleep state clock gating status unchanged 1: Enable clock “dma_clk”...
Page 375 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: Clock “bif_per_pmbus_clk” deep sleep state clock gating status unchanged 1: Enable clock “bif_per_pmbus_clk” deep sleep state clock gating CLK_DEEP_SL dse_bif_per_ssp_cl 4000_2040h [14]...
Page 376 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CLK_DEEP_SL dse_wdt_clk_g 4000_2040h [20] Enable wdt_clk clock gating when EEP_MSK_CNF the Cortex®-M0 enters deep sleep G_SET state. 0: Clock “wdt_clk” deep sleep state clock gating status unchanged 1: Enable clock “wdt_clk”...
Page 377 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Disable clock “ram1_clk” deep sleep state clock gating CLK_DEEP_SL dse_ram2_clk_g 4000_2044h Disable ram2_clk clock gating when EEP_MSK_CNF the Cortex®-M0 enters deep sleep G_CLR state.
Page 378 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CLK_DEEP_SL dse_bif_per_svid_cl 4000_2044h [12] Disable bif_per_svid_clk clock gating EEP_MSK_CNF when the Cortex®-M0 enters deep G_CLR sleep state. Note: The CRC32 peripheral is using the SVID slot so this actually controls the CRC32 clock.
Page 379 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CLK_DEEP_SL dse_dtimer2_clk_g 4000_2044h [18] Disable dtimer2_clk clock gating EEP_MSK_CNF when the Cortex®-M0 enters deep G_CLR sleep state. 0: Clock “dtimer2_clk” deep sleep state clock gating status unchanged 1: Disable clock “dtimer2_clk”...
Page 380: Reset Generator Unit
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem 15.3.3 Reset generator unit The reset generator unit (RGU) implements the reset scheme of the CPUS. The CPUS reset scheme is shown in Figure 103. EN_SWPWDN i_rstn rstn &...
Page 381: Reset Sources
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem 15.3.3.1 Reset sources The CPUS supports multiple reset sources: External reset • CPUS_EN reset • SW_PWDN reset • WDT reset • CPU system reset • Soft reset • Peripheral modules reset •...
Page 382: Software Power-Down
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem An assertion of the SYSTRESETQ signal by Cortex®-M0 (debugger reset request) will cause the CPUS to be initialized, with the exception of the debugger section and WDT functionality. So the debugger will not be disconnected.
Page 383: Software Reset
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem 15.3.3.3 Software reset The CPUS software reset is invoked by setting the SWRST bit in the RSTMODS register. To perform the reset, the EN_SWRES bit in SWRST_CTRL register must be set first (enabling CPUS software reset execution), then a SWRST set bit in the RSTMODS register will cause a CPUS reset (Figure 106).
Page 384 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description RSTSR SYSRST 4000_1000h [15] Cortex®-M0 SYSRESETQ flag. 0: The last reset was not generated by SYSRESETQ 1: The last reset was generated by SYSRESETQ RSTSR SWRST...
Page 385 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description RSTMODS CNFGOTP1WRST 4000_1008h OTP wrapper reset bit. To exercise a module reset, FW has to set and to clear the proper bit accordingly. 0: Normal operation of the OTP wrapper 1: Performs a reset of the OTP...
Page 386 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Performs a reset of the D TIMER1 module RSTMODS DTIMER2RST 4000_1008h [12] module reset bit. To exercise TIMER2 a module reset, FW has to set and clear the proper bit accordingly.
Page 387 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description SWPWDN_CTRL register: only if the SW_PWDN_CTRL register has been configured does the SW_PWDN_REQ register have effect. 0: No request to enter power-down 1: Request CPUS to enter power- down.
Page 388 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description RSTMODS_SET CNFGOTP1WRST 4000_1020h OTP wrapper reset bit. To exercise a module reset, FW has to set and clear the proper bit accordingly. 0: Status of module reset unchanged 1: Forces reset of module...
Page 389 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Forces reset of module RSTMODS_SET DTIMER2RST 4000_1020h [12] module reset bit. To exercise TIMER2 a module reset, FW has to set and clear the proper bit accordingly.
Page 390 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Release reset RSTMODS_CLR BIFREGRST 4000_1024h BIF REG reset bit. To exercise a module reset, FW has to set and clear the proper bit accordingly.
Page 391: Memory
Support configurability and trimming parameters • Support a code patching mechanism • ROM and RAM are Infineon Technologies macros, highly optimized for area and power. OTP is a NVM external IP provided by a third party. 15.4.1 Read-only memory The read-only memory (ROM) module embeds an AHB wrapper, the ROM memory BIST and the ROM memory macro.
Page 392: Random-Access Memory
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem The ROM memory BIST is a HW engine used during chip production to verify the proper functionality of the module (self-check functional test). It reads the entire content of the ROM, generating a signature that is checked for correctness.
Page 393: Otp Memory Map
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem interface macro interface wrapper Power-up FSM Figure 107 OTP module block diagram 15.4.3.1 OTP memory map OTP data can be read by FW starting from address 1002_0000h, but to simplify the address decoding logic, it can also be accessed at addresses 0002_0000h, 0003_0000h and 1003_0000h.
Page 394: Otp Configuration Interface
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Address Size Description 1003_FFFFh 1004_0000h 5001_FFFFh 5002_0000h OTP configuration registers 5002_0078h 15.4.3.2 OTP configuration interface It is possible for FW to configure OTP block behavior, or access the OTP macro indirectly or perform a specific test procedure (BIST) using the registers mapped on APB space starting from 5002_0000h.
Page 395 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Table 98 OTP instructions for indirect access Instruction Instruction Source/destination Description value register Program and verify 128 bits into OTP Data taken from 5h01 PROG and VERIFY (complete write sequence: write, DATAW0-4 read-back and, if necessary, soak) Data stored into...
Page 396: Otp Timing Configuration
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem “PROG and VERIFY” operation executes a complete write sequence: Writing the data into the OTP with a WRITE pulse with a timing defined in PROG_PULSE_REG field of • OTP_PROG_C register Reading back the data with MRA-MRB-MR defined in READ1_MRAB and READ1_MR registers •...
Page 397: Otp Direct Access
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem PROG_PULSE_REG, PROG_SOAK_PULSE_REG and BIST_READ_TIMEOUT control the READ pulse width during standard programming, soaking and the BIST procedure, respectively. VPP_WARMUP_REG and VPP_WARMDOWN_REG are used to define timings of the internal charge pump during a program phase: VPP_WARMUP_REG defines how long the charge pump needs to be activated for before the programming start;...
Page 398 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem OTP timing requirements are specified in Table 100. Table 100 OTP timing requirements Timing Description Requirement [ns] READ address setup time READ address hold-time READ pulse width READ recovery time 14.8 READ access time 11.2...
Page 399 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem But the worst-case scenario is when the microcontroller asks for an address different from the prefetching one while the prefetch FSM is executing the caching access (Figure 110). In this case prefetch FSM must abort its transfer and allow AHB FSM to proceed with the new access.
Page 400: Otp Module Registers
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem a system point of view, it needs to be mitigated, for example by copying the OTP program onto the RAM and executing it from the RAM. 15.4.3.6 OTP module registers The relevant OTP-related registers and their descriptions are provided in Table 101.
Page 401 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 3: AHB = 12.5 MHz CONF FL_EVEN 5002_0004h Even row “flip” control. 0: Do not flip even rows 1: Flip even rows CONF FL_ODD 5002_0004h...
Page 402 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description DATAW2 DATA 5002_0018h [31:0] DATA[95:64] written to OTP by PROG and PROG+Verify instructions. DATAW3 DATA 5002_001Ch [31:0] DATA[127:96] written to OTP by PROG and PROG+Verify instructions.
Page 403 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description INT_RAW PWR_STAT 5002_0050h Raw (unmasked) power-up status. 0: OTP power-up not complete 1: OTP power-up complete INT_RAW RAW_INSTR_DONE 5002_0050h Raw (unmasked) instruction status. 0: OTP instruction not complete 1: OTP instruction complete INT_RAW...
Page 404 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: Fault did not occur during OTP programming 1: Fault occurred during OTP programming INT_ACTIVE_C PWR_STAT 5002_005Ch [0] Writing 1 clears PWRUP_DONE on INT_ACTIVE register.
Page 405: Memory Management Unit
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: Main memory space 1: Boot memory space 2, 3: RDNT memory space 4, 5: Main + boot memory spaces 6, 7: Main + boot + RDNT memory spaces OTP_BIST_C...
Page 406: Mmu Registers
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Each LUT contains information about how the MMU is performing the remapping and setting up access protection. For example, LUT0, covering addresses from 0000_0000h to 0000_03FFFh, is composed of the following: Write protection: If the Cortex®-M0 address is within 0000_0000h to 0000_03FFFh, the operation is a write •...
Page 407 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: OTP 2: RAM1 3: RAM2 MMU_LUT_RO PROT 4000_4004h Defines the write protection of the target address block in the target M1_DATA memory space.
Page 408 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO BLK_ADR 4000_400Ch [7:1] Defines the target address block M3_DATA into which the ROM section is remapped. MMU_LUT_RO BASE_ADR 4000_400Ch [9:8] Defines the target memory space into which the ROM section is...
Page 409 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO PROT 4000_4018h Defines the write protection of the M6_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 410 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO BASE_ADR 4000_4020h [9:8] Defines the target memory space M8_DATA into which the ROM section is remapped. 0: ROM 1: OTP 2: RAM1 3: RAM2 MMU_LUT_RO...
Page 411 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description to a protected block will result in an illegal access fault. 0: Disable write protection 1: Enable write protection MMU_LUT_RO BLK_ADR 4000_402Ch [7:1]...
Page 412 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: ROM 1: OTP 2: RAM1 3: RAM2 MMU_LUT_RO PROT 4000_4038h Defines the write protection of the M14_DATA target address block in the target memory space.
Page 413 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Enable write protection MMU_LUT_RO BLK_ADR 4000_4040h [7:1] Defines the target address block M16_DATA into which the ROM section is remapped.
Page 414 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 3: RAM2 MMU_LUT_RO PROT 4000_404Ch Defines the write protection of the M19_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 415 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO BLK_ADR 4000_4054h [7:1] Defines the target address block M21_DATA into which the ROM section is remapped. MMU_LUT_RO BASE_ADR 4000_4054h [9:8] Defines the target memory space into which the ROM section is...
Page 416 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO PROT 4000_4060h Defines the write protection of the M24_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 417 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO BASE_ADR 4000_4068h [9:8] Defines the target memory space M26_DATA into which the ROM section is remapped. 0: ROM 1: OTP 2: RAM1 3: RAM2 MMU_LUT_RO...
Page 418 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description to a protected block will result in an illegal access fault. 0: Disable write protection 1: Enable write protection MMU_LUT_RO BLK_ADR 4000_4074h [7:1]...
Page 419 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: ROM 1: OTP 2: RAM1 3: RAM2 MMU_LUT_RO PROT 4000_4080h Defines the write protection of the M32_DATA target address block in the target memory space.
Page 420 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Enable write protection MMU_LUT_RO BLK_ADR 4000_4088h [7:1] Defines the target address block M34_DATA into which the ROM section is remapped.
Page 421 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 3: RAM2 MMU_LUT_RO PROT 4000_4094h Defines the write protection of the M37_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 422 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO BLK_ADR 4000_409Ch [7:1] Defines the target address block M39_DATA into which the ROM section is remapped. MMU_LUT_RO BASE_ADR 4000_409Ch [9:8] Defines the target memory space into which the ROM section is...
Page 423 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO PROT 4000_40A8h Defines the write protection of the M42_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 424 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO BASE_ADR 4000_40B0h [9:8] Defines the target memory space M44_DATA into which the ROM section is remapped. 0: ROM 1: OTP 2: RAM1 3: RAM2 MMU_LUT_RO...
Page 425 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description to a protected block will result in an illegal access fault. 0: Disable write protection 1: Enable write protection MMU_LUT_RO BLK_ADR 4000_40BCh [7:1]...
Page 426 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: ROM 1: OTP 2: RAM1 3: RAM2 MMU_LUT_RO PROT 4000_40C8h Defines the write protection of the M50_DATA target address block in the target memory space.
Page 427 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Enable write protection MMU_LUT_RO BLK_ADR 4000_40D0h [7:1] Defines the target address block M52_DATA into which the ROM section is remapped.
Page 428 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 3: RAM2 MMU_LUT_RO PROT 4000_40DCh [0] Defines the write protection of the M55_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 429 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO BLK_ADR 4000_40E4h [7:1] Defines the target address block M57_DATA into which the ROM section is remapped. MMU_LUT_RO BASE_ADR 4000_40E4h [9:8] Defines the target memory space into which the ROM section is...
Page 430 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO PROT 4000_40F0h Defines the write protection of the M60_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 431 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO BASE_ADR 4000_40F8h [9:8] Defines the target memory space M62_DATA into which the ROM section is remapped. 0: ROM 1: OTP 2: RAM1 3: RAM2 MMU_LUT_RO...
Page 432 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description to a protected block will result in an illegal access fault. 0: Disable write protection 1: Enable write protection MMU_LUT_RO BLK_ADR 4000_4104h [7:1]...
Page 433 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: ROM 1: OTP 2: RAM1 3: RAM2 MMU_LUT_RO PROT 4000_4110h Defines the write protection of the M68_DATA target address block in the target memory space.
Page 434 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Enable write protection MMU_LUT_RO BLK_ADR 4000_4118h [7:1] Defines the target address block M70_DATA into which the ROM section is remapped.
Page 435 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 3: RAM2 MMU_LUT_RO PROT 4000_4124h Defines the write protection of the M73_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 436 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO BLK_ADR 4000_412Ch [7:1] Defines the target address block M75_DATA into which the ROM section is remapped. MMU_LUT_RO BASE_ADR 4000_412Ch [9:8] Defines the target memory space into which the ROM section is...
Page 437 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO PROT 4000_4138h Defines the write protection of the M78_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 438 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_OT BASE_ADR 4000_4200h [9:8] Defines the target memory space P0_DATA into which the OTP section is remapped. 0: ROM 1: OTP 2: RAM1 3: RAM2 MMU_LUT_OT...
Page 439 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description to a protected block will result in an illegal access fault. 0: Disable write protection 1: Enable write protection MMU_LUT_OT BLK_ADR 4000_420Ch [7:1]...
Page 440 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: ROM 1: OTP 2: RAM1 3: RAM2 MMU_LUT_OT PROT 4000_4218h Defines the write protection of the P6_DATA target address block in the target memory space.
Page 441 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Enable write protection MMU_LUT_OT BLK_ADR 4000_4220h [7:1] Defines the target address block P8_DATA into which the OTP section is remapped.
Page 442 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 3: RAM2 MMU_LUT_OT PROT 4000_422Ch Defines the write protection of the P11_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 443 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_OT BLK_ADR 4000_4234h [7:1] Defines the target address block P13_DATA into which the OTP section is remapped. MMU_LUT_OT BASE_ADR 4000_4234h [9:8] Defines the target memory space into which the OTP section is...
Page 444 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_OT PROT 4000_4240h Defines the write protection of the P16_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 445 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_OT BASE_ADR 4000_4248h [9:8] Defines the target memory space P18_DATA into which the OTP section is remapped. 0: ROM 1: OTP 2: RAM1 3: RAM2 MMU_LUT_OT...
Page 446 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description to a protected block will result in an illegal access fault. 0: Disable write protection 1: Enable write protection MMU_LUT_OT BLK_ADR 4000_4254h [7:1]...
Page 447 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: ROM 1: OTP 2: RAM1 3: RAM2 MMU_LUT_OT PROT 4000_4260h Defines the write protection of the P24_DATA target address block in the target memory space.
Page 448 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Enable write protection MMU_LUT_OT BLK_ADR 4000_4268h [7:1] Defines the target address block P26_DATA into which the OTP section is remapped.
Page 449 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 3: RAM2 MMU_LUT_OT PROT 4000_4274h Defines the write protection of the P29_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 450 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_OT BLK_ADR 4000_427Ch [7:1] Defines the target address block P31_DATA into which the OTP section is remapped. MMU_LUT_OT BASE_ADR 4000_427Ch [9:8] Defines the target memory space into which the OTP section is...
Page 451 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_OT PROT 4000_4288h Defines the write protection of the P34_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 452 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_OT BASE_ADR 4000_4290h [9:8] Defines the target memory space P36_DATA into which the OTP section is remapped. 0: ROM 1: OTP 2: RAM1 3: RAM2 MMU_LUT_OT...
Page 453 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description to a protected block will result in an illegal access fault. 0: Disable write protection 1: Enable write protection MMU_LUT_OT BLK_ADR 4000_429Ch [7:1]...
Page 454 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: ROM 1: OTP 2: RAM1 3: RAM2 MMU_LUT_OT PROT 4000_42A8h Defines the write protection of the P42_DATA target address block in the target memory space.
Page 455 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Enable write protection MMU_LUT_OT BLK_ADR 4000_42B0h [7:1] Defines the target address block P44_DATA into which the OTP section is remapped.
Page 456 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 3: RAM2 MMU_LUT_OT PROT 4000_42BCh Defines the write protection of the P47_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 457 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_OT BLK_ADR 4000_42C4h [7:1] Defines the target address block P49_DATA into which the OTP section is remapped. MMU_LUT_OT BASE_ADR 4000_42C4h [9:8] Defines the target memory space into which the OTP section is...
Page 458 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_OT PROT 4000_42D0h Defines the write protection of the P52_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 459 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_OT BASE_ADR 4000_42D8h [9:8] Defines the target memory space P54_DATA into which the OTP section is remapped. 0: ROM 1: OTP 2: RAM1 3: RAM2 MMU_LUT_OT...
Page 460 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description to a protected block will result in an illegal access fault. 0: Disable write protection 1: Enable write protection MMU_LUT_OT BLK_ADR 4000_42E4h [7:1]...
Page 461 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: ROM 1: OTP 2: RAM1 3: RAM2 MMU_LUT_OT PROT 4000_42F0h Defines the write protection of the P60_DATA target address block in the target memory space.
Page 462 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Enable write protection MMU_LUT_OT BLK_ADR 4000_42F8h [7:1] Defines the target address block P62_DATA into which the OTP section is remapped.
Page 463 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 3: RAM2 MMU_LUT_RA PROT 4000_4404h Defines the write protection of the M11_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 464 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RA BLK_ADR 4000_440Ch [7:1] Defines the target address block M13_DATA into which the RAM1 section is remapped. MMU_LUT_RA BASE_ADR 4000_440Ch [9:8] Defines the target memory space into which the RAM1 section is...
Page 465 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RA PROT 4000_4418h Defines the write protection of the M16_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 466 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RA BASE_ADR 4000_4420h [9:8] Defines the target memory space M18_DATA into which the RAM1 section is remapped. 0: ROM 1: OTP 2: RAM1 3: RAM2 MMU_LUT_RA...
Page 467 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description to a protected block will result in an illegal access fault. 0: Disable write protection 1: Enable write protection MMU_LUT_RA BLK_ADR 4000_442Ch [7:1]...
Page 468 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: ROM 1: OTP 2: RAM1 3: RAM2 MMU_LUT_RA PROT 4000_4438h Defines the write protection of the M114_DATA target address block in the target memory space.
Page 469 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Enable write protection MMU_LUT_RA BLK_ADR 4000_4500h [7:1] Defines the target address block M20_DATA into which the RAM2 section is remapped.
Page 470 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 3: RAM2 MMU_LUT_RA PROT 4000_450Ch Defines the write protection of the M23_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 471 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RA BLK_ADR 4000_4514h [7:1] Defines the target address block M25_DATA into which the RAM2 section is remapped. MMU_LUT_RA BASE_ADR 4000_4514h [9:8] Defines the target memory space into which the RAM2 section is...
Page 472 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RA PROT 4000_4520h Defines the write protection of the M28_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 473 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RA BASE_ADR 4000_4528h [9:8] Defines the target memory space M210_DATA into which the RAM2 section is remapped. 0: ROM 1: OTP 2: RAM1 3: RAM2 MMU_LUT_RA...
Page 474 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description to a protected block will result in an illegal access fault. 0: Disable write protection 1: Enable write protection MMU_LUT_RA BLK_ADR 4000_4534h [7:1]...
Page 475 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: ROM 1: OTP 2: RAM1 3: RAM2 MMU_PER_SP 4000_4600h [27:0] Configures the write protection of the peripherals mapped in the peripheral space.
Page 476 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description [0]: Not used [1]: WDT, D , GPIO TIMER [2]: UART, I C, SSP, PMBus [3]: Trim [4]: Analog [5]: VSP0 [6]: VSP1 [7]: VSP2 [8]: VCTRL0...
Page 477 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description [8]: VCTRL0 [9]: VCTRL1 [10]: PID0 [11]: PID1 [12]: ISP0 [13]: ISP1 [14]: PWM [15]: COMMON [16]: TELEM0 [17]: TELEM1 [18]: FAULT0 [19]: FAULT1 [20]: FAN1...
Page 478: Dma Controller
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem 15.6 DMA controller The DMA controller is an Arm® PrimeCell IP (PL230); extensive documentation can be found in the “Arm® PrimeCell µDMA controller (PL230) Technical Reference Manual”. The principal features of the DMA controller are: It is compatible with AHB-Lite for DMA transfers •...
Page 479: Dma Memory Map
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem The controller AHB block contains a single AHB-Lite master that enables it to transfer data from a source AHB slave to a destination AHB slave using a 32-bit data bus. The controller is compliant with the AMBA® 3 AHB-Lite protocol.
Page 480: Dma Channel Assignment
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem 15.6.3 DMA channel assignment DMA channel assignment is shown in Table 104. The DMA macro supports single transfer requests (SREQs) and multiple transfer requests (REQs), but multiple transfer requests are currently not supported by the XDPP1100. DMA channel 0 has the highest priority, channel 15 the lowest.
Page 481: Dma Registers
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem 15.6.4 DMA registers The relevant DMA-related registers and their descriptions are provided in Table 105. Table 105 DMA-related register description Register name Field name Access Address Bits Description DMA_STATUS MASTER_ENABLE 5000_0000h...
Page 482 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description [0] Controls HPROT[1] to indicate if a privileged access is occurring Notes: 1. When bit[n]=1, then the corresponding H is high PROT 2.
Page 483 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description dma_sreq input from generating DMA requests. For each bit [x], On READ: 0: DMA channel x responds to requests that it receives on dma_req or dma_sreq.
Page 484 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Disables dma_req and dma_sreq on channel x from generating DMA requests DMA_CHNL_R CHNL_REQ_MASK_ 5000_0024h [15:0] The write-only register enables EQ_MASK_CLR DMA request on a per-channel basis.
Page 485 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: DMA channel x is using the alternate data structure On WRITE: 0: No effect. Use the CHNL_PRI_ALT_CLR Register to set bit [x] to 0.
Page 486 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description DMA_ERR_CLR ERR_CLR 5000_004Ch [0] The read/write ERR_CLR register returns the status of dma_err, and enables you to set dma_err low. On READ: 0: dma_err is low 1: dma_err is high...
Page 487: General-Purpose Input Output (Gpio) Module
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description For each bit [x]: 0: No change to DMA channel x interrupt 1: Clear DMA channel x interrupt DMA_ERR_INT_CLR 5000_100Ch [31] DMA error interrupt clear.
Page 488: Gpio Registers
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem 15.7.1 GPIO registers The relevant GPIO-related registers and their descriptions are provided in Table 106. Table 106 GPIO register description Register name Field name Access Address Bits Description GPIODATA DATA 6004_0000h...
Page 489 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: GPIOx configured as input 1: GPIOx configured as output GPIOIS INTSENSE 6004_0404h [7:0] The GPIOIS register is the interrupt sense register.
Page 490 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description GPIOIE allow the corresponding 6005_0410h pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables interrupt triggering on that pin.
Page 491 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description detection logic register. Writing a 0 has no effect. This register is write- only and all bits are cleared by a reset.
Page 492: Wdt Module
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description GPIOPeriphID2 Revision 6004_0FE8h [7:4] Returns the peripheral revision number with 0 indicating the initial 6005_0FE8h revision. GPIOPeriphID3 Configuration 6004_0FECh [7:0] Returns the configuration option of the peripheral.
Page 493: Watchdog Block Diagram
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem 15.8.1 Watchdog block diagram The watchdog block structure is shown in Figure 113. Test Free running integration counter registers Identitification Address registers decoder Read data Lock register generation Figure 113 Watchdog block structure 15.8.2...
Page 494 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Enable reset output WDOGINTCLR INTCLR 6000_000Ch [31:0] Interrupt clear. This write-only register clears the watchdog interrupt, and reloads the counter from the value in WDOGLOAD.
Page 495 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description WDOGITOP ITINT 6000_0F04h Integration test WDOGINT value. Sets the value of the WDOGINT signal when in integration test mode. 0: Set WDOGINT low 1: Set WDOGINT high WDOGPERIPHI PartNumber0...
Page 496: Modules
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description used as a standard cross-peripheral ID system. In this case CellID[31:0] = 0xB105F00D. WDOGPCELLID WDOGPCELLID3 6000_0FFCh [7:0] CellID[31:24]. Together with the other cell ID registers, CellID[31:0] is used as a standard cross-peripheral ID system.
Page 497: Dual-Timer Block Diagram
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem 15.9.1 Dual-timer block diagram The dual-timer block diagram is shown in Figure 114. Free running counter 1 Test integration Free running registers counter 2 Identitification Address registers decoder Read data TIMINTC generation...
Page 498 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description TIM_SEQ0_TIMERLOAD value replaces the current count value. Then each time the counter reaches zero, the current count value is reset to the value written to TIM_SEQ0_TIMERBGLOAD.
Page 499 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description TIM_SEQ0_TIM CLRINT 6001_000Ch [31:0] Interrupt clear. A write of any value ERINTCLR 6002_000Ch to this write-only register clears the counter interrupt. 6003_000Ch TIM_SEQ0_TIM RAWINT...
Page 500 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description If values are written to both the TIM_SEQ1_TIMERLOAD and TIM_SEQ1_TIMERBGLOAD registers before an enabled rising edge on TIMCLK, the following occurs: On the next enabled clock edge, the value written to the TIM_SEQ1_TIMERLOAD value...
Page 501: Pmbus Module
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description TIM_SEQ1_TIM TMODE 6001_0028h Timer operation mode. ERCONTROL 6002_0028h 0: Free-running mode 6003_0028h 1: Periodic mode TIM_SEQ1_TIM 6001_0028h Timer enable. ERCONTROL 6002_0028h 0: Timer disabled 6003_0028h...
Page 502 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem clr_irq Irq_bus fsm_stat PMBUS_APB fsm_ctrl fsm_cnfg SCL_OUT SDA_OUT SCL_IN SCL_IN_F SDA_IN SDA_IN_F I2CF PMBUS_TOP Figure 115 PMBus block diagram The PMBus module manages the I C/SMBus/PMBus transactions by using a CPU. The advantage of such an approach is to have a fully programmable, configurable, and extensible SMBus/PMBus interface that can support any kind of commands.
Page 503: Pmbus Clock Scheme
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem provided to avoid clock stretch stalling; watchdogs are enabled only when a transaction is in progress. The PMB_FSM embeds an HW CRC logic for RX PEC and TX PEC calculations. The FSM is organized into two main sections: the RX section and the TX section.
Page 504: 15.10.3.1 Configuration
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem 15.10.3.1 Configuration To enable the CPU to manage the PMBus transactions, the following actions must be performed (Figure 117): Enable the PMBus APB clocks interface (bif_per_pmbus_clk). • Configure and enable the PMBus KERNEL clocks (pmbus_kernel_clk). •...
Page 505: 15.10.3.2 Write Transaction
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem 15.10.3.2 Write transaction The following is an example of how to manage an incoming WRITE_BYTE transaction with and without PEC, where the host places data on the I C bus and the slave decodes the data.
Page 506 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem PMBUS Write Transaction Wait irq (RX) Wait for irq (START) Read I_CODE Read I_CODE Clear Interrupt flag: isr = isr Clear Interrupt flag: isr = isr Load Adr_lut with a valid set of address Select Ack Source = ADR_HIT Was ACK ? Trigger CTRL_RX...
Page 507: 15.10.3.3 Read Byte Transaction
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem 15.10.3.3 Read byte transaction Here the process of managing an incoming READ_BYTE transaction (Figure 119) with and without PEC is described, where the slave has to place data on the I C bus following an initial sequence where the host sends the read request.
Page 508 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Clear the interrupt event (write “1” into ISR.IFx). • Prepare the TX_BUFFER with the expected data, set the number of bytes to be transmitted, then trigger the • FSM to move forward.
Page 509 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem PMBUS Read Transaction Wait for irq_rx or irq_stop or irq_tx_after_start Wait for irq_rx_after_start Clear Interrupt flag: Irq_tx_after_start ? isr = isr Write Transation or Read address Slave_address = status.slave_address Clear Interrupt flag: isr = isr Slave_address...
Page 510: 15.10.3.4 Pmbus Ara Command
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem 15.10.3.4 PMBus ARA command The ARA incoming transaction can be managed with the following sequence (Figure 120): Enable irq_rx_ara to detect ARA transaction. • Wait for irq_rx_ara interrupt assertion. •...
Page 511: Pmbus Registers
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem 15.10.4 PMBus registers The relevant PMBus-related registers and their descriptions are provided in Table 109. Table 109 PMBus-related register descriptions Register name Field name Access Address Bits Description STATUS BUSY 7008_0000h...
Page 512 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: SCL_IN is at low level 1: SCL_IN is at high level STATUS SDA_IN 7008_0000h [27] Status of the debounced SDA input signal.
Page 513 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CNFG PREEMPTIVE 7008_0004h Enable/Disable automatic handler of ACK/NACK. 0: CPU is in charge to generate ACK/NACK 1: HW takes care of generation of ACK/NACK.
Page 514 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 5: Signal must be stable for at least six clock signals 6: Signal must be stable for at least seven clock signals 7: Signal must be stable for at least eight clock signals CNFG...
Page 515 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 2: RX address write IRQ 3: RX IRQ 4: RX address read IRQ 5: TX IRQ 6: Stop IRQ 7: Watchdog timeout IRQ 8: Busy IRQ ARA_CW EN_ARA_CW...
Page 516 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Generate ACK CTRL_RX ACK_SRC_SEL 7008_0010h [4:2] ACK/NACK source selection. Define which kind of comparison action is used to automatically generate the ACK/NACK event after a byte has been received.
Page 517 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description RXPEC DATA 7008_0018h [7:0] The RXPEC register reflects the ongoing PEC CRC calculation for the incoming bytes (address included). The RXPEC register is cleared at detection of a start event.
Page 518 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description manage multiple DATA_LUTs with a single access. 0: No operation 1: Clear all the DATA_LUTs 2: Set all the DATA_LUTs in the index interval [MIN_RANGE : MAX_RANGE] to 1 3: Initialize all the DATA_LUTs to 1...
Page 519 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 3: ADDR responds to both read and write transactions ADDR_LUT0_A ADDR 7008_0040h [8:2] Sets the slave address at which the DDR_CW PMBus interface will respond.
Page 520 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description ADDR_LUT2_A TYPE 7008_0048h [10:9] Transaction type. Defines the type DDR_CW of transaction associated with the defined slave address. 0: PMBus transaction 1: I 2: Reserved 3: Reserved...
Page 521 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 3: Reserved ADDR_LUT5_A EN_ADDR 7008_0054h [1:0] Enable/Disable this ADDR_LUT5 DDR_CW configuration word. 0: ADDR configuration word is disabled 1: ADDR responds to write transactions only 2: ADDR responds to read transactions only...
Page 522 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: ADDR responds to write transactions only 2: ADDR responds to read transactions only 3: ADDR responds to both read and write transactions ADDR_LUT7_A ADDR...
Page 523 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description [7:0] = Byte 0 DATA_LUT3_D DATA 7008_008Ch [31:0] The 32-bit data word 3 in 8x32-bit ATA_W (or 8x4-byte) scratch table used in the prediction ACK/NACK approach or as buffer for the data to be transmitted over the PMBus...
Page 524 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description transmitted over the PMBus interface. [31:24] = Byte 3 [23:16] = Byte 2 [15:8] = Byte 1 [7:0] = Byte 0 DATA_LUT_BIT INDEX 7008_00C0h...
Page 525 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description STATUS_IOUT[ STATUS_IOUT 7008_0110h [7:0] Loop 0 STATUS_IOUT command data for HW-based SMBALERT generation. STATUS_IOUT[ STATUS_IOUT 7008_0114h [7:0] Loop 1 STATUS_IOUT command data for HW-based SMBALERT generation.
Page 526 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description STATUS_PWR STATUS_PWRGOOD 7008_0148h Loop 0 STATUS_PWRGOOD GOOD[0] command data for HW-based SMBALERT generation. STATUS_PWR STATUS_PWRGOOD 7008_014Ch Loop 1 STATUS_PWRGOOD command data for HW-based GOOD[1] SMBALERT generation.
Page 527 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description STATUS_MASK STATUS_INPUT_MA 7008_0178h [7:0] Loop 0 STATUS_INPUT mask to _LP0[2] enable/disable bits for SMBALERT generation. For each bit [x]: 0: Bit [x] enabled for SMBALERT generation 1: Bit [x] enabled for SMBALERT generation...
Page 528 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: Bit [x] enabled for SMBALERT generation 1: Bit [x] enabled for SMBALERT generation STATUS_MASK STATUS_IOUT_MAS 7008_0194h [7:0] Loop 1 STATUS_IOUT mask to _LP1[1] enable/disable bits for SMBALERT generation.
Page 529: I 2 C Module
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Bit [x] enabled for SMBALERT generation STATUS_MASK STATUS_FAN12_MA 7008_01ACh [7:0] Loop 1 STATUS_FAN12 mask to _LP1[7] enable/disable bits for SMBALERT generation.
Page 530: 15.11.1.1 Status Information
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem 15.11.1.1 Status information The state of the interface at any time is indicated by the status code recorded in the STAT register. There are 28 status codes corresponding to the different possible states of the I C, plus a further code that indicates when no relevant status information is available.
Page 531: 15.11.1.2 Master Transmit
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Code Status Last byte transmitted in slave mode, ACK received Second Address byte + Write bit transmitted, ACK received Second Address byte + Write bit transmitted, ACK not received Unused Unused Unused...
Page 532 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Code MI2CV State Microprocessor Response Next MI2CV Action Or set STA, clear IFLG Transmit START when bus free Arbitration lost, SLA + Write Clear IFLG, AAK=0 Receive data byte, transmit bit received, ACK transmitted not ACK Received data byte, transmit...
Page 533: 15.11.1.3 Master Receive
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Code MI2CV State Microprocessor response Next MI2CV action Second Address byte + Write Same as for code D0h Same as for code D0h bit transmitted, ACK not received If a repeated START condition has been transmitted, the status code will be 10h instead of 08h.
Page 534 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Code MI2CV State Microprocessor response Next MI2CV action Transmit START when bus free Address + Read bit Clear IFLG, AAK=0 Receive data byte, transmit transmitted, ACK received not ACK Receive data byte, transmit Or clear IFLG, AAK=1 Address + Read bit...
Page 535: 15.11.1.4 Slave Transmit
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Code MI2CV State Microprocessor response Next MI2CV action Data byte received, not ACK Read DATA, set STA, clear Transmit repeated START transmitted IFLG Or read DATA, set STP, clear Transmit STOP IFLG Or read DATA, set STA and...
Page 536: 15.11.1.5 Slave Receive
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem 15.11.1.5 Slave receive In slave receive mode, a number of data bytes are received from a master transmitter. The I C will enter slave receive mode when it receives its own slave address and a write bit (LSB = 0) after a START condition.
Page 537 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description ADDR.SLA[4:0]=11110b, the I peripheral recognizes this as the first part of a 10-bit address and if the next two bits match ADDR.SLAX[1:0] it sends an ACK.
Page 538 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description state C8h then return to the idle state (status code F8h) when IFLG is cleared. 1: An acknowledge (low level on SDA) will be sent during the acknowledge clock pulse on the I C bus if:...
Page 539 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: The I C peripheral enters master mode and will transmit a START condition on the bus when the bus is free.
Page 540 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 04h: Address + write bit transmitted, ACK not received 05h: Data byte transmitted in master mode, ACK received 06h: Data byte transmitted in master mode, ACK not received 07h: Arbitration lost in address or data byte...
Page 541 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 17h: Data byte transmitted in slave mode, ACK received 18h: Data byte transmitted in slave mode, ACK not received 19h: Last byte transmitted in slave mode, ACK received 1Ah: Second address byte + write bit transmitted, ACK received...
Page 542: Crc Module
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description the address matches XADDR.SLAX[7:0] the I C peripheral generates an interrupt and goes into slave mode. SRST 700B_001Ch [6:0] Software reset. A software reset of the I C peripheral is applied upon writing any value to this register.
Page 543: Crc Registers
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem 15.12.1 CRC registers The relevant CRC-related registers and their descriptions are provided in Table 117. Table 117 CRC register descriptions Register name Field name Access Address Bits Description DATA 7009_0000h [31:0]...
Page 544: Uart
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem 15.13 UART The UART module is an Arm® PrimeCell IP (PL011); extensive documentation can be found in the “Arm® PrimeCell UART (PL011) Technical Reference Manual”. The UART provides the following: Programmable use of UART or IrDA SIR input/output •...
Page 545: Uart Registers
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Read data[11:0] nUARTRST rxd[7:0] txd[7:0] 32 x8 32 x8 Write data[7:0] transmit receive FIFO FIFO PRDATA[15:0] PWDATA[15:0] Control and status nSIROUT PADDR[11:2] Transmitter Baud rate divisor UARTTXD interface PWRITE Baud rate Baud16...
Page 546 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description select. In FIFO mode, this error is associated with the character at the top of the FIFO. UARTDR 700C_0000h [10] Break error.
Page 547 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.
Page 548 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description the FEN bit in the line control register, UARTLCR_H. If the FIFO is disabled, this bit is set when the receive holding register is empty.
Page 549 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description signal according to the low-power divisor value written to the UARTILPR register. The low-power divisor value is calculated as follows: Low-power divisor (ILPDVSR) = (FUARTCLK / FIrLPBaud16) where FIrLPBaud16 is nominally...
Page 550 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description Error = (231911 - 230400)/230400 × 100 = 0.656 percent The maximum error using a 6-bit UARTFBRD register = 1/64 × 100 = 1.56 percent.
Page 551 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description UARTLCR_H WLEN 700C_002Ch Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: 0: 5 bits 1: 6 bits 2: 7 bits...
Page 552 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description pulse with a width of 3/16 of the bit period. If this bit is set to 1, low- level bits are transmitted with a pulse width that is three times the period of the IrLPBaud16 input signal, regardless of the selected bit...
Page 553 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping.
Page 554 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description when the nUARTCTS signal is asserted. 0: CTS HW flow control is disabled 1: CTS HW flow control is enabled UARTIFLS TXIFLSEL 700C_0034h...
Page 555 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description UARTIMSC DCDMIM 700C_0038h nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set.
Page 556 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description interrupt is set. A write of 0 clears the mask. UARTIMSC OEIM 700C_0038h [10] Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt.
Page 557 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description interrupt state of the UARTRIINTR interrupt. UARTMIS CTSMMIS 700C_0040h nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt.
Page 558 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Clear interrupt UARTICR DCDMIC 700C_0044h nUARTDCD modem interrupt clear. 0: No effect 1: Clear interrupt UARTICR DSRMIC 700C_0044h nUARTDSR modem interrupt clear. 0: No effect 1: Clear interrupt UARTICR...
Page 559 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description PARTNUMBER[11:0] identifies the peripheral. In this case the three- digit product code, 0x011, is returned. UARTPeriphID PARTNUMBER1 700C_0FE4h [3:0] PARTNUMBER[11:8]. Together with the lower bits from PARTNUMBER0, PARTNUMBER[11:0] identifies the peripheral.
Page 560: Debugger Port
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description standard cross-peripheral ID system. In this case UARTPCellID[31:0] = 0xB105F00D. 15.14 Debugger port The debugger port on the XDPP1100 is implemented through the Cortex®-M0 serial wire debugger (SWD) interface, a two-wire serial protocol that is used to access the Cortex®...
Page 561 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem The serial data line has to be driven both by the debugger and XDPP1100 (bidirectional communication protocol), to avoid contention. The SWD protocol defines slots for data transmitting/receiving and turnaround periods.
Page 562 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Figure 125 SWD enabling logic on XADDR1 In functional mode, TEST_GATE is latched to Logic 0 during power-up (XADDR1 is connected to an external resistor), so SWD IOs cannot be enabled by mistake. The XADDR1 pin can used anyway for multi-configuration purposes after the power-up sequence.
Page 563 XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Central processing unit subsystem Figure 126 XADDR1 timing diagram Additionally, the SWD interface can be enabled any time after the power-up, by writing in the CPUS_CFG register (DS_DBGPORT bit) using the I C interface (or FW).
Page 564: Revision History
XDP™ XDPP1100, XDPP1100A reference manual Digital power controller Revision history Revision history Document Date Description of changes revision V 1.0 2021-08-25 Initial public release • V 1.1 2023-01-03 Figure 47: updated signal resolutions • Figure 49: updated signal resolutions • Figure 50: updated signal resolutions, changed text "C"...
Page 565: Disclaimer
With respect to any examples, hints or any typical 81726 Munich, Germany values stated herein and/or any information WARNINGS regarding the application of the product, Infineon Technologies hereby disclaims any and all Due to technical requirements products may contain warranties and liabilities of any kind, including ©...

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