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DG_1711_PL21_1802_031149
XDPL8218 design guide
For high power factor flyback converter with constant voltage output
About this document
Scope and purpose
This document is a design guide using
flyback converter, which regulates the secondary output voltage supply to the second-stage Constant Current
(CC) converter for LED lighting applications.
Intended audience
Power supply design engineers, field application engineers.
Table of contents
About this document ....................................................................................................................... 1
Table of contents ............................................................................................................................ 1
1
Introduction .......................................................................................................................... 3
2
Design specifications .............................................................................................................. 5
3
Transformer design ................................................................................................................ 6
4
Flyback MOSFET and secondary main output diode selection ...................................................... 8
5
CS resistor and GD pin-related design ...................................................................................... 10
6
MOSFET maximum current cycle-by-cycle limit and start-up phase design .................................. 11
7
HV pin-related design ............................................................................................................ 14
8
V
9
Output OVP-related design ..................................................................................................... 17
10
DC link filter and secondary main output capacitance ............................................................... 18
11
Input voltage levels for start-up and protection ....................................................................... 19
12
ZCD pin-related design ........................................................................................................... 20
13
Secondary-side regulation FB circuit design ............................................................................. 22
14
Regulated mode parameters .................................................................................................. 26
14.1
Digital notch filter .................................................................................................................................. 26
14.2
On-time limit and switching frequency limit (QRM1/DCM) ................................................................. 26
14.3
ABM FB voltage sensing and control .................................................................................................... 27
14.4
FB voltage mapping and mode transition ............................................................................................ 28
14.5
FB voltage maximum limit ramp .......................................................................................................... 29
15
Other protection-related parameters ...................................................................................... 30
15.1
V
OVP ................................................................................................................................................... 30
15.2
15.3
IC over-temperature protection ........................................................................................................... 30
15.4
Primary MOSFET over-current protection ............................................................................................ 30
15.5
Debug mode .......................................................................................................................................... 31
16
PCB layout guide ................................................................................................................... 32
Design Guide
XDPL8218
as the control IC of the front-stage High Power Factor (HPF)
UVP ....................................................................................................................... 30
Please read the Important Notice and Warnings at the end of this document
V 1.0
2018-06-06
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Summary of Contents for Infineon XDPL8218
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Page 1: Table Of Contents
DG_1711_PL21_1802_031149 XDPL8218 design guide For high power factor flyback converter with constant voltage output About this document Scope and purpose This document is a design guide using XDPL8218 as the control IC of the front-stage High Power Factor (HPF) flyback converter, which regulates the secondary output voltage supply to the second-stage Constant Current (CC) converter for LED lighting applications. - Page 2 XDPL8218 design guide For high power factor flyback converter with constant voltage output Introduction Parameter configuration list, set-up and procedures ..............33 17.1 Parameter configuration list ......................... 33 17.2 Parameter configuration set-up ......................34 17.3 Parameter configuration procedures ....................35 Fine-tuning guide ........................
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Page 3: Introduction
For LED lighting applications, XDPL8218 flyback CV output usually is converted to a CC output by a second- stage DC-DC switching or linear regulator. XDPL8218 comes in a PG-DSO-8 package with eight pins, as shown in the datasheet [1]. The main functions of each pin are shown in... - Page 4 Graphical User Interface (GUI) on a PC. This enables a lower Bill of Materials (BOM) and rapid engineering changes without the need for complex component design iterations. Note: By default, the configurable parameters of a new XDPL8218 chip from Infineon are empty, so it is necessary to configure them before any application testing. Figure 2 shows the XDPL8218 design guide document sectioning for each step of the recommended design flow.
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Page 5: Design Specifications
XDPL8218 design guide For high power factor flyback converter with constant voltage output Design specifications Design specifications A front-stage HPF flyback converter with CV output set-point V of 54 V (54 V/0.8 A) has been selected as a out,setpoint design example. The design specifications are shown in... -
Page 6: Transformer Design
For good reliability against input voltage surge, it is recommended to reserve a voltage margin V margin,FET minimum 50 V from V . If XDPL8218 input Over-Voltage Protection (OVP) would be enabled later in Section (BR)DSS 10, as a rule of thumb, V should be at least 25 percent of V , which is equivalent to 76.25 V based on... - Page 7 XDPL8218 design guide For high power factor flyback converter with constant voltage output Transformer design As a result, the primary main winding inductance L can be defined and calculated as: �� ∙ �� ∙ (�� + �� ����,������ ( ���� ) ������,����������������...
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Page 8: Flyback Mosfet And Secondary Main Output Diode Selection
XDPL8218 design guide For high power factor flyback converter with constant voltage output Flyback MOSFET and secondary main output diode selection Flyback MOSFET and secondary main output diode selection The CoolMOS P7 MOSFET series is the latest CoolMOS product family and targets customers looking for high performance and at the same time being price sensitive. - Page 9 XDPL8218 design guide For high power factor flyback converter with constant voltage output Flyback MOSFET and secondary main output diode selection The selectable MOSFET R can be defined as: ds(on),25°C �� ∙ �� (10) ������,�������� �� ≤ ���� ( ���� ) ,25°��...
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Page 10: Cs Resistor And Gd Pin-Related Design
XDPL8218 design guide For high power factor flyback converter with constant voltage output CS resistor and GD pin-related design CS resistor and GD pin-related design Figure 5 shows the connections of the Current Sense (CS) resistor R , gate resistor R... -
Page 11: Mosfet Maximum Current Cycle-By-Cycle Limit And Start-Up Phase Design
To limit the flyback output power to the LEDs below 100 VA as per UL1310 requirements under such fault conditions, especially at high input voltage, XDPL8218 regulated mode features the CS pin voltage level 1 for MOSFET maximum current cycle-by-cycle limit V... - Page 12 XDPL8218 design guide For high power factor flyback converter with constant voltage output MOSFET maximum current cycle-by-cycle limit and start-up phase design �� = ��. ���� �� ��������,����,��,����,������ parameter defines the value of V ) variable when the estimated input voltage V...
- Page 13 XDPL8218 design guide For high power factor flyback converter with constant voltage output MOSFET maximum current cycle-by-cycle limit and start-up phase design parameter in Figure 8 denotes the initial CS pin voltage level 1 for MOSFET current limit on the input OCP1,init voltage measurement pulse, during pre-start-up check.
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Page 14: Hv Pin-Related Design
XDPL8218 design guide For high power factor flyback converter with constant voltage output HV pin-related design HV pin-related design As shown in Figure 9, HV series resistor R is connected from the HV pin to the cathodes of HV diode D... -
Page 15: Vcc Capacitance And Output Uvp Design
XDPL8218 design guide For high power factor flyback converter with constant voltage output VCC capacitance and output UVP design capacitance and output UVP design To fulfill the Energy Star time-to-light requirement of 500 ms, the V voltage maximum charging time for IC activation, t should not exceed 350 ms. - Page 16 XDPL8218 design guide For high power factor flyback converter with constant voltage output VCC capacitance and output UVP design Under the single-fault condition of second-stage CC regulator MOSFET drain and source pins being shorted, the main output could be clamped by a low-output LED voltage, which could result in the flyback MOSFET continuously operating in the saturation region due to low V and gate-drive voltages.
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Page 17: Output Ovp-Related Design
XDPL8218 design guide For high power factor flyback converter with constant voltage output Output OVP-related design Output OVP-related design Under the single-fault condition of the FB pin open, the main output voltage would rise quickly above V out,setpoint As shown in... -
Page 18: Dc Link Filter And Secondary Main Output Capacitance
DC link bus voltage DC,filter DC,filter To compensate for the input current displacement caused by the C , the XDPL8218 enhanced Power Factor DC,filter Correction (PFC) feature can be enabled by configuration of the compensation gain parameter named C . As a start, it can be configured as per the C value. -
Page 19: Input Voltage Levels For Start-Up And Protection
XDPL8218 design guide For high power factor flyback converter with constant voltage output Input voltage levels for start-up and protection Input voltage levels for start-up and protection parameter refers to the enable switch for maximum input voltage start-up check and input OVP, based... -
Page 20: Zcd Pin-Related Design
XDPL8218 design guide For high power factor flyback converter with constant voltage output ZCD pin-related design ZCD pin-related design ZCD pin filter capacitor C , ZCD series resistor R and ZCD shunt resistor R are connected based on the ZCD,1... - Page 21 XDPL8218 design guide For high power factor flyback converter with constant voltage output ZCD pin-related design −0.14 ∙ 3.2 ∙ ( 65 + 0.7 ) �� = − ∙ [ √ 2 ∙ 350 + ] = 14.6 ��Ω ������,1,������...
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Page 22: Secondary-Side Regulation Fb Circuit Design
Figure The FB pin does not need any external pull-up as XDPL8218 has a fixed voltage reference V of 2.428 V, which is internally connected to its FB pin via an internal pull-up resistor. The internal pull-up resistor value is configurable based on the R parameter. - Page 23 FB,pull,up FB,pull,up XDPL8218’s internal ADC sampling point for the FB pin voltage signal is right after the GD pin signal becomes high for a period of t (480 ns typ.), to ensure a high Signal to Noise Ratio (SNR). The FB pin capacitor C...
- Page 24 XDPL8218 design guide For high power factor flyback converter with constant voltage output Secondary-side regulation FB circuit design Based on the commonly used ceramic capacitor value which is near to the calculated C above, C = 470 pF is selected in this design example.
- Page 25 XDPL8218 design guide For high power factor flyback converter with constant voltage output Secondary-side regulation FB circuit design �� �������� −9 2 ∙ �� ∙470 ∙ 10 ∙ 5 �������������� �� = ��8 ��Ω �������� Design Guide 25 of 48 V 1.0...
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Page 26: Regulated Mode Parameters
Regulated mode parameters Regulated mode parameters In regulated mode, XDPL8218 supports multi-mode operation consisting of QRM1, Discontinuous Conduction Mode (DCM) without valley switching, and ABM. The mode of operation and switching parameters are selected mainly based on the digitally filtered FB voltage V mapping. -
Page 27: Abm Fb Voltage Sensing And Control
XDPL8218 design guide For high power factor flyback converter with constant voltage output Regulated mode parameters In QRM1 and DCM, the minimum on-time variable t ) is based on the t parameter or t on,min on,min on,min,V,out,sense variable, whichever is higher. The t... -
Page 28: Fb Voltage Mapping And Mode Transition
XDPL8218 design guide For high power factor flyback converter with constant voltage output Regulated mode parameters Table 7 Referring to , the recommended parameter configuration for ABM FB voltage sensing and control is selected in this design example. Table 7... -
Page 29: Fb Voltage Maximum Limit Ramp
XDPL8218 design guide For high power factor flyback converter with constant voltage output Regulated mode parameters The on-time ramp increases from t ) at V , until t ) is reached at V on,min FB,on on,max FB,max,map Note: ) and t... -
Page 30: Other Protection-Related Parameters
= 119°C is recommended and selected in this design example. critical Note: XDPL8218’s lifetime is not guaranteed when operating junction temperature is above 125°C, which is possible if T is configured above 119°C, with temperature sensing tolerance of ± 6°C. -
Page 31: Debug Mode
The parameter setting of Debug = Disabled is selected in this design example. The Debug parameter Mode Mode should only be enabled for debugging purposes. For more details on XDPL8218 debug mode, please refer to Section 19.2. Design Guide 31 of 48 V 1.0... -
Page 32: Pcb Layout Guide
XDPL8218 design guide For high power factor flyback converter with constant voltage output PCB layout guide PCB layout guide Minimize the circumference of the following high-current/high-frequency loop with traces which are short and wide (or with jumper wires which are short and thick). -
Page 33: Parameter Configuration List, Set-Up And Procedures
Parameter configuration list, set-up and procedures 17.1 Parameter configuration list Figure 21 shows the XDPL8218 parameter configuration list, with selected values based on the design examples from Section 2 Section 15. For another system design, the values in the list can be different. -
Page 34: Parameter Configuration Set-Up
Please ensure the board is not supplied with any voltage before connecting the programmable cable to the target XDPL8218 board. For parameter configuration on the XDPL8218 40 W reference design, please connect the programming cable to its configuration connector X2. -
Page 35: Parameter Configuration Procedures
GUI for parameter configuration. Alternatively, the following simple guide is also available for quick and easy reference. Open the XDPL8218 parameter configuration file (*.csv) from the default installation folder of the project add- on at C:\Users\<Username>\Infineon Technologies AG\.dp vision\Parameters, as shown in... - Page 36 IC. In that case, the user will have to replace the XDPL8218 chip with a new one in order to burn the configuration.
- Page 37 Test configuration − This function will download the parameter values from the list in .dp Vision into the XDPL8218 RAM, followed by an automatic IC start-up, for application testing with the new configuration. Unlike using the burn configuration, parameter configuration with this option is not permanent...
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Page 38: Fine-Tuning Guide
18.1 Input voltage-sensing parameter fine-tuning When the primary MOSFET is switched on, the XDPL8218 measures the current flowing out of the ZCD pin -I , to estimate the DC link filter capacitor voltage V... -
Page 39: Qr Valley Switching Parameter Fine-Tuning
Unlike conventional analog solutions which achieve QR valley switching by introducing an external hardware delay on the zero-crossing signal with the ZCD pin capacitor, the XDPL8218 ZCD pin capacitor is mainly used for noise filtering only. Therefore, a fixed capacitor value, e.g. 47 pF, can be used across designs of different power classes. - Page 40 For high power factor flyback converter with constant voltage output Fine-tuning guide parameter fine-tuning is, however, necessary to compensate for XDPL8218 internal propagation delay in ZCDPD ZCD and also external delay caused by the noise-filtering capacitor at the ZCD pin.
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Page 41: Input Power Quality Related Parameter Fine-Tuning
If necessary, fine-tune the C parameter using the test configuration function in .dp Vision, to achieve the optimized power factor and iTHD. For example with the XDPL8218 40W reference design, the initial C based on C is 0.22 ��F for powering up of the board, and fine-tuned C... -
Page 42: Debugging Guide
This scenario means a protection with auto-restart reaction has been triggered. It is recommended to activate the XDPL8218 debug mode for firmware status code read-out in this case, to know exactly which protection has been triggered. For more details on the XDPL8218 debug mode, please refer Section 19.2. - Page 43 Under Voltage Lockout (UVLO) protection has been triggered, which is likely caused by either one of the following: Issue(s) with V supply circuit or/and start-up related parameter. − Debug mode enabled, plus any protection triggering. For more details on the XDPL8218 debug mode, − please refer Section 19.2.
- Page 44 Figure This scenario means the configuration mode has likely been entered due to no parameter at start-up. To avoid this, please burn the first full set of parameters to the XDPL8218 chip. Figure 29 Scenario IV waveform example (configuration mode entered with no parameter at start- Scenario V: V stays constant at approximately 7.5 V and the UART pin signal stays mostly high (see an...
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Page 45: Firmware Status Code Read-Out Procedures With Debug Mode
Debugging guide 19.2 Firmware status code read-out procedures with debug mode For further debugging, the XDPL8218 debug mode can be activated to read out the firmware status code, to identify which protection has been triggered. Table 15 shows the recommended procedures for firmware status code read-out in debug mode. -
Page 46: References
XDPL8218 design guide For high power factor flyback converter with constant voltage output References References XDPL8218 datasheet [2] REF-XDPL8218-U40W engineering report Design Guide 46 of 48 V 1.0 2018-06-06... -
Page 47: Revision History
XDPL8218 design guide For high power factor flyback converter with constant voltage output References Revision history Document Date of release Description of changes version V 1.0 2018-06-06 Initial version Design Guide 47 of 48 V 1.0 2018-06-06... -
Page 48: Www.infineon.com/Xdpl8218
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