486Slc Cpu Cache Control; Technical Option Control - DIGITAL-LOGIC MICROSPACE PC/104 Technical User's Manual

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4.7.4

486SLC CPU CACHE Control

First 64k:
A000-F000:
A20M input:
486SLC Cache (KEN):
FLUSH input:
Flush Cache on Hold:
486SLC CPU Clockdoubler:
SUSPEND Pins:
RPL Pins:
Block 1 Starting Address:
Block 1 Size:
Block 2 Starting Address:
Block 2 Size:

4.7.5 Technical Option Control

DMA CLK Source Select:
Bus CLK Source Select:
Refresh CMD Width:
CPU clk Select (Procclk):
Parity Control:
Dynamic Memory Sizing:
DRAM Configuration:
Base RAM above 256K:
Extd. Memory Boundary:
Non-Cacheable
Non-Cacheable
Disabled
Disabled
Enabled
Disabled
50MHz (Cxin = 25MHz double )
Disabled
Disabled
000000
Disabled
000000
Disabled
6.25/5/4.16MHz
8.33MHz (Cxin 1/6)
280ns
25MHz = CPUX1
Disabled
Enabled
16MB(4x4M)
Enabled
No Boundary
29
MSM486V Manual V3.22
This Bit switches on the Cache.
This Bit switches on the clock doubler on the
TI486SXLC-2 .
Thereby an area can be possibly excluded.
Thereby an area can be possibly excluded.
Description