NXP Semiconductors RDE-1252 Reference Manual
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NXP Semiconductors RDE-1252 Reference Manual

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S32G-VNP-RDB3
Reference Manual
Version: 0.4
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  • Page 1 S32G-VNP-RDB3 Reference Manual Version: 0.4...

  • Page 2: Table Of Contents

    Contents Contents Tables Figures Introduction Acronyms and Abbreviations Related documentation Board Version S32G-VNP-RDB3 Specifications Hardware Resources Block diagram PCB specification S32G-VNP-RDB3 top view Connector Buttons Power Switch DIP Switch Jumpers 2.10 LEDs Functional Description Power supplies Boot Reset Clocks JTAG Aurora Trace External Memory and Storage 3.7.1...
  • Page 3 Ethernet 3.9.1 Ethernet switch 3.9.2 Ethernet PHY 3.9.3 SMI Interface 3.10 3.11 LIN and UART 3.12 FlexRay 3.13 DSPI 3.14 3.15 Cables Description Revision History...

  • Page 4: Tables

    Tables Table 1. Acronyms and abbreviations ................6 Table 2. Related documentation ................... 7 Table 3. S32G-VNP-RDB3 Board Version ..............8 Table 4. Hardware Resources ....................9 Table 5. S32G-VNP-RDB3 PCB Specifications ............11 Table 6. The connectors of S32G-VNP-RDB3............12 Table 7.

  • Page 5: Figures

    Figures Figure 1. The block diagram of S32G-VNP-RDB3 ............ 10 Figure 2. The top view of S32G-VNP-RDB3 ..............11 Figure 3. The power supply block diagram of S32G-VNP-RDB3 ...... 18 Figure 4. Boot mode pins ...................... 19 Figure 5. RCON pins ....................... 20 Figure 6.

  • Page 6: Introduction

    Introduction The S32G-VNP-RDB3 is a compact, highly-optimized and integrated reference design board featuring the S32G399A vehicle network processor. With its high-performance computing capacity and rich input/output(I/O), this board can provide reference for a variety of typical automotive applications, such as service-oriented gateway, high-performance central compute unit, safety controller for ADAS and autonomous driving, FOTA master controlling image download and distribution, black-box for vehicle data logging, security services and key management, smart antennas etc.

  • Page 7: Related Documentation

    Media Independent Interface PCBA Printed Circuit Board Assembly Packet Forwarding Engine Physical Layer RGMII Reduced General Media Independent Interface SerDes Serializer/Deserializer SGMII Serial Gigabit Media Independent Interface Serial Management Interface SPDT Single Pole Double Throw Solid State Drive Time Sensitive Network Universal serial bus uSDHC Ultra Secured Digital Host Controller...

  • Page 8: Board Version

    interfaces, chip features, and clock information. Provides information about S32G3 S32G3 Data Sheet electrical characteristics, and ordering information. Provides an overview of the S32G-VNP- S32G-VNP-RDB3 User Guide RDB3, and describes how to quickly bring up the board. Board Version The table below lists the board version of S32G-VNP-RDB3. For detailed revision information, please refer to the "Revision History"...

  • Page 9: S32G-Vnp-Rdb3 Specifications

    S32G-VNP-RDB3 Specifications This section describes the hardware resources, specifications, and mechanical information of S32G-VNP- RDB3. Hardware Resources The resources of S32G-VNP-RDB3 are listed as below. Table 4. Hardware Resources Items Resources Description 4 x Cortex-A53 LS (8 x Cortex-A53) 4 x Cortex-M7 LS 1 x Hardware Security Engine (HSE) S32G399A Processor...

  • Page 10: Block Diagram

    1 x 20PIN JTAG for S32G399A JTAG 1 x 10PIN JTAG for SJA1110A Aurora Trace 1 x AURORA Low-power Supports Low-power mode with DDR self-refresh mode Additional Features Supports internal RTC and on-board external RTC 1 x M.2 M-key slot M.2 slot 1 x M.2 E-key slot Expansion...

  • Page 11: Pcb Specification

    PCB specification The table below lists the PCB specifications of S32G-VNP-RDB3. Table 5. S32G-VNP-RDB3 PCB Specifications Items Specifications Ambient Temperature ~ 35° C, Lab environment PCB dimensions 180mm x 140mm S32G-VNP-RDB3 top view The figure below shows the top view of S32G-VNP-RDB3. Figure 2.

  • Page 12: Connector

    Connector The table below shows the connectors of S32G-VNP-RDB3 and their corresponding signals. For more details on the connector signals, please refer to schematic. Table 6. The connectors of S32G-VNP-RDB3 Part Connector type Description Typical connection USB 2.0 Micro-AB Console port (UART1) Connects to host computer.

  • Page 13: Buttons

    Supports PCIe x1 (Gen3, Gen2, PCIe x1 socket Connects to PCIe x1 EP device Gen1) Ethernet port with Magnetics for 1000BASE-T/ 100BASE-TX Dual-port connectivity Connects to RJ45 Ethernet cable RJ45 connector P2A(bottom) P2B(top) Ethernet port with Magnetics for 1000BASE-T/ 100BASE-TX Dual-port connectivity Connects to RJ45 Ethernet cable...

  • Page 14: Dip Switch

    If the SW15 is moved to POS. 1, the power supply is input from the Power Jack(J176) If the SW15 is moved to POS. 2, the board power supply is turned off. If the SW15 is moved to POS. 3, the power supply is input from the connector(J5-pin2) DIP Switch The table below describes the DIP switches of S32G-VNP-RDB3.

  • Page 15: Table 10. The Setting Of Boot Modes

    ON : S32G399A Parallel RCON[x+15] = 1, where x = 1d to 8d SW6[x] OFF: S32G399A Parallel RCON[x+15] = 0, where x = 1d to 8d ON : S32G399A Parallel RCON[x+23] = 1, where x = 1d to 8d SW7[x] OFF: S32G399A Parallel RCON[x+23] = 0, where x = 1d to 8d ON : Connects the S32G399A uSDHC interface to SD card.

  • Page 16: Jumpers

    ALL-OFF ALL-OFF ALL-OFF ALL-OFF ALL-OFF ALL-OFF ALL-OFF ALL-OFF 1-OFF, 2-OFF 1-OFF, 2-OFF 1-OFF, 2-OFF 1-OFF, 2-OFF SW10 1-ON, 2-OFF 1-ON, 2-OFF 1-ON, 2-OFF 1-OFF, 2-OFF Jumpers The table below describes the jumpers of S32G-VNP-RDB3. Table 11. Jumpers Part Type Default setting Description 1-2 Open : VR5510 enters normal mode after power on.(The VR5510 watchdog will be enabled)

  • Page 17: Leds

    1-2 Shorted J190 3 x 2 connector 3-4 Shorted J190 can be used for CAN PHY testing. 5-6 Shorted 1-2 Shorted J191 3 x 2 connector 3-4 Open J191 can be used for CAN PHY testing. 5-6 Shorted 1-2 Shorted J192 3 x 2 connector 3-4 Open...

  • Page 18: Functional Description

    Functional Description Power supplies The power supply of S32G-VNP-RDB3 is comprised of two parts: external 12V AC-DC power adapter and onboard PMIC. The specifications of the 12V AC-DC power adapter are as follows: • Input: 110-240V AC, 50/60 Hz • Output: 12 VDC, 6.67A, 80W MAX The figure below shows the S32G-VNP-RDB3 power supply block diagram.

  • Page 19: Boot

    Boot The BootROM of S32G399A is responsible for booting customer applications and the HSE_H FW. It supports Serial Boot, Boot from RCON, Boot from Fuses. Combined value of Boot mode pins, FUSE_SEL fuse status and Lifecycle control the boot mode .

  • Page 20: Figure 5. Rcon Pins

    1-OFF,2-ON BOOTMOD1 value=RESET_B 1-ON, 2-ON BOOTMOD1 value=INV_RESET_B 1-OFF,2-OFF BOOTMOD0 value=0 1-ON, 2-OFF BOOTMOD0 value=1 SW10 1-OFF,2-ON BOOTMOD0 value=RESET_B 1-ON, 2-ON BOOTMOD0 value=INV_RESET_B RCON uses up to 32 general-purpose I/O pins, RCON[0] to RCON[31]. They are latched on functional reset deassertion. RCON[31:0] pins corresponds bit by bit to values in the fuse word BOOT_CFG1[31:0]. Values of these pins will be sampled during S32G399A reset, and these pins can be used for other functions after boot (to be precise after the sample stage).

  • Page 21: Reset

    Reset S32G-VNP-RDB3 supports two kinds of reset: power-on reset and warm reset. Both could reset most of hardware components on board. Power-on reset will be initiated by depressing SW1 and self-triggered reset (warm reset) will be initiated by depressing SW2. Except for the entire board reset, the Ethernet switch and PHY can be individually reset by S32G399A GPIOs.

  • Page 22: Clocks

    Clocks The S32G399A has multiple clock sources including FIRC, SIRC, FXOSC. They can be selected to drive clock of system peripherals, cores, and infrastructure. S32G-VNP-RDB3 uses a 40 MHz crystal oscillator as FXOSC. FIRC and SIRC are internal clocks on chip. The figure below shows the Clock Tree of S32G-VNP-RDB3.

  • Page 23: Jtag

    JTAG JTAG debug is supported by direct connection to the header connector J48. Users can connect a dedicated debugger, such as Lauterbach or S32 Debug Probe. On the S32G-VNP-RDB3, the 20-pin JTAG header connector carries JTAG signals and the additional signals for S32G399A debugging, and the 10-pin JTAG header connector carries JTAG signals for SJA1110 debugging.

  • Page 24: Nor Flash

    CKE_A[0:1] 1.1V S32G399A LPDDR4 CLK_A_P, CLK_A_N CDT_CA_A CS_A[0:1] CDT_CA_B CA_A[0:5] DMI_A[0:1] 1.8V DQS[0:1]_A_P, DQS[0:1]_A_N VDD1 DQ_A[0:15] DDR_RESET DDR subsystem CKE_B[0:1] 1.1V CLK_B_P, CLK_B_N VDD2 CS_B[0:1] VDDQ CA_B[0:5] 1.1V DMI_B[0:1] DQS[0:1]_B_P, DQS[0:1]_B_N DQ_B[0:15] Figure 8. The connection of LPDDR4 SDRAM 3.7.2 NOR flash The S32G399A QuadSPI module provides a common interface to single, dual, and octal NOR flash memory, including Hyperflash memory.

  • Page 25: Sd/Emmc

    3.7.3 SD/eMMC On S32G-VNP-RDB3, SD card interface and eMMC are connected to the S32G399A uSDHC module with a multiplexed logic. The uSDHC module acts as a bridge, passing host bus transactions to the SD/eMMC cards by sending commands and performing data accesses to/from the cards. The figure below shows the connection between the S32G399A and SD/eMMC.

  • Page 26: Serdes Interface

    SerDes Interface The S32G399A has two SerDes instances, and each instance supports two lanes. The S32G-VNP-RDB3 supports both SGMII and PCI Express high-speed serial communication interfaces. The figure below shows the SerDes routing diagram of S32G-VNP-RDB3. SW8 = ON S32G399A PCIe X1 SerDes1 Lan0 •...
  • Page 27 SerDes0 SJA1110 PORT1 SerDes1 PCIe X1 socket (P1) SJA1110 PORT4 SerDes0 SJA1110 PORT1 SerDes1 AQR113C SerDes0 SJA1110 PORT1/NA SJA1110 PORT4 SerDes1 PCIe X1 socket (P1) SerDes0 SJA1110 PORT1/NA SJA1110 PORT4...

  • Page 28: Ethernet

    Ethernet The GMAC and PFE of the S32G399A enables a host application to transmit and receive data over an Ethernet network in compliance with IEEE 802.3-2015, and the PFE of S32G399A additionally offloads the processing of Ethernet packets from the host cores, yielding higher performance and lower power than pure software processing can achieve.

  • Page 29: Ethernet Switch

    3.9.1 Ethernet switch The SJA1110 is a firmware based automotive ethernet switch, with an embedded ARM Cortex-M7 core. It has a SPI interface which is used to communicate with S32G399A. Apart from the SPI_HOST, it also contains the SPI_PER interface which can operate as a SPI master for access to other SPI slaves or as a SPI slave to enable inter-processor communication applications.

  • Page 30: Smi Interface

    AR8035 SJA1110 Port2 RGMII 1000BASE-T KSZ9031 S32G399A PFE_MAC2 RGMII 1000BASE-T KSZ9031 S32G399A GMAC0 RGMII 1000BASE-T AQR113C supports multiple speed operation modes. AQR113C S32G399A PFE_MAC1 SGMII For more details, please refer to chapter SerDes Interface. 1. The PHY inside SJA1110 is not included in this table. 3.9.3 SMI Interface The table below describes the SMI Interfaces of S32G-VNP-RDB3.
  • Page 31 U43 S32G399A PC_11 LLCE_CAN0_RXD U24 PCAL6524HEAZ P0_1 LLCE_CAN01_EN U24 PCAL6524HEAZ P0_0 LLCE_CAN01_STB U43 S32G399A PJ_01 LLCE_CAN1_TXD U43 S32G399A PJ_02 LLCE_CAN1_RXD TJA1043 U24 PCAL6524HEAZ P0_1 LLCE_CAN01_EN U24 PCAL6524HEAZ P0_0 LLCE_CAN01_STB U43 S32G399A PJ_03 LLCE_CAN2_TXD U43 S32G399A PJ_04 LLCE_CAN2_RXD TJA1043 U24 PCAL6524HEAZ P0_3 LLCE_CAN2_EN U24 PCAL6524HEAZ...
  • Page 32 U43 S32G399A PJ_13 LLCE_CAN7_TXD U43 S32G399A PJ_14 LLCE_CAN7_RXD TJA1153 U24 PCAL6524HEAZ P1_1 LLCE_CAN67_EN U24 PCAL6524HEAZ P1_0 LLCE_CAN67_STB U43 S32G399A PK_03 LLCE_CAN10_TXD U43 S32G399A PK_04 LLCE_CAN10_RXD TJA1043 U24 PCAL6524HEAZ P1_5 LLCE_CANAB_EN U24 PCAL6524HEAZ P1_4 LLCE_CANAB_STB U43 S32G399A PK_05 LLCE_CAN11_TXD U43 S32G399A PK_06 LLCE_CAN11_RXD TJA1043...
  • Page 33 U24 PCAL6524HEAZ P2_0 LLCE_CANEF_STB U43 S32G399A PJ_07 LLCE_CAN4_TXD U43 S32G399A PJ_08 LLCE_CAN4_RXD TJA1153 U24 PCAL6524HEAZ P0_7 LLCE_CAN45_EN U24 PCAL6524HEAZ P0_6 LLCE_CAN45_STB U43 S32G399A PJ_09 LLCE_CAN5_TXD U43 S32G399A PJ_10 LLCE_CAN5_RXD TJA1153 U24 PCAL6524HEAZ P0_7 LLCE_CAN45_EN U24 PCAL6524HEAZ P0_6 LLCE_CAN45_STB U43 S32G399A PJ_15 LLCE_CAN8_TXD U43 S32G399A...

  • Page 34: Lin And Uart

    U24 PCAL6524HEAZ P1_7 LLCE_CANCD_EN U24 PCAL6524HEAZ P1_6 LLCE_CANCD_STB U43 S32G399A PK_09 LLCE_CAN13_TXD U43 S32G399A PK_10 LLCE_CAN13_RXD TJA1463 U24 PCAL6524HEAZ P1_7 LLCE_CANCD_EN U24 PCAL6524HEAZ P1_6 LLCE_CANCD_STB U43 S32G399A PB_01 FLEX_CAN0_TXD U43 S32G399A PB_02 FLEX_CAN0_RXD TJA1043 U24 PCAL6524HEAZ P2_3 FLEX_CAN0_EN U24 PCAL6524HEAZ P2_2 FLEX_CAN0_STB U43 S32G399A...

  • Page 35: Flexray

    PA_13 UART1 FT232RQ PB_00 TXD1 PK_15 LLCE_LIN0 (Master mode) RXD1 PL_00 TXD2 PC_08 LLCE_LIN1 (Master mode) RXD2 PC_04 TJA1024 (REV E) TXD3 PC_05 TJA1124 (REVF) LLCE_LIN2 (Master mode) RXD3 PC_06 TXD4 PC_07 LLCE_LIN3 (Master mode) RXD4 PL_07 PB_11 U100 FLEX_LIN2 (Slave mode) TJA1021T PB_12 3.12...

  • Page 36: Dspi

    U24 PCAL6524HEAZ P2_7 EIO_FR_EN_A 3.13 DSPI The table below describes the DSPI connections on the S32G-VNP-RDB3. Table 22. DSPI Connections Interface S32G399A Port Connection SOUT PA_06 Connects to J5. (SW11[1] = OFF) PF_15 Connects to J5. (SW11[1] = OFF) DSPI1 PA_08 Connects to J5.

  • Page 37: Usb

    PCIe x1 socket PCAL6524HEAZ 0100010R/W, 0x22 U137 PCT2075 1001000R/W, 0x48 Main : 0100000R/W, 0x20 VR5510 Safety: 0100001R/W, 0x21 PFS5600 0011000R/W, 0x18 PF5300 0101000R/W, 0x28 I2C4_SDA PC_01 I2C4_SCL PC_02 U108 PF5020 0001000R/W, 0x08 PF5020 0001001R/W, 0x09 U136 INA231 1000000R/W, 0x40 I2C2_SCL PB_05 Connector I2C2_SDA PB_06 3.15...

  • Page 38: Cables Description

    CLKOUT PL_08 Cables Description The table below describes the Cable of Connector J6. Table 25. J6 Cable Signal Cable color connector connector Cable color Signal FlexRay_BP Blue White FlexRay_BM FlexCAN0_H Green White FlexCAN0_L FlexCAN1_H Green White FlexCAN1_L LLCE_CAN0_H Yellow White LLCE_CAN0_L LLCE_CAN1_H Yellow...

  • Page 39: Table 26. J5 Cable

    LLCE_CAN13_H Yellow White LLCE_CAN13_L LLCE_CAN14_H Yellow White LLCE_CAN14_L LLCE_CAN15_H Yellow White LLCE_CAN15_L Black Black The table below describes the Cable of Connector J5. Table 26. J5 Cable Signal Cable color connector connector Cable color Signal Orange 12_VIN 5V_OUT Orange Orange 12V_OUT 3V3_OUT Black...

  • Page 40: Table 27. J53 Cable

    Green Green ADC_IN1 ADC_IN2 Green Green ADC_IN3 ADC_IN4 The table below describes the Cable of Connector J53. Table 27. J53 Cable Connector Signal Cable color White 100Base-T1 TRX6 Yellow White 100Base-T1 TRX9 Yellow White 100Base-T1 TRX5 Yellow White 100Base-T1 TRX7...
  • Page 41 Yellow White 100Base-T1 TRX8 Yellow White 100Base-T1 TRX10 Yellow...

  • Page 42: Revision History

    Revision History Date Version Description 28 Dec 2021 Revised Initial Draft 14 Jan 2022 Updated format and grammar. 21 Jan 2022 Updated format and grammar. • In section "Board Version": − Added description "For detailed revision information, please refer to..." −...
  • Page 43 Disclaimer Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein.

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