NXP Semiconductors RW61 Series Design Manual
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NXP Semiconductors RW61 Series Design Manual

NXP Semiconductors RW61 Series Design Manual

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AN14002
RW61x Design Guide
Rev. 3.0 — 20 March 2025
Document information
Information
Keywords
Abstract
Content
Power supply, clock source, reset, host interface, RF interface, PCB layout, PCB stack-up,
reference design, evaluation board (EVB)
Provides design guidelines for RW61x.
Application note

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Summary of Contents for NXP Semiconductors RW61 Series

  • Page 1 AN14002 RW61x Design Guide Rev. 3.0 — 20 March 2025 Application note Document information Information Content Keywords Power supply, clock source, reset, host interface, RF interface, PCB layout, PCB stack-up, reference design, evaluation board (EVB) Abstract Provides design guidelines for RW61x.

  • Page 2: Overview

    AN14002 NXP Semiconductors RW61x Design Guide 1 Overview This document provides design guidelines for the RW61x device. The RW61x is a highly integrated, low-power tri-radio Wireless MCU with an integrated MCU and Wi-Fi 6 + Bluetooth Low Energy (LE)/802.15.4 radios.
  • Page 3 AN14002 NXP Semiconductors RW61x Design Guide Figure 2 shows RW612 block diagram for the dual antenna configuration. FlexSPI (Quad) Applications System Security/ Peripherals memory encryption Flexcomm Ethernet Antenna RMII Wi-Fi 5 GHz Wi-Fi 5 GHz Tx Tx/Rx SPDT SDIO 3.0...

  • Page 4: Power Supply

    AN14002 NXP Semiconductors RW61x Design Guide 2 Power supply 2.1 Overview Table 1 lists RW61x power supply pins and respective voltage values. Table 1. Power supply pins Supply Description Typical value (V) VCORE Core power supply 1.05 VIO, VIO_SD Digital I/O power supply 1.8 or 3.3...

  • Page 5: Vbat

    AN14002 NXP Semiconductors RW61x Design Guide 2.3 VBAT VBAT is the power supply to the internal buck regulators. Decoupling capacitors are required for the VBAT supply pin. The capacitor values are 0.1 µF and 22 µF. The 0.1 µF capacitors must be placed as close to VBAT pins as possible.

  • Page 6: Internal Buck Regulator Guidelines

    AN14002 NXP Semiconductors RW61x Design Guide 2.4 Internal buck regulator guidelines The internal buck regulators supply AVDD18 and VCORE pins. Figure 5 shows a simplified BGA application circuit for AVDD18 and VCORE supply using internal buck regulators. Figure 5. Application circuit for AVDD18 and VCORE - TFBGA package Table 3 shows the 11V_iBUCK and 18_iBUCK components.

  • Page 7: Vcore

    AN14002 NXP Semiconductors RW61x Design Guide 2.5 VCORE To avoid false glitch detect, and to reduce noise coupling and ripples, the capacitors are placed on each VCORE pin. Figure 6 shows 470 pF capacitors (C117, C287, C124, and C292) placed on VCORE pins on BGA package.

  • Page 8: Vpa

    AN14002 NXP Semiconductors RW61x Design Guide 2.6 VPA VPA is the power supply to the internal Wi-Fi PA. Decoupling capacitors are required for the VPA supply pin. The capacitor values are 10 µF and 100 pF. The 100 pF capacitors must be placed as close to VPA pins as possible.

  • Page 9: Avdd18

    AN14002 NXP Semiconductors RW61x Design Guide 2.7 AVDD18 Each AVDD18 supply pin requires one capacitor unless stated otherwise. Refer to the NXP reference design for details. Figure 8 shows the typical circuit of AVDD18 supply pins. Figure 8. Circuit for AVDD18 supply pins Table 6 shows AVDD18 components.

  • Page 10: Vio

    AN14002 NXP Semiconductors RW61x Design Guide Table 8 shows the components of AVDD18 supply pin with RC filter. Table 8. Components of AVDD18 supply pin with RC filter Component Manufacturer Part number Series resistor R = 0 ohm (0402) CYNTEC PFR05S-000-XNH Decoupling capacitor C = 0.1 µF (0201)

  • Page 11: Power-Up Sequence

    AN14002 NXP Semiconductors RW61x Design Guide 2.9 Power-up sequence Refer to the section Power-up sequence in RW61x data sheets and [2]. Make sure the PDn (power down) is deasserted after all external power supplies are up. 2.10 PCB layout guidelines Refer to the following PCB layout guidelines for power supply: •...
  • Page 12 AN14002 NXP Semiconductors RW61x Design Guide • The power from source to power pin must go through the decoupling network before connecting to the power pin as shown in Figure Power VIA GND VIA GND VIA WLCSP bump WLCSP bump...
  • Page 13 AN14002 NXP Semiconductors RW61x Design Guide • Ensure the current return path/loop is as small as possible. The current loop consists of BUCK18_VOUT, inductor, capacitor, and ground pins. Figure 14 shows the buck input ground loop Figure 14. Buck input ground loop Figure 15 shows the buck output ground loop.

  • Page 14: Rf Interface

    AN14002 NXP Semiconductors RW61x Design Guide 3 RF interface NXP reference designs for the Wireless SoC show the front-end configurations currently supported by NXP. Discuss your desired front-end configuration with your NXP representative and have your design reviewed by NXP.
  • Page 15 AN14002 NXP Semiconductors RW61x Design Guide Figure 17 shows the typical circuit diagram for a two-antenna design without antenna diversity. Figure 17. Circuit diagram for dual-antenna configuration without antenna diversity Table 10 lists the recommended RF front-end components for two-antenna without diversity.

  • Page 16: Single Antenna Rf Front-End

    AN14002 NXP Semiconductors RW61x Design Guide 3.1.2 Single antenna RF front-end Figure 18 shows the typical front-end topology for a single-antenna application. An external SPDT switch is required to select either 2.4 GHz Wi-Fi or Bluetooth LE/802.15.4 transmit/receive paths. Use discrete low-pass filters (LPF) to ensure the rejection of out of band emissions.
  • Page 17 AN14002 NXP Semiconductors RW61x Design Guide Table 11 lists the recommended RF front-end components for a single antenna design. Table 11. RF front-end components for single antenna designs RF component Manufacturer Part number Diplexer DPX165950DT-8085D1 Discrete LPF on Wi-Fi 5 GHz path —...

  • Page 18: Single Antenna Rf Front-End With Antenna Diversity

    AN14002 NXP Semiconductors RW61x Design Guide 3.1.3 Single antenna RF front-end with antenna diversity Figure 20 shows the typical RF front-end topology for a single antenna design with antenna diversity. Two external SPDT switches are required to switch Wi-Fi and Bluetooth LE/802.15.4 paths. Use discrete low-pass filters (LPF) to ensure the rejection of out-of-band emissions.
  • Page 19 AN14002 NXP Semiconductors RW61x Design Guide Table 12 lists the recommended RF front-end components for a single antenna design with antenna diversity. Table 12. RF front-end components for single-antenna design with antenna diversity RF component Manufacturer Part number Diplexer DPX165950DT-8085D1 Discrete LPF on Wi-Fi 5 GHz path —...

  • Page 20: Rf Front-End For Wlcsp Package

    AN14002 NXP Semiconductors RW61x Design Guide 3.2 RF front-end for WLCSP package RF front-end for the WLCSP package is the same as for the TFBGA package. Note: For optimized PCB design, NXP RW61x EVB for WLCSP package uses a different diplexer pinout than TFBGA design.

  • Page 21: Pcb Layout Guidelines

    AN14002 NXP Semiconductors RW61x Design Guide 3.3 PCB layout guidelines Refer to the following PCB layout guidelines for RF interface: • Route the RF signals on the top layer (micro strip) with 50 ohm impedance. • Reference the RF signals to a solid ground plane.
  • Page 22 AN14002 NXP Semiconductors RW61x Design Guide • Keep the RF control signal traces as far away as possible from the RF traces. • Follow the recommendations of the manufacturer for RF front-end parts. For example, add ground vias close to the ground pin of the front-end part.
  • Page 23 AN14002 NXP Semiconductors RW61x Design Guide • For HVQFN package only, add an EPAD ground under the package for thermal relief as shown in Figure • Make sure that the GND EPAD has multiple thermal vias for the thermal relief path to be effective.

  • Page 24: Clock Source

    AN14002 NXP Semiconductors RW61x Design Guide 4 Clock source RW61x requires a reference clock input for its operation. The reference clock can be sourced from either an external crystal or external oscillator. 4.1 Crystal In a typical application, a 40 MHz crystal is used as a reference clock. Select a crystal with the following characteristics: •...

  • Page 25: Pcb Layout Guidelines For The Crystal

    AN14002 NXP Semiconductors RW61x Design Guide 4.1.1 PCB layout guidelines for the crystal • Place the crystal close to the Wireless SoC. • Keep the crystal away from the RF traces and high frequency signal traces such as SDIO, UART, and SPI interface signals, using the ground as a shield.

  • Page 26: External Oscillator

    AN14002 NXP Semiconductors RW61x Design Guide 4.2 External oscillator Figure 32 shows the typical application circuit for an external oscillator. External oscillator 1.8 V XTAL_IN Bypass capacitor Wireless SoC XTAL_OUT 100 Ω aaa-052160 Figure 32. Application circuit for external oscillator An external 40 MHz external oscillator can be used as a reference clock source. The clock input can be clipped sinusoidal or square wave.

  • Page 27: Reset

    AN14002 NXP Semiconductors RW61x Design Guide 5 Reset 5.1 Reset overview The PDn signal is used to reset RW61x device. One GPIO on the host device can be used to control the PDn pin. On the NXP reference design, the PDn signal is pulled up to an external voltage level between 1.75 V and 3.63 V.

  • Page 28: Pcb Layout Guidelines

    AN14002 NXP Semiconductors RW61x Design Guide Figure 33. Configuration pins Note: VIO_3 is always ON (AON) and supplied with external 1.8 V or 3.3 V. 5.3 PCB layout guidelines • To avoid EMI affecting the reset signal, do not route the PDn signal next to a large switching signal or on the edge of the PCB.

  • Page 29: Memory

    AN14002 NXP Semiconductors RW61x Design Guide 6 Memory The FlexSPI module supports all flash memories that are JESD216 standard compliant. Refer to the data sheet of the memory part to ensure it is compatible. 6.1 FlexSPI flash FlexSPI is a flexible serial peripheral interface between the external flash and MCU. RW61x supports a FlexSPI flash memory size up to 1 Gbit.

  • Page 30: Usb Otg

    AN14002 NXP Semiconductors RW61x Design Guide 7 USB OTG For full OTG support, USB_VBUS and USB_ID pins are required. USB_VBUS is a detection pin powered by a 5 V input (to bypass external VBAT power draw). For standard USB host/device mode, USB_VBUS is configured to bypass detection. USB_VBUS is left unconnected.

  • Page 31: Minimum Bill Of Materials

    AN14002 NXP Semiconductors RW61x Design Guide 8 Minimum bill of materials NXP EVB is designed for RW61x performance evaluation and software development. The minimum bill of materials provides an optimized component count while maintaining the optimal RF performance and being a cost-effective design.

  • Page 32: Miscellaneous

    AN14002 NXP Semiconductors RW61x Design Guide 9 Miscellaneous 9.1 Unused interfaces and pins Table 17. Unused interfaces and pins Pin name PCB connection when not used XTAL_OUT Connect a 100 Ω resistor to ground RF_TR_2 Connect a 50 Ω resistor to ground RF_TR_5 Connect a 50 Ω...

  • Page 33: Gpios

    AN14002 NXP Semiconductors RW61x Design Guide 9.2 GPIOs For the typical alternate functions assigned to the GPIO pins, refer to the RW61x data sheets and [2]. If the GPIO pins are not used, keep them unconnected. Table 18 shows GPIO assignments for Flexcomm functions.
  • Page 34 AN14002 NXP Semiconductors RW61x Design Guide Table 18. GPIO assignments for Flexcomm functions Pin name Flexcomm function Ethernet GPIO # Flexcomm # USART SDIO RMII I/F USART_CTS — — SPI_CS — — USART_RXD I2C_SDA I2S_DAT SPI_MOSI — — USART_TXD I2C_SCL I2S_WS SPI_MISO —...
  • Page 35 AN14002 NXP Semiconductors RW61x Design Guide Table 18. GPIO assignments for Flexcomm functions ...continued Pin name Flexcomm function Ethernet GPIO # Flexcomm # USART SDIO RMII I/F USART_RXD I2C_SDA I2S_DAT SPI_MOSI — ENET_TIMER2 USART_CLK I2S_CLK SPI_CLK — ENET_CLK USART_TXD I2C_SCL I2S_WS SPI_MISO —...

  • Page 36: Pcb Stack-Up

    AN14002 NXP Semiconductors RW61x Design Guide 9.3 PCB stack-up • Ensure the stack-up is symmetrical. • Ensure that all layers meet specified thickness. • For TFBAG and WLCSP packages, the NXP reference design PCB typically consists of six layers with FR4 material and blind buried vias.

  • Page 37: Design Review Rules

    AN14002 NXP Semiconductors RW61x Design Guide 9.4 Design review rules To discuss design options and schedule a design review, contact your NXP representative. For a design review, follow these rules: • File format for the schematic: PDF • File format for the layout: PADs or Allegro •...

  • Page 38: Debug Interface

    AN14002 NXP Semiconductors RW61x Design Guide 10 Debug interface Serial wire debug (SWD) is the debug interface designed specifically for the micro debugging of processors. Joint test action group (JTAG) is designed for device and board testing. The JTAG/SWD pins are multiplexed with other digital I/O pins. On reset, the pins assume the SWD functions by default.

  • Page 39: References

    AN14002 NXP Semiconductors RW61x Design Guide 11 References Data sheet – RW610: Wireless MCU with Integrated Wi-Fi 6 and Bluetooth Low Energy (link) Data sheet – RW612: Wireless MCU with Integrated Tri-radio Wi-Fi 6 + Bluetooth Low Energy / 802.15.4 –...

  • Page 40: Revision History

    AN14002 NXP Semiconductors RW61x Design Guide 12 Revision history Revision history Date Description AN14003 v.3.0 20 March 2025 • Section 9.2 "GPIOs": added GPIO[18] and corrected GPIO[22]. AN14002 v.2.0 1 November 2024 • Changed the access to public. No changes in the content.

  • Page 41: Legal Information

    NXP Semiconductors. In the event that customer uses the product for design-in and use in In no event shall NXP Semiconductors be liable for any indirect, incidental, automotive applications to automotive specifications and standards, punitive, special or consequential damages (including - without limitation - customer (a) shall use the product without NXP Semiconductors’...
  • Page 42 AN14002 NXP Semiconductors RW61x Design Guide Bluetooth — the Bluetooth wordmark and logos are registered trademarks owned by Bluetooth SIG, Inc. and any use of such marks by NXP Semiconductors is under license. AN14002 All information provided in this document is subject to legal disclaimers.
  • Page 43 AN14002 NXP Semiconductors RW61x Design Guide Tables Tab. 1. Power supply pins ..........4 Tab. 12. RF front-end components for single- Tab. 2. VBAT components ..........5 antenna design with antenna diversity .... 19 Tab. 3. Internal regulator components ......6 Tab. 13.
  • Page 44 AN14002 NXP Semiconductors RW61x Design Guide Figures Fig. 1. RW610 block diagram - Dual antenna Fig. 18. Front-end diagram for single-antenna configuration ............2 application ............16 Fig. 2. RW612 block diagram - Dual antenna Fig. 19. Circuit diagram for single-antenna design ..16 configuration ............

  • Page 45: Table Of Contents

    AN14002 NXP Semiconductors RW61x Design Guide Contents Overview ............2 Power supply ........... 4 Overview ............4 Topology .............4 VBAT ..............5 Internal buck regulator guidelines ......6 VCORE .............. 7 VPA ..............8 AVDD18 ............. 9 VIO ..............10 Power-up sequence .........11 2.10...

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