Quectel AF51Y Hardware Design page 22

The following figure shows the PCIe interface connection between AF51Y and the host.
HOST
In order to ensure the signal integrity of PCIe interface, C3 and C4 should be placed close to the host
module, and C5 and C6 should be placed close to the AF51Y module. The extra stubs of traces must be
as short as possible. A couple of 100 nF capacitors (C1/C2) must be added when the host is I.MX serial,
because the differential clock of I.MX serial does not meet PCIe compliance standard.
The following principles of PCIe interface design should be complied with, to meet PCIe Gen2
specifications.
⚫
It is important to route the PCIe signal traces as differential pairs with total grounding. And the
differential impedance is 100 Ω ±10 %.
⚫
For PCIe signal traces, the maximum length of each differential data pair
(PCIE_TX/PCIE_RX/PCIE_REFCLK) is recommended to be less than 300 mm, and each differential
data pair matching should be less than 0.7 mm (5 ps).
⚫
Spacing to all other signals (inter-interface) is four times of trace width.
⚫
Do not route signal traces under crystals, oscillators, magnetic devices, or RF signal traces. It is
important to route the PCIe differential traces in inner-layer of the PCB and surround the traces with
ground on that layer and with ground planes above and below.
AF51Y_Hardware_Design
R1
100K
PCIE_CLKREQ
PCIE_WAKE
PCIE_RST_N
PCIE_REFCLK_P
PCIE_REFCLK_M
C3
100 nF
PCIE_TX0_M
C4
100 nF
PCIE_TX0_P
PCIE_RX0_M
PCIE_RX0_P
Figure 5: PCIe Interface Connection
Wi-Fi&Bluetooth Module Series
VDD_EXT
R2 R3
100K NM_100K
PCIE_CLKREQ_N
PCIE_WAKE_N
PCIE_RST_N
C1
100 nF
PCIE_REFCLK_P
C2
100 nF
PCIE_REFCLK_M
PCIE_RX_M
PCIE_RX_P
C5
100 nF
PCIE_TX_M
C6
100 nF
PCIE_TX_P
AF51Y
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