Quectel AF51Y Hardware Design page 17

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Pin Name
WLAN_EN
PCIE_REFCLK_P
PCIE_REFCLK_M
PCIE_TX_P
PCIE_TX_M
PCIE_RX_P
PCIE_RX_M
PCIE_CLKREQ_N
PCIE_RST_N
PCIE_WAKE_N
WLAN_DBG_TXD
WLAN_DBG_RXD
Bluetooth Interface
Pin Name
BT_EN
PCM_DIN*
PCM_SYNC*
PCM_CLK*
PCM_DOUT*
BT_RTS
BT_CTS
BT_TXD
AF51Y_Hardware_Design
Pin No.
I/O
Description
84
DI
WLAN enable control
PCIe reference clock
54
AI
(+)
PCIe reference clock
9
AI
(-)
52
AO
PCIe transmit (+)
7
AO
PCIe transmit (-)
56
AI
PCIe receive (+)
11
AI
PCIe receive (-)
12
DO
PCIe clock request
14
DI
PCIe reset
13
DO
PCIe wakes up host
WLAN debug UART
21
DO
transmit
WLAN debug UART
65
DI
receive
Pin No.
I/O
Description
Bluetooth enable
83
DI
control
76
DI
PCM data input
35
DI
PCM data frame sync
37
DI
PCM clock
36
DO
PCM data output
Bluetooth UART
77
DO
request to send
Bluetooth UART clear
38
DI
to send
Bluetooth UART
39
DO
transmit
Wi-Fi&Bluetooth Module Series
Comment
1.8 V power domain.
Active high.
Require differential impedance
of 100 Ω.
1.8 V power domain
1.8 V power domain
1.8 V power domain
1.8 V power domain.
If unused, keep this pin open.
Comment
1.8 V power domain.
Active high.
1.8 V power domain
1.8 V power domain
1.8 V power domain
1.8 V power domain
1.8 V power domain
1.8 V power domain
1.8 V power domain
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