Coexistence Interfaces; Uart Coexistence Interface; Wlan_Slp_Clk Interface - Quectel AF51Y Hardware Design

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3.8. Coexistence Interfaces

3.8.1. UART Coexistence Interface

Table 12: Pin Definition of UART Coexistence Interface
Pin Name
Pin No.
COEX_TXD
59
COEX_RXD
16
AF51Y module supports LTE & WLAN coexistence and LTE & Bluetooth coexistence. The following figure
shows the UART coexistence interface connection between AF51Y and AG52xR series and AG55xQ
series modules.
AF51Y
3.9. WLAN_SLP_CLK
An external 32.768 kHz sleep clock connecting to WLAN_SLP_CLK is necessary. AF51Y is unable to
boot up and work without sleep clock.
Table 13: Pin Definition of WLAN_SLP_CLK Interface
Pin Name
Pin No.
WLAN_SLP_CLK 15
AF51Y_Hardware_Design
I/O
Description
LTE & WLAN & Bluetooth coexistence
DO
transmit
LTE & WLAN & Bluetooth coexistence
DI
receive
COEX_TXD
COEX_RXD
Figure 9: UART Coexistence Interface Connection
Interface*
I/O
Description
DI
External 32.768 kHz sleep clock input
Wi-Fi&Bluetooth Module Series
Comment
If unused, keep this pin
open.
If unused, keep this pin
open.
COEX_UART_RXD
HOST
COEX_UART_TXD
Comment
1.8 V power domain
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