AMD 780G User Manual page 30

3-6-1 DRAM Configuration
(CASL) CAS # Latency
DRAM Command Rate
RAS to RAS R/W Delay (tRTC)
CKE base Power down Mode
CKE based powerdom
Memclock tri-stating
Memory Hole Remapping
Auto Optimize Bottom IO
*Bottom of {31:24}IO
Bottom of UMA DRAM [31:24] IO Space
DDRII Timing Item
* Tw Tr Command delay
* Trfc 0 for DIMM 0
* Trfc 1 for DIMM 1
* Trfc 2 for DIMM 2
* Trfc 3 for DIMM 3
(Trtp) precharge Time
(Trcd)Row cycle Time
(Trcd)RAS to ras Delay (Trrd)
(Tras)Minium RAS Active Time
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values
CAS # Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: Auto,3, 4 and 5.
RAS-to-CAS Delay
This field let's you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow gives
more stable performance. This field applies only when synchronous DRAM is installed in
the system.
Row Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast
gives faster performance; and Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system.
Phoenix – AwardBIOS CMOS Setup Utility
DRAM Configuration
F6:Fail-safe Defaults
Auto
2T
Auto
Enabled
per channel
Disabled
Eabled
Enabled
EO
FO
Disabled
3 bus clock
75ns
75ns
75ns
75ns
3 clocks
26 bus clocks
6clocks
18 busclock
F7:Optimized Defaults
26
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