Analog Devices EVAL-ADMV8505 User Manual page 7

User Guide
EVALUATION BOARD SOFTWARE
Table 1. ADMV8505 Chip Plug-In Label Functions (See
Label Function
D
The displayed block diagram section shows the capacitor codes for the filter. While in SPI Write mode, any changes to the WR registers automatically triggers
a read operation of the READBACK registers, so that this section always reflects the actual hardware.
E
The Filter Settings section shows several controls for configuring the filter. Depending upon if INTERPOLATE is enabled, various controls can be visible.
When INTERPOLATE is enabled (as shown
FC_LOAD Value: this numeric up and down box (0 to 255) is used to set the desired center frequency value. Note that this is a unitless quantity, where a 0
corresponds to the lowest center frequency, and 255 corresponds to the highest center frequency.
Requested FC: enter in a requested center frequency in this text box. The value entered is used to compute the closest FC_LOAD Value for that frequency of
operation.
Anticipated FC: this text box is an estimation of the operating center frequency based upon the FC_LOAD Value.
INTERPOLATE: this check box enables the interpolation functionality on the chip.
When INTERPOLATE is disabled (not shown in
FC_LOAD Value: this numeric up and down box (0 to 255) is used to set the desired center frequency capacitor code.
BW_LOAD Value: this numeric up and down box (0 to 255) is used to set the desired bandwidth capacitor code.
MATCH_LOAD Value: this numeric up and down box (0 to 255) is used to set the desired input and output match capacitor code.
INTERPOLATE: this check box enables the interpolation functionality on the chip.
READBACK Values to Filter Settings: this button is available when interpolation is disabled. Click this button to populate the read back values from the
hardware into the FC_LOAD, BW_LOAD, and MATCH_LOAD values.
F
The Display section determines the actively selected SPI write or LUT number. This section includes the following:
Mode: use the drop-down menu to select either write or LUT display mode. When the display mode is set to write, then the Filter Settings section updates the
WR registers.
LUT: when the Mode is set to LUT, scroll up and down to set the LUT number (0 to 31) that is currently being configured and displayed in the Filter Settings
section. Changing to the LUT number automatically changes the Mode to LUT.
G
Use the Logic Pins section to toggle the SDP-S logic pins, which are connected to the logic pins on the ADMV8505 chip. This section includes the following:
RSTB: clear the check box to bring the ADMV8505 RST pin low, which holds the chip in reset. Select the check box again to bring the chip out of reset.
SFL: select the check box to bring the ADMV8505 SFL pin high, which places the chip in SFL mode. This action also toggles the on-board
switch connected to the ADMV8505 CS pin (see
normal SPI transactions are disallowed.
CSB_AUX: this pin is only available in SFL mode. Selecting the check box brings the CSB_AUX pin high, which advances the internal state machine pointer
to the next LUT. If an external waveform generator is connected to the CSB_EXT port on the ADMV8505-EVALZ, the CSB_AUX pin has no effect, and the
CSB_EXT port takes precedence.
H Click Proceed to Memory Map to open the ADMV8505 Memory Map (see
J1 All changes, except those made within the CONFIGURATION section, do not take effect until clicking Apply Changes. If Auto Apply is highlighted in the
ADMV8505 Board tab (see
apply or read back the block diagram settings.
J2 To read back all of the SPI registers of the chip, click Read All.
J3 Click Reset Chip to reset the chip.
J4 Click Diff to show registers that are different on the chip.
J5 Click Software Defaults to restore the software defaults to the chip, and then click Apply Changes. The software defaults for the ADMV8505 registers are
zero, except for Register 0x011, which is set to 0x7F, and the interpolation coefficients in Register 0x300 to Register 0x30F.
J6 Click Memory Map Side-By-Side to enable the side by side memory map view.
K Click Interpolation Coefficients to open the subdiagram for displaying and editing the interpolation coefficients (see
can be changed to calibrate the center frequency and/or change the desired operating bandwidth of the filter. Once the Interpolation Coefficients subdiagram
is visible, an additional button, Calibration, is available. Click Calibration to open the additional subdiagram (see
calibration sequence. Refer to the ADMV8505 data sheet theory of operations section for guidance on editing the interpolation coefficients.
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Figure 7) (Continued)
Figure 7), the following controls are visible:
Figure 7), the following controls are visible:
Figure 12). While in SFL mode, the ADMV8505 CS pin is connected to the SDP-S logic pin, CSB_AUX, and
Figure 5), the Apply Changes feature continuously runs every few seconds, and users do not have to click the Apply Changes to
EVAL-ADMV8505
Figure 8)
ADG749BKSZ
Figure 9). The interpolation coefficients
Figure 10) for performing the recommended
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