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Chapter 4: BIOS
Memory RAS Configuration
Memory RAS Configuration Setup
Enable Pcode WA for SAI PG
Use this feature to enable the Pcode Work Around for SAI Policy Group. The options
are Disable and Enable.
Mirror Mode
This feature allows memory to be mirrored between two channels, providing 100%
redundancy. The options are Disable, Mirror Mode 1LM, and Mirror Mode 2LM.
UEFI ARM Mirror
This options allows the system to imitate the behavior of the UEFI based Address
Range Mirror with setup option. The options are Disable and Enable.
Correctable Error Threshold
Use this feature to specify the threshold value for correctable memory-error logging,
which sets a limit on the maximum number of events that can be logged in the memory
error log at a given time. The default setting is 512.
Partial Cache Line Sparing PCLS
Use this feature to enable Partial Cache Line Sparing (PCLS). The options are Disable
and Enable.
ADDDC Sparing
Adaptive Double Device Data Correction (ADDDC) Sparing detects when the prede-
termined threshold for correctable errors is reached, copying the contents of the failing
DIMM to spare memory. The failing DIMM or memory rank will then be disabled. The
options are Disable and Enable.
Patrol Scrub
Patrol Scrubbing is a process that allows the CPU to correct correctable memory errors
detected on a memory module and send the correction to the requestor (the original
source). When this feature is set to Enable, the IO hub will read and write back one
cache line every 16K cycles if there is no delay caused by internal processing. By us-
ing this method, roughly 64 GB of memory behind the IO hub will be scrubbed every
day. The options are Disable, Enable, and Enable at End of POST.
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