Toshiba TLCS-900/H1 Series Manual page 6
Original cmos 32-bit microcontroller
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PG0 to PG1
(AN0 to AN1)
AN2/MX (PG2)
AN3/MY/
(PG3)
ADTRG
AVCC, AVSS
VREFH, VREFL
(PX, INT4) P96
(PY, INT5) P97
(TXD0, TXD1) PF0
(RXD0, RXD1) PF1
(SCLK0,SCLK1) PF2
D+
D−
(I2SCKO, TXD0) P90
(I2SDO, RXD0) P91
(I2SWS, SCLK0,
) P92
CTS
0
(LGOE0) P93
(LGOE1) P94
(LGOE2, CLK32KO) P95
(TA1OUT, INT0) PC0
(TA3OUT, INT1) PC1
(TB0OUT0, INT2) PC2
(INT3) PC3
(LCP0) PK0
(LLP) PK1
(LFR) PK2
(LBCD) PK3
PL0 to PL7
(LD0 to LD7)
(
,
) PJ0
SDRAS
SRLLB
(
,
) PJ1
SDCAS
SRLUB
(
,
) PJ2
SDWE
SRWR
(SDLLDQM) PJ3
(SDLUDQM) PJ4
(NDALE, SDULDQM) PJ5
(NDCLE, SDUUDQM) PJ6
(SDCKE) PJ7
(SDCLK) PF7
900/H1 CPU
10-bit
4-channel
XWA
AD converter
XBC
Touch
XDE
screen
XHL
I/F (TSI)
XIX
XIY
Serial I/O
XIZ
SIO0
XSP
Serial I/O SIO1
SR
USB
controller
Watchdog timer
2
I
S
MMU
Port 9
8-bit timer
(TIMERA0)
8-bit timer
(TIMERA1)
8-bit timer
(TIMERA2)
8-bit timer
(TIMERA3)
16-bit timer
(TIMERB0)
LCD
controller
16-KB RAM
SDRAM
controller
8-KB mask ROM
(Boot program)
Figure 1.1 TMP92CH21 Block Diagram
92CH21-4
PLL
H-OSC
W A
B
C
Clock gear
D
E
H
L
L-OSC
IX
IY
IZ
SP
Interrupt
32 bits
controller
F
PC
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
NAND flash
I/F (2 channel)
Port 8
Keyboard
I/F
RTC
Melody/
Alarm out
TMP92CH21
DVCC [4]
DVSS [3]
X1
X2
TEST
XT1
XT2
RESET
AM0
AM1
D0 to D7
P10 to P17
(D8 to D15)
P20 to P27
(D16 to D23, KO0 to KO7)
P30 to P37
(D24 to D31)
P40 to P47
(A0 to A7)
P50 to P57
(A8 to A15)
P60 to P67
(A16 to A23)
P70 (
)
RD
P71 (
,
)
WRLL
NDRE
P72 (
,
)
WRLU
NDWE
P73 (EA24)
P74 (EA25)
P75 (R/
, NDR/B)
W
P76 (
)
WAIT
P80 (
)
CS
0
P81 (
,
)
CS
1
SDCS
P82 (
,
,
)
CS
2
CSZA
SDCS
P83 (
)
CS
3
P84 (
,
,
)
CSZB
WRUL
ND
0
CE
P85 (
,
,
)
CSZC
WRUU
ND
1
CE
P86 (
,
)
CSZD
SRULB
P87 (
,
)
CSZE
SRUUB
PC7 (
, LCP1)
CSZF
PA0 to PA7 (KI0 to KI7,
LD8 to LD11)
PC6 (KO8, LDIV)
PM2 (
,
)
ALARM
MLDALM
PM1 (MLDALM)
2006-09-15
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