Toshiba TLCS-900/H1 Series Manual page 52

(2) Write cycle (0 waits)
t
OSC
X1
t
CH
SDCLK
WAIT
A0~A23
CSn
R/
W
t
AW
WRxx
D0~D31
t
RDO
RD
SRxxB
t
SAS
SRWR
Note: The phase relation between X1 input signal and the other signals is undefined.
The above timing chart is an example.
t
CYC
t
CL
t t
TK KT
t
WK
t
WW
t
DW
Data output
t
SBW
t
SDS
t
SWP
92CH21-469
TMP92CH21
t
WA
t
SWR
t
WD
t
SDH
2006-09-15