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Setting Up the
HP 10343B
Front Pane!
The HP 10343B has three switches on the front panel (see figure 2-2):
Bus Mode. Allows the user to test either a Single-Ended or Differential
Bus system. This switch setting must match the type of SCSI bus you are
currently monitoring.
State Parity Check. The use of the parity bit is not manditory on a SCSI
bus system. This switch allows the user to switch off the parity check.
Note
Excessive parity errors may appear on screen if parity is on with a
system that does not use parity.
Timing Bit Select This switch allows you to select the Parity, Select, or
Reset lines for timing. The output of this selection is on Status bit 3 of
pod 1 which connects to bucket D of the HP 10269A/B.
Note
HP 163QA/G and HP 1631A Logic Analyzers do not have
enough timing channels to look at both the Timing Status and
Data lines at the same time. To look at the Status or Data lines,
you must manually move pod 1 of the logic analyzer between
connector C (Data) and connector D (Status) of the HP
10269A/B. Only one group of timing lines can be seen at one
time.
SCSI Bus Preprocessing
2-7
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