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Principles of Operation
RECEIVE BUFFER MANAGEMENT. The host is responsible for setting aside receive buffers in system
memory. The starting address and length of each buffer are sent to the LANIC via the RECV command.
These buffers are identified via a unique ID number. When the LANIC fills a receive buffer, it returns
the ID number to the host via the Response Queue (RQ). From the time that the host enters the buffer
descriptor into the CQ until the LANIC returns the 10 number in the RQ, the host must ensure that the
buffer is frozen in physical memory. Since neither the host nor the LANIC have control over what time
a packet arrives, there must be a sufficient number of buffers ready for the LANIC to receive bursts of
packets, otherwise packets will be lost. For further information on lost packets, see the paragraph
"Receiver Blind Spots".
QUEUING OF RECEIVED PACKETS. Received packets may be queued by the LANIC before being
reported to the host. In order to report received packets to the host, the LANIC nlicroprocessor must
access system memory. However, it may not be able to do this during a burst of receive packets because
the LANIC DMA capability will be saturated with packet transfers to system memory. The
microprocessor will update the RQ as soon as a lull in received packet traffic occurs.
RECEIVER BLIND SPOTS. Under certain conditions, the LANIC can fail to receive a packet. The
following conditions are necessary for the LANIC to receive a packet at any time:
The receiver must be turned on.
There must be a buffer ready to receive the packet.
The LANIC must be able to write to memory fast enough to prevent losing data.
If any of the above conditions are not met, receive packets will be lost.
RECEIVE OPERATION EXAMPLE. The host allocates one or more receive buffers and enters RECV
commands containing the buffer descriptors and IDs into the CQ. The LANIC removes these descriptors
from the CQ and puts them on an internal queue, and turns the 82586 LCC receiver on. The LCC
prepares for packet reception by taking the first buffer descriptor off the internal queue. The Lec looks
at the destination address of all packets on the network. When the destination address matches the
LANIC's station address, the LCC deserializes the packet and starts writing it to system memory using the
current receive buffer descriptor. At the end of the packet, the LeC compares the CRe and re-uses the
buffer descriptor if there was an error in packet reception. Otherwise, the LCC records the packet
reception, prepares the next buffer descriptor from the internal queue, and interrupts the microprocessor.
When the microprocessor acknowledges the interrupt, the LCC adds the status and ID number of the
completed packet(s) to the RQ.
Error Management
The LANIC detects command, system, and network errors, takes recovery action when appropriate, and
reports status to the host. Command format errors are simply reported to the host, but do not result in
any interruption of operations in progress. The LANIC attempts recovery of certain errors, such as MAU
jabber, and if recovery is successful, the LANIC reports the recovery to the host for logging, and continues
operation. When the LANIC detects a non -recoverable error, such as a system memory error, it aborts all
operations in progress, reports the nature of the error to the host via the system interrupt mechanism, and
waits for further action by the host.
Feb 85
3-5
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