Analog Power Layout; Crystal - Espressif Systems ESP32-S3 Hardware Design Manuallines

Chapter 4. PCB Layout Design
If the chip power entrance is not near VDD3P3, it is recommended to add a 10 µF capacitor to both the chip
power entrance and VDD3P3. Also, reserve two 1 µF capacitors if space permits.
• The width of the main power traces should be no less than 25 mil. The width of VDD3P3 power traces should
be no less than 20 mil. The recommended width of other power traces is 10 mil.

4.3.3 Analog Power Layout

Figure ESP32-S3 Analog Power Traces in a Four-layer PCB Design
PCB design.
Fig. 6: ESP32-S3 Analog Power Traces in a Four-layer PCB Design
The analog power layout should meet the following guidelines:
• As shown in Figure ESP32-S3 Analog Power Traces in a Four-layer PCB
the capacitor to ground in the CLC filter circuit near VDD3P3 to the fourth layer through a via, and maintain
a keep-out area on other layers. The purpose is to further reduce harmonic interference.
• VDD3P3 analog power supply should be surrounded by ground copper. It is required to add GND isolation
between VDD3P3, power trace and the surrounding GPIO and RF traces, and place vias whenever possible.

4.4 Crystal

Figure ESP32-S3 Crystal Layout (with Keep-out Area on Top Layer)
connected to the ground through vias and a keep-out area is maintained around the crystal on the top layer for ground
isolation.
Figure ESP32-S3 Crystal Layout (without Keep-out Area on Top Layer)
nected to the ground through vias but there is no keep-out area on the top layer for ground isolation.
If there is sufficient ground on the top layer, it is recommended to maintain a keep-out area around the crystal for
ground isolation. This helps to reduce the value of parasitic capacitance and suppress temperature conduction, which
can otherwise affect the frequency offset.
The layout of the crystal should follow the guidelines below:
• Ensure a complete GND plane for the RF, crystal, and chip.
• The crystal should be placed far from the clock pin to avoid interference on the chip. The gap should be at least
2.0 mm. It is good practice to add high-density ground vias stitching around the clock trace for better isolation.
• There should be no vias for the clock input and output traces, which means the traces cannot cross layers. The
clock traces should not intersect with each other.
• Components in series to the crystal trace should be placed close to the chip side.
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shows a reference PCB layout where the crystal is
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shows the analog power layout in a four-layer
Design, it is recommended to connect
shows the layout for the crystal that is con-
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