Power Layout; Analog Power Layout; Two-Layer Pcb Design; Crystal - Espressif Systems ESP32 Hardware Design Manuallines

Chapter 4. PCB Layout Design
• The ground pad at the bottom of the chip should be connected to the ground plane through at least nine ground
vias.
• If you need to add a thermal pad EPAD under the chip on the bottom of the module, it is recommended to
employ a square grid on the EPAD, cover the gaps with solder paste, and place ground vias in the gaps, as
shown in Figure ESP32 Power Traces in a Four-layer PCB
by tin leakage and bubbles when soldering the module EPAD to the substrate.
4.3.2 3.3 V Power Layout
The 3.3 V power traces, highlighted in yellow, are routed as shown in Figure
PCB Design.
The 3.3 V power layout should meet the following guidelines:
• The ESD protection diode is placed next to the power port (circled in red in Figure
Four-layer PCB Design). The power trace should have a 10 µF capacitor on its way before entering into the
chip, and a 0.1 or 1 µF capacitor could also be used in conjunction. After that, the power traces are divided
into several branches using a star-shaped topology, which reduces the coupling between different power pins.
Note that all decoupling capacitors should be placed close to the corresponding power pin, and ground vias
should be added close to the capacitor's ground pad to ensure a short return path.
• In Figure ESP32 Power Traces in a Four-layer PCB
supply VDD3P3, and the power entrance since the analog power is close to the chip power entrance. If the
chip power entrance is not near VDD3P3, it is recommended to add a 10 µF capacitor to both the chip power
entrance and VDD3P3. Also, reserve two 1 µF capacitors if space permits.
• The width of the main power traces should be no less than 25 mil. The width of VDD3P3 power traces should
be no less than 20 mil. The recommended width of other power traces is 10 mil.

4.3.3 Analog Power Layout

The analog power layout should meet the following guidelines:
• VDD3P3 analog power supply should be surrounded by ground copper. It is required to add GND isolation
between VDD3P3, power trace and the surrounding GPIO and RF traces, and place vias whenever possible.

4.3.4 Two-layer PCB Design

In a two-layer PCB design, the 3.3 V power traces are routed as shown labelled with VDD33 in Figure
Traces in a Two-layer PCB
The power layout in a two-layer PCB design should meet the following guidelines:
• In contrast to the design practices for a four-layer PCB design, the power traces in a two-layer PCB design
should be routed on the top layer.
• Reduce the size of the thermal pad in the center of the chip. Route the power traces between the thermal pad
and its surrounding signal pins. Employ vias only when the power traces have to reach the bottom layer.
• Maintain a complete ground plane while reducing the surrounding area of the power traces.
• Other good practices for routing power traces in four-layer PCB designs still apply to two-layer PCB designs.

4.4 Crystal

Figure ESP32 Crystal Layout (with Keep-out Area on Top Layer)
connected to the ground through vias and a keep-out area is maintained around the crystal on the top layer for ground
isolation.
The layout of the crystal should follow the guidelines below:
Espressif Systems
Design.
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Design. This can avoid chip displacement caused
ESP32 Power Traces in a Four-layer
Design, the 10 µF capacitor is shared by the analog power
shows a reference PCB layout where the crystal is
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ESP32 Power Traces in a
ESP32 Power
Release master