Power Supply; General Guidelines; Power Layout - Espressif Systems ESP32-S3 Hardware Design Manuallines

Chapter 4. PCB Layout Design

4.3 Power Supply

Figure ESP32-S3 Power Traces in a Four-layer PCB Design
PCB design.

4.3.1 General Guidelines

• Four-layer PCB design is preferred.
• The power traces should be routed on the inner third layer whenever possible.
• Vias are required for the power traces to go through the layers and get connected to the pins on the top layer.
There should be at least two vias if the main power traces need to cross layers. The drill diameter on other
power traces should be no smaller than the width of the power traces.
• The ground pad at the bottom of the chip should be connected to the ground plane through at least nine ground
vias.
• If you need to add a thermal pad EPAD under the chip on the bottom of the module, it is recommended to
employ a square grid on the EPAD, cover the gaps with solder paste, and place ground vias in the gaps, as
shown in Figure ESP32-S3 Power Traces in a Four-layer PCB
by tin leakage and bubbles when soldering the module EPAD to the substrate.
4.3.2 3.3 V Power Layout
The 3.3 V power traces, highlighted in yellow, are routed as shown in Figure
PCB Design.
The 3.3 V power layout should meet the following guidelines:
• The ESD protection diode is placed next to the power port (circled in red in Figure
a Four-layer PCB Design). The power trace should have a 10 µF capacitor on its way before entering into the
chip, and a 0.1 or 1 µF capacitor could also be used in conjunction. After that, the power traces are divided
into several branches using a star-shaped topology, which reduces the coupling between different power pins.
Note that all decoupling capacitors should be placed close to the corresponding power pin, and ground vias
should be added close to the capacitor's ground pad to ensure a short return path.
• In Figure ESP32-S3 Power Traces in a Four-layer PCB
power supply VDD3P3, and the power entrance since the analog power is close to the chip power entrance.
Espressif Systems
Fig. 5: ESP32-S3 Power Traces in a Four-layer PCB Design
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shows the overview of the power traces in a four-layer
Design. This can avoid chip displacement caused
ESP32-S3 Power Traces in a Four-layer
Design, the 10 µF capacitor is shared by the analog
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ESP32-S3 Power Traces in
Release master