Off-Package Flash And Psram; Clock Source; External Crystal Clock Source (Compulsory) - Espressif Systems ESP32-S3 Hardware Design Manuallines

Chapter 3. Schematic Checklist
Table 4: Pin-to-Pin Mapping Between Chip and In-Package Quad SPI
PSRAM
ESP32-S3R2/ESP32-S3FH4R2
SPICLK
SPICS1
SPID
SPIQ
SPIWP
SPIHD
Table 5: Pin-to-Pin Mapping Between Chip and In-Package Octal SPI
PSRAM
ESP32-S3R8/ESP32-S3R8V
SPICLK
SPICS1
SPID
SPIQ
SPIWP
SPIHD
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37

3.3.2 Off-Package Flash and PSRAM

ESP32-S3 supports up to 1 GB off-package flash and 1 GB off-package RAM. If VDD_SPI is used to supply power,
make sure to select the appropriate off-package flash and RAM according to the power voltage on VDD_SPI (1.8
V/3.3 V). It is recommended to add a zero-ohm series resistor on the SPI communication lines to lower the driving
current, reduce interference to RF, adjust timing, and better shield from interference.

3.4 Clock Source

ESP32-S3 supports two external clock sources:
•

External crystal clock source (Compulsory)

• RTC clock source (Optional)
3.4.1 External Crystal Clock Source (Compulsory)
The ESP32-S3 firmware only supports 40 MHz crystal.
The circuit for the crystal is shown in Figure
selected crystal should be within ±10 ppm.
Please add a series component (resistor or inductor) on the XTAL_P clock trace. Initially, it is suggested to use an
inductor of 24 nH to reduce the impact of high-frequency crystal harmonics on RF performance, and the value should
be adjusted after an overall test.
The initial values of external capacitors C1 and C4 can be determined according to the formula:
Espressif Systems
In-Package PSRAM (2 MB, Quad SPI)
CLK
CE#
SI/SIO0
SO/SIO1
SIO2
SIO3
In-Package PSRAM (8 MB, Octal SPI)
CLK
CE#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS/DM
ESP32-S3 Schematic for External
C1 × C4
C = + C
L stray
C1 + C4
14
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Crystal. Note that the accuracy of the
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