Espressif Systems ESP32-S3 Hardware Design Manuallines page 24

Hide thumbs Also See for ESP32-S3:
  • Faq (191 pages)
Table of Contents

Advertisement

Chapter 3. Schematic Checklist
No.
Name
44
MTCK
45
MTDO
46
VDD3P3_CPU
47
MTDI
48
MTMS
49
U0TXD
50
U0RXD
51
GPIO45
52
GPIO46
53
XTAL_N
54
XTAL_P
55
VDDA
56
VDDA
57
GND
• IE –input enabled
• WPU –internal weak pull-up resistor enabled
• WPD –internal weak pull-down resistor enabled
• USB_PU –USB pull-up resistor enabled
– By default, the USB function is enabled for USB pins (i.e., GPIO19 and GPIO20), and
the pin pull-up is decided by the USB pull-up resistor.
controlled by USB_SERIAL_JTAG_DP/DM_PULLUP and the pull-up value is controlled by
USB_SERIAL_JTAG_PULLUP_VALUE. For details, see
Chapter USB Serial/JTAG Controller.
– When the USB function is disabled, USB pins are used as regular GPIOs and the pin's internal weak
pull-up and pull-down resistors are disabled by default (configurable by IO_MUX_FUN_WPU/WPD)
Pin
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
XTAL_32K_P
XTAL_32K_N
GPIO17
GPIO18
GPIO19
GPIO20
3
• Low-level glitch: the pin is at a low level output status during the time period;
• High-level glitch: the pin is at a high level output status during the time period;
• Pull-down glitch: the pin is at an internal weak pulled-down status during the time period;
• Pull-up glitch: the pin is at an internal weak pulled-up status during the time period.
Espressif Systems
Table 9 – continued from previous page
Type
Power
IO
VDD3P3_CPU
IO
VDD3P3_CPU
Power
IO
VDD3P3_CPU
IO
VDD3P3_CPU
IO
VDD3P3_CPU
IO
VDD3P3_CPU
IO
VDD3P3_CPU
IO
VDD3P3_CPU
Analog
Analog
Power
Power
Power
Table 10: Power-Up Glitches on Pins
3
Glitch
Low-level glitch
Low-level glitch
Low-level glitch
Low-level glitch
Low-level glitch
Low-level glitch
Low-level glitch
Low-level glitch
Low-level glitch
Low-level glitch
Low-level glitch
Low-level glitch
Low-level glitch
Low-level glitch
Low-level glitch
Low-level glitch
Low-level glitch
Low-level/High-level glitch
Low-level glitch/High-level glitch
Pull-down glitch/High-level glitch
Submit Document Feedback
At Reset
After Reset
IE
IE
IE
IE
IE, WPU
IE, WPU
IE, WPU
IE, WPU
IE, WPD
IE, WPD
IE, WPD
IE, WPD
The USB pull-up resistor is
ESP32-S3 Technical Reference Manual
4
Page 22, 4
21
IO MUX
RTC
Analog
IO MUX
IO MUX
IO MUX
IO MUX
IO MUX
IO MUX
IO MUX
IO MUX
>
Typical Time (µs)
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
Release master

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the ESP32-S3 and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Table of Contents

Save PDF