Flash And Psram - Espressif Systems ESP32-S3 Hardware Design Manuallines

Chapter 4. PCB Layout Design
• The external matching capacitors should be placed on the two sides of the crystal, preferably at the end of the
clock trace, but not connected directly to the series components. This is to make sure the ground pad of the
capacitor is close to that of the crystal.
• Do not route high-frequency digital signal traces under the crystal. It is best not to route any signal trace under
the crystal. The vias on the power traces on both sides of the crystal clock trace should be placed as far away
from the clock trace as possible, and the two sides of the clock trace should be surrounded by grounding copper.
• As the crystal is a sensitive component, do not place any magnetic components nearby that may cause interfer-
ence, for example large inductance component, and ensure that there is a clean large-area ground plane around
the crystal.
4.5 RF
The RF trace is routed as shown highlighted in pink in Figure
The RF layout should meet the following guidelines:
• A π-type matching circuit should be added to the RF trace and placed close to the chip, in a zigzag.
• The RF trace should have a 50 Ω characteristic impedance. The reference plane is the second layer. For
designing the RF trace at 50 Ω impedance, you could refer to the PCB stack-up design shown below.
• Add a stub to the ground at the ground pad of the first matching capacitor to suppress the second harmonics.
It is preferable to keep the stub length 15 mil, and determine the stub width according to the PCB stack-up
so that the characteristic impedance of the stub is 100 Ω ± 10%. In addition, please connect the stub via to
the third layer, and maintain a keep-out area on the first and second layers. The trace highlighted in Figure
ESP32-S3 Stub in a Four-layer PCB Design
0201.
• The RF trace should have a consistent width and not branch out. It should be as short as possible with dense
ground vias around for interference shielding.
• The RF trace should be routed on the outer layer without vias, i.e., should not cross layers. The RF trace should
be routed at a 135° angle, or with circular arcs if trace bends are required.
• The ground plane on the adjacent layer needs to be complete. Do not route any traces under the RF trace
whenever possible.
• There should be no high-frequency signal traces routed close to the RF trace. The RF antenna should be
placed away from high-frequency components, such as crystals, DDR SDRAM, high-frequency clocks, etc. In
addition, the USB port, USB-to-serial chip, UART signal lines (including traces, vias, test points, header pins,
etc.) must be as far away from the antenna as possible. The UART signal line should be surrounded by ground
copper and ground vias.

4.6 Flash and PSRAM

The layout for flash and PSRAM should follow the guidelines below:
Espressif Systems
Fig. 9: ESP32-S3 RF Layout in a Four-layer PCB Design
is the stub. Note that a stub is not required for package types above
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ESP32-S3 RF Layout in a Four-layer PCB
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Design.
Release master