Cmsemicon CMS32L051 Manuals

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Cmsemicon CMS32L051 User Manual (703 pages)

Ultra-low-power 32-bit microcontroller based on the ARM Cortex-M0+

Brand: Cmsemicon | Category: Microcontrollers | Size: 16 MB

Documentation Instructions
2
Table of Contents
3
Chapter 1 CPU

14
- 1.1 Overview
  14
- 1.2 Cortex-M0+ Core Features
  14
- 1.3 Debugging Features
  14
- 1.4 SWD Interface Pin
  16
- 1.5 ARM Reference Document
  17
Chapter 2 Pin Function

18
Chapter 3 System Structure

57
- 3.1 Overview
  57
- 3.2 System Address Partition
  58
Chapter 4 Clock Generation Circuit

60
Chapter 5 Universal Timer Unit (Timer4)

107
Chapter 6 Function of EPWM Output Control Circuit

205
Chapter 7 Real-Time Clock

220
Chapter 8 15-Bit Interval Timer

245
Chapter 9 Clock Output/Buzzer Output Controller

251
Chapter 10 Watchdog Timer

257
Chapter 12 Universal Serial Communication Unit

295
Chapter 13 Serial Interface SPI

459
- Serial Interface SPI Function
  459
- Structure of SPI
  459
- Registers for Controlling SPI
  460
- Peripheral Enable Register 0 (PER0)
  461
- SPI Operating Mode Register (SPIM)
  462
- SPI Clock Selection Register (SPIC)
  463
- Transmit Buffer Registers (SDRO)
  464
- Receive Buffer Register (SDRI)
  464
- SPI Pin Port Function Control Register
  465
- Operation of SPI
  466
- Master Tramission and Reception
  467
- Master Reception
  470
- Slave Send and Receive
  473
- Slave Reception
  476
Chapter 14 Serial Interface IICA

479
- Function of IICA
  479
- Structure of the Serial Interface IICA
  482
- Registers for Controlling Serial Interface IICA
  485
- Peripheral Enable Register 0 (PER0)
  486
- IICA Control Register N0 (Iicctln0)
  486
- IICA Status Register N (Iicsn)
  491
- IICA Flag Register N (Iicfn)
  493
- IICA Control Register N1 (Iicctln1)
  495
- IICA Low Level Width Setting Register N (Iicwln)
  497
- IICA High Level Width Setting Register N (Iicwhn)
  497
- Registers Controlling the IICA Pin Port Function
  498
- Function of I C-Bus Mode
  499
- Pin Structure
  499
- Setting the Transmit Clock Via Iicwln Register and Iicwhn Register
  500
- Definition and Control Method of I C-Bus
  501
- Start Conditions
  502
- Address
  503
- Designation of Transmission Direction
  503
- Acknowledge (ACK)
  504
- Stop Conditions
  505
- Wait
  506
- Release Method of Wait
  508
- Interrupt Request (Intiican) Generation Timing and Wait Control
  509
- Detection Method for Address Matching
  510
- Detection of Errors
  510
- Extension Code
  511
- Arbitration
  512
- Wake-Up Function
  514
- Communicate with Reservation
  517
- Other Cautions
  521
- Communication Operation
  522
- Generation Timing of I C Interrupt Request (Intiican)
  531
- Timing Diagram
  552
Chapter 15 Irda

568
- Function of Irda
  568
- Registers for Controlling the Irda
  569
- Peripheral Enable Register 0 (PER0)
  569
- Irda Control Register (IRCR)
  570
- Operation of Irda
  571
- Operating Steps for Irda Communication
  571
- Transmission
  572
- Reception
  572
- High Level Pulse Width Selection
  573
- Considerations When Using Irda
  573
Chapter 16 Enhanced DMA

574
- The Function of DMA
  574
- Structure of DMA
  576
- Registers for Controlling DMA
  577
- DMA Control Data Areas and DMA Vector Table Areas Allocation
  578
- Control Data Allocation
  579
- Vector Table
  581
- Peripheral Enable Register 1 (PER1)
  583
- DMA Control Register J(Dmacrj) (J=0~23)
  583
- DMA Block Size Register J (Dmblsj) (J=0~23)
  585
- DMA Transmit Count Register J(Dmactj) (J=0~23)
  586
- DMA Transmit Count Reload Register J(Dmrldj) (J=0~23)
  587
- DMA Source Address Register J(Dmsarj) (J=0~23)
  588
- DMA Destination Address Register J(Dmdarj) (J=0~23)
  588
- DMA Boot Enable Register I (Dmaeni) (I=0~2)
  589
- DMA Base Address Register (DMABAR)
  591
- DMA Operation
  592
- Start the Source
  592
- Normal Mode
  593
- Repeat Pattern
  596
- Chain Transfer
  599
- Precautions When Using DMA
  601
- DMA Controls the Settings of Data and Vector Tables
  601
- DMA Controls the Allocation of Data Areas and DMA Vector Table Areas
  601
- Number of Execution Clocks for DMA
  602
- Response Time of DMA
  603
- Startup Source for DMA
  603
- Operation in Standby Mode
  604
Chapter 17 Linkage Controller (EVENTC)

605
- Feature of EVENTC
  605
- Structure of EVENTC
  605
- Control Registers
  606
- Output Target Selection Register N (Elselrn) (N=00~14)
  607
- Operation of EVENTC
  610
Chapter 18 Interrupt Function

611
Chapter 19 Key Interrupt Function

623
- Function of Key Interrupt
  623
- Structure of Key Interrupt
  623
- Registers for Controlling Key Interrupt
  625
- Key Return Mode Register (KRM)
  625
- Port Mode Register (Pmx)
  626
Chapter 20 Standby Function

627
- Standby Function
  627
- Sleep Mode
  628
- Setting of the Sleep Mode
  628
- Release of Sleep Mode
  631
- Deep Sleep Mode
  632
- The Setting for Deep Sleep Mode
  632
- Release of Deep Sleep Mode
  634
Chapter 21 Reset Function

636
- Register for Confirming the Reset Source
  641
- Reset Control Flag Register (RESF)
  641
Chapter 22 Power-On Reset Circuit

644
Chapter 23 Voltage Detection Circuit

649
Chapter 24 Security Features

667
Chapter 25 Temperature Sensor

683
Chapter 26 Option Byte

686
Chapter 27 FLASH Control

695
- Description of FLASH Control
  695
- Structure of FLASH Memory
  695
- Registers for Controlling FLASH
  696
- Flash Write Protection Register (FLPROT)
  696
- FLASH Operation Control Registers (FLOPMD1, FLOPMD2)
  697
- Flash Erase Control Register (FLERMD)
  697
- Flash Status Register (FLSTS)
  698
- Flash Full-Chip Erase Time Control Register (FLCERCNT)
  698
- Flash Sector Erase Time Control Register (FLSERCNT)
  699
- Flash Write Time Control Register (FLPROCNT)
  700
- FLASH Operation Method
  701
- Sector Erase
  701
- Chip Erase
  702
- Programming (Word Program)
  702
- Flash Read
  702
- Cautions for FLASH Operation
  702
Appendix Revision History

703

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Cmsemicon CMS32L051 Manuals

Cmsemicon CMS32L051 User Manual (703 pages)

Table of Contents

Chapter 1 CPU

Chapter 2 Pin Function

Chapter 3 System Structure

Chapter 4 Clock Generation Circuit

Chapter 5 Universal Timer Unit (Timer4)

Chapter 6 Function of EPWM Output Control Circuit

Chapter 7 Real-Time Clock

Chapter 8 15-Bit Interval Timer

Chapter 9 Clock Output/Buzzer Output Controller

Chapter 10 Watchdog Timer

Chapter 12 Universal Serial Communication Unit

Chapter 13 Serial Interface SPI

Chapter 14 Serial Interface IICA

Chapter 15 Irda

Chapter 16 Enhanced DMA

Chapter 17 Linkage Controller (EVENTC)

Chapter 18 Interrupt Function

Chapter 19 Key Interrupt Function

Chapter 20 Standby Function

Chapter 21 Reset Function

Chapter 22 Power-On Reset Circuit

Chapter 23 Voltage Detection Circuit

Chapter 24 Security Features

Chapter 25 Temperature Sensor

Chapter 26 Option Byte

Chapter 27 FLASH Control

Appendix Revision History

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