Baud Rate Clock Generation; Dart Operations; Keyboard Communication; General - Facit 4431 Service Instruction

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7.5
INP~T/OUTPUT
INTERFACES
The Facit 4431 I/0 interface utilizes an Z80A -
DART (Dual channel Asynchronous Receiver/Trans-
mitter) 066, in conjunction with a programmable
clock generator 065 and 076, a Line Driver 074,
a Line Receiver 075, Transistor V108 to provide
two independent serial data channels and key-
board UART 058 with baud rate generator 057, KBD
Line driver 073/070 and KBD Line Receiver V104/
073. The primary channel is dedicated to commu-
nication with the host and is labeled the I/0
port (X1). The second channel allows communica-
tion with a local printer (X2). Keyboard commu-
nication is through a coiled cabel from connec-
tor X3 to the external keyboard. The Z80A recei-
ves vectored interrupts from the DART when I/O
operations require service.
7.5.1 BAUD RATE CLOCK GENERATION
The 4MHz CPU clock is divided by 13 in 076 and
the resulting 30.8KHz signal at 076-7 goes to
the clock inputs 065-21, 22, 23 of the Z80A CTC
(Counter Timer Circuit). The CTC provides sepa-
rate baud rate clocks for the transmit and re-
ceive functions of the I/0 channel and one baud
rate clock for both the transmit and receive
functions of the printer channel. Also, 076-7
goes to the divider 057 and the output 057-3 is
used as keyboard communication baud rate clock.
The CPU programs the CTC to generate the proper
baud rates as selected in the SET-UP mode. All
three clocks oscillate at sixteen times the
desired data rate. The I/0 transmit and receive
clocks are connected to channel A clock inputs
of the DART at 066-14 and 066-13 respectively.
The printer clock is connected to the channel B
clock input of the DART at 066-27.
The CTC 065 is also programmed by the CPU to
generate interrupts at 8msec intervals which the
CPU uses as a real-time reference. It should be
noted that the interrupt priority structure es-
tablished by the connection from the IEI (Inter-
rupt Enable Input) at 065-13 allows the DART in-
terrupt to be processed before the CTC inter-
rupt.
7.5.2 DART OPERATIONS
The Z80A CPU determines the proper data format
(data bits, stop bits, parity, word lenght, etc)
from the Set-Up mode soft switches and programs
the DART for these characteristics. The DART
then takes care of all parallel/serial data con-
version and data formating. Data to be transmit-
ted is stored in a 128 character buffer and re-
ceived data is stored in a 256 character buffer
which are controlled by the CPU. TTL to RS232C/
V24 level conversion is provided by 074, and RS
232C/V24 to TTL conversion is performed by 075
and V108.
7.5.3 KEYBOARD COMMUNICATION
The keyboard communication is controlled by CPU
through the UART 058. The parallel to serial and
serial to parallel conversion and data formating
is taken care of by the UART. The UART transmits
and receive data to/from the keyboard using
standard RS232C/V24 formating (8 data bits, no
parity, 2 stop bits) no protocol is used and the
baud rate is 300 baud. 057 is a frequency dive-
der and 073 is a Transmit/Receive buffer, 070 is
used as a line driver and V104 as line receiver.
8 M 0 N I T 0 R A N D P 0 W E R
S U P P L Y _ _ _ _ _ _ _ _ _ _ _ _ _ _
8.1 GENERAL
The video monitor assembly consists of the vi-
deo electronic board, the display tube, and the
power supply unit. The monitor assembly is ser-
viced by replacement of the entire assembly.
8.2 MONITOR
Electrical Design
The horizontal sync, vertical sync and video
signals from the Main Logic Board drive the
horizontal, vertical and intensity modulation
circuits on the video board to produce a non-in
terlaced raster display on the CRT. The display
area is defined as a rectangle 8" wide by 6"
high in the middle of the screen to minimize
distortion and ensure optimum resolution. The
circuit is conceived to operate with a 12 Volt
power supply.
It
consists of:
• an IC for the horizontal processing (TOA
1180P 5IC2)
• a split transformer for the horizontal out-
put
• an IC for the vertical processing (TOA 1170
S 6IC2)
• a focusing voltage modulation circuit
Performances:
• picture tube with "non-glaring" treatment
• green phosphor P42 C with medium short per-
sistence (300uS)
• size of the picture 8"x6" +/- 0.2"
Input volt ages:
• Video min 1V to max 2V (positive)
• Hor.sync. pulse between +2.5V and +5V
• Frequency 15 700Hz +/- 500Hz
• Vertical sync. negative going between 2V and
5V
• Frequency 49Hz -- 61Hz
• Supply voltages 12V approx 1A