Facit 4431 Service Instruction page 11

6.2 DISPLAY REFRESH MEMORY
The Display Refresh Memory stores
code and video attribute status of
ter to be diplayed on the screen.
4431 has 4k (4096) 12 bit words of
mory to provide 2 pages of memory
MEM.
ADDRESS
FROM
MULTIPLEXOR
1 2
BANK
SEL
12
10 _.., --
r------.
ASCII
RAM
4k x 8
D51,52
ATTR
RAM
4k x 4
the ASCII
each chara-
The Facit
display me-
in the 80
14
. .
D26
D68,69,67,66
FIG 6.2
6.3 SYNCHRONIZATION GENERATOR
4
Figure 6.3 is a block diagram of the Sync Gene-
rator Circuits.
•
Z80 ADDRESS BUS
•
Z80 DATA BUS
CRT
REFRESH
CONTROLLER
. .
4
12
-"'
ADDRESS
r
11
column mode, or 1 page of memory in the 132
column mode. Access to the display memory by
the CPU (to write and read data) is controlled
by the DISPLAY ACCESS HANDLER circuitry. A
block diagram of the Display Refresh Memory is
shown in Fig 6.2.
TO (VG)
•
1 8
•
TO (VG)
•
1 4
4 _..
..
DISPLAY MEMORY
ASCII
BUFFERS
D54,55
ATTR
BUFFER
D70,71,53
14
8 _..,
--
14
.,t_4 --
...
CPU OATA
BUS
CPU DATA
BUS
The Sync Generator circuit provides all timing
signals required to:
-"'
r
_,.,
r
COLUMN ADDRESS
COUNTERS
12-"'
MULTIPLEXORS
8_..
r-
~
r
. .
..
12
~
D49
i.._
D29,30
Dl2,ll ,28
Dl3,10,27
-
t
+
MEM SHA
SCREEN
RE
CONTROL
i.._
-
4
CHARACTER RATE CLOCK
D30
•
•
NM! GENERATION
80/132
OOT
MEMORY
FOR SCROLLING AND
COLUMN ______.
OSCILLATOR
SHARE
LOADING ROW ADDRESS
SELECT
SIGNAL
D23,8
GENERATION
FIG 6.3 SYNCHRONIZATION GENERATOR
• address the display refresh memory to ex-
tract extract characters to be passed on to
the video generator circuit.
• indicate to the video generator circuit the
presence of double wide and/or double high
character rows.