Display Refresh Memory; Program Memory Access; Screen Attribute Latch; Ear Om - Facit 4431 Service Instruction

The reset circuit consisit of capacitor C1
(22uF), charged through a 22k resistor (R24),
diode V1, and D17. The votage across C1 is
coupled to a noninverting CMOS gate D17 through
a 12k resistor (R22). The output of gate is fed
back to the input through a 82k resistor (R23),
which guarantees that the circuit will not jit-
ter when passing the switching threshold (which
is approximately half the power supply voltage
for CMOS). Diode V1 quickly discharges C1 to
ensure that the processor will go through its
reset procedure and start up at address 0 in
the event of a brief power failure.
7.1.3 PROGRAM MEMORY ACCESS
The design of Facit 4431 allows the use of ei-
ther 2732 or 2764 EPROMs for the Z80 program
memory, resulting in a maximum of 24k when 3
2764s are used. Program memory decoding is ac-
complished in D17, which is enabled by D34-11
(the OR of read and memory request). Address
line A15 allows the processor to access program
memory when low, or to access the screen re-
fresh RAM when high.
7.1.4 SCREEN ATTRIBUTE LATCH
Octal latch D64 is used to write data and
control information to the EAROM (see section
7.1.5) and to latch data that controls the dis-
play attributes. When the screen saver feature
is enabled and approximately 9 minutes have
elapsed without reception of data from either
the host or keyboard D64-16 will go high to
blank the display. The level of D64-19 selects
either 80 or 132 column mode (low=80). Finnaly,
D64-2 is used to kill interrupts as discussed
in the Synch Generator portion of this manual
(Section 7.4).
7.1.5. EAROM
In the Facit 4431, operational characteristics
which are defined in most other terminals by
switches or jumpers are selected in Set-Up Mode
and are saved from one operating session to the
next in the EAROM D63. The EAROM is accessed
during power-up, terminal reset, and when a
Save or Recall Set-Up Features operation is
performed. At all other times the EAROM is in
the standby mode with pins 6, 7, 8, and 9 at
12V potentials. All data and control informa-
tion from the CPU is latched in D64 and passes
through the open collector gates of D65, which,
through the pull-up resistors of R34, provide
the additional current required by the EAROM.
The control lines D63-7, 8 and 9 select the
read/write address/data modes of the EAROM.
The EAROM contains one hundred 14 bit words
which are accessed serially through pin 12.
During any EAROM access operation (read, erase,
or write) a 14KHz clock signal appears on pin 6
and control signals on pins 7, 8 and 9. Due to
the critical timing constraints of the EAROM,
15
the CPU must suspend all other operations while
generating the clock, data and control signals.
To insure that non-maskable interrupts are dis-
abled, the CPU latches a high to D64-2 for the
duration of the EAROM access. EAROM read/write
operations access the entire device address
space and take about 2.5 seconds for a read and
6.5 seconds for a write. The data last written
to the device is retained when power is removed
Transistor V105 guarantees that ~he -23 Volt
supply is removed in sequence before the +12
volt supply to protect the EAROM during power-
down.
7.2 DISPLAY REFRESH MEMORY
The Facit 4431 was designed to allow the pro-
cessor transparent access to the display ref-
resh memory when the display is not active.
Without this means of resolving potential con-
flicts between the CPU and the refresh memory
circuitry, both could attempt to access the
display refresh RAM during the active display
interval, resulting in a chaotic display. The
Display Access Handle circuitry controls CPU
access to the display refresh RAM in the follo-
wing manner:
The MEMSHARE signal (see Section 7.4.3) allo-
cates one half of each character time to the
CPU to access the display memory and the other
half to the refresh circuitry. If the CPU
attempts to access the display refresh memory
during the refresh portion of the MEMSHARE sig-
nal the Display Access Handler circuitry places
the processor in the wait state until at least
one character position cycle is completed, at
which time the MEMSHARE signal will again be in
the CPU phase. When the Z80 enters the WAIT
state, it holds the address, data and read or
write lines at the active level until the end
of the WAIT state, at which time it completes
the read or write cycle.
7.2.1 WAIT STATE GENERATION
The MREQ signal from the processor is inverted
in D31 and ANDed with the MI signal so that the
output at D32-11 represents an attempt by the
processor to access memory other the the pro-
gram EPROMs. This signal is then ANDed with ad-
dress line A15 so that the output at D32-3 sig-
nifies an attempt by the CPU to access the dis-
play RAM. This output is tied to D14-1, which
takes shift register D14 out of the load state
so that the next CPU clock on D14-2 will cause
D14-9 to go low, as the parallel data is seri-
ally shifted out. The low D14-9 goes to D32-5,
which results in D32-6 going low and placing
the CPU in the WAIT state. The low at D14-9 al-
so goes to the D input of the F/F D31-12, which
will be clocked with the next rising edge of
the MEMSHARE signal to appear at the Q output
D31-9. This will force D32-6 low to ensure that
the CPU remains in the WAIT state until the CPU
portion of the MEMSHARE signal. D14-9 will re-
main low for three clock periods, until the da-