Table of Contents
Advertisement
16
ta loaded in to the D input D14-14
appears at
D14-9. At this point D14-9 and D31-12 are high,
but the signal are D32-6 will not go high until
the next rising edge of the MEMSHARE signal
clocks the data through F/F D31 to D32-4. This
synchronizes the end of the WAIT pulse with the
rising edge of MEMSHARE, which is the beginning
of the next CPU portion of the character time
cycle.
7.2.2
WRITING TO THE ASCII (Character)
DISPLAY MEMORY
The inputs to D25 (RD at D25-15, WR at D25-1,
the AND of A15 and MRQ at D25-13 and D25-3,
and A14 at D25-14 and D25-2) are used to deco-
de reads and writes to either the ASCII
(cha-
racter)
or ATTR
(attribute) display memory.
Note that the write ASCII signal from D25-6 is
the only signal from D25 to go through some
extra gating before proceeding to the memory
section. This was done to ensure that write
pulse
is present only during a specific por-
tion of the CPU part of a character time.
As
the WR ASCII signal at D25-6 goes low, which
is coincident with the WR pulse from the
CPU
at enable input D25-1, it is allowed through
D34 only when the WAIT signal
from D32-6
is
present at D34-10. This gate ensures that the
actual write to the display memory takes place
while the processor is in the WAIT state,
and
terminates synchronously with end of the WAIT
state.
Remember that on the rising edge of the MEM-
SHARE signal (which indicates the start of the
CPU portion of the character time) the address
multiplexers to the display RAM are switched
over to the CPU address bus from the refresh
circuit column counters.
Also remember that
the OK to Write signal (See section 7.4.3)
starts low about a third of the way into the
CPU portion of MEMSHARE, and terminates as the
MEMSHARE signal goes low at start of the re-
fresh
portion of the character time cycle.
Thus the output at D34-6, which is the OR of
OK to Write and WR ASCII, ensures that the ad-
dress from the multiplexers will
have had a
chance to properly settle before the write pul
se comes along. The signal from D24-2 to D54-
11
latches the data into D54, and the output
at D34-6 enables the output of the latch.
The
signal from D34-6 also goes to the write enab-
le inputs of the ASCII display RAM at
D51-21
and D52-21 to actually write the data into the
RAM.
7.2.3
READING THE ASCII (Character)
DISPLAY
MEMORY
When the CPU attempts to read the display me-
mory it will be placed in the WAIT state, as
explained in section 7.2.2,
and the address
and read lines from the processor will be held
in the active state. At the start of the
pro-
cessor portion of the character time cycle the
rising edge of the MEMSHARE signal will switch
the display RAM address multiplexers D27,
D10
and
D13 over to the CPU address bus, and at
the end of the CPU portion of the character
time cycle the rising edge of MEH SH at D55-11
will latch the data into D55. Since the multi-
plexers had the entire CPU portion of the cha-
racter time cycle in which to settle,
it
is
guaranteed that correct data was latched into
D55. The processor, however, will not actually
read the data from the latch until after WAIT
state ends, which occurs on the rising edge of
MEMSHARE at the start of the next CPU portion
of the character time cycle.
7.2.4
WRITING/READING THE ATTR
(Attribute)
DISPLAY RAM
Once again, when the processor attempts to ac-
cess the Display Memory it will be placed
in
the WAIT state as described in Section 7.2.1,
but the attribute data will
be immediatly
latched into D53 by the WR ATTR signal from
D25-7 to D53-11. The upper four
bits of the
attribute latch D53 are used to control full
screen attributes and are discussed in Section
7.3.3. 3. The lower four bits of the CPU data
bus,
DO-D3,
are
latched into D53 to set the
video attribute of individual
characters.
As
it
is ineffecient to write an attribute every
time a character is written, the write enable
inputs on
pin 10 of D68, D69 and D66 and the
enable line of tristate octal buffer D71
are
tied to the WR ASCII line so that whenever an
ASCII character is written into D51 or D52 the
attri butes are automatically written into the
corresponding location in the attribute memo-
ry. Thus the attribute latch D53 need be writ-
ten to only when an attribute change is desi-
red.
Reading the attributes is done through D70
in
1a manner similar to that for reading an ASCII
character from the display memory, as descri-
bed in Section 7.2.3. The attribute data is
placed on the lower four bits of the CPU data
bus when RD ATTR signal from D25-9 to D71-19
goes low.
7.3
SYNCHRONIZATION GENERATOR
7.3.1
CRT CONTROLLER (CRTC)
The CRTC D49, allows programming of terminal
sync characteristics by loading the control-
ler's internal registers. The registers which
controls these parameters
are addressed via
the address lines AO through A3 and are loaded
via the 8-bit wide CPU data bus. The CRTC
is
selected for loading By D36, the WRITE decoder
in the Processor section using the addresses
3000-300F Hex.
Data in the internal
registers of the CRTC
determines the number of display rows (24 data
rows and 1 status row), the number of columns
(80 or 132), the number of scan lines per dis-
play row (10). The number of scan
lines
per
frame is altered for 50 or 60 Hz.
Advertisement
Chapters
Table of Contents
Troubleshooting
