Non-Maskable Interrupt - Facit 4431 Service Instruction

7.3.4 NON-MASKABLE INTERRUPT
To make the display as versatile as possible,
the processor updates the row start address for
every character row, each character row has 10
scan lines, and consequently a NON-MASKABLE
INTERRUPT (NMI) is generated every 10 scan
lines. If smooth scroll is selected, and a
scrolling window is defined, extra NMis may be
required.
7.3.4.1 Non-smooth scroll or full screen win-
dow
The vertical sync pulse is used as real time
reference in updating the display. Therefore,
upon power-up, the processor looks for the ver-
tical sync pulse, which is read in through the
latch D43. Once the Vertical sync pulse posi-
tion is established the processor will be ready
to process the NMis. To avoid the possibility
of the processor having to process the NMI
before the vertical sync is established, the
NMI is disabled by the signal KILL INT at D20-5
which is set high by writing to the EAROM latch
D64. When the vertical sync is determined this
signal is removed, enabling the NMI.
The negative going vertical sync pulse appears
at D5-8. It is ANDed with the carry pulse from
the scan line counter D21-12 in D7. This ensu-
res that whenever the refresh memory is scan-
ning the 10th scan line of any character row,
the processor will be ready to update the row
address, and also loads D30 with information
about wheter the row needs to be blanked, if it
is a double wide or high row, and if it is the
TOP or BOTTOM half of the row. Incidentally,
this also loads information about the extra
interrupt used in case of smooth scroll which
is described in Section 7.3.4.2.
The column counters are loaded with the row ad-
dress values whenever the Blank signal from the
CRTC is active, which indicates the screen is
in the retrace period. This resets the column
counters to address of the first character po-
sition on the row for every scan line and the
column counters count up to the last column on
the line. When the register D30 is loaded with
four bits of information from the data bus, the
other four bits are used to load the scan line
count into the 74LS192 (D21) in the Video Gene-
rator section. In the case of non-smooth scroll
this will always be zero.
The new row start address is written during the
horizontal blanking period which guarantees
that the screen will not be disturbed. When the
processor, under software control, has set up
the address and data information for D29, D30
and D21, a WRITE operation is attempted. At
this point the 74LS138 (D2), enables the output
pin 9 thus resetting the F/F D31 which in turn
causes D32-6 to go low and place the processor
in a WAIT state. The WAIT state ensures that
the address and data lines will have had time
to settle, and that the new row start address
is not written before the horizontal blanking
interval at the end of scan line 10.
19
The WRITE pulse appears at D36-9, and after
buffering in D24 is gated with the BLANK signal
delayed by two character times in D23-9,10. It
then emerges at D23-8 as the write pulse that
strobes the scan line counter D21-11, and the
registers D30-11 and D29-11 latching the new
scan line count and the row start address. The
horizontal blanking pulse is generated at D49-
17 as a positive going BLANK SIGNAL and is
latched into the octal latch D46-17, by the
character rate clock MEMSHARE signal. The out-
put of the latch D46-16 is the BLANK signal
delayed by one character time and is gated with
the BLANK signal at D22-1,2 to load the column
counters D12, D11, and D28 in the sync. genera-
tor circuitry with the new row start address.
The BLANK pulse delayed by one character time,
is also used as an input to the octal latch D46
-17 to generate a BLANK signal that is delayed
by two character times at D46-19. This signal
is used to gate the write pulse at D23-9 and
also to disable the line decoder D16. Thus the
output D16-9 will go high and remove the reset
from F/F D31, and the rising edge of the next
MEMSHARE pulse will terminate the WAIT state.
Figure 7.3 shows the various BLANK signals,
the write row start register signal and the
load column counter signal.
D49-17
BLANK
BLANK DELAYED BY
ONE CHAR.
POSITION
D23-3
PARALLEL LOAD
COL. COUNTERS.
D46-19
BLANK DELAYED
BY TWO CHAR.
POSITIONS.
D23-8
WRITE TO ROW START
LATCHES
&
SCAN LINE
COUNTER
L
.____ __ J
CLK TO D21-5
~
u:,
I I
.. u
D23-8
t
RELEASE TIME DEPENDS
ON WHEN THE PROCESSOR
RESPONDS TO WAIT STATE
BEING TAKEN AWAY WHICH
IS SYNCHRONIZED WITH
MEMSHARE SIGNAL.
FIG 7.3 SIGNALS GENERATED DURING BLANKING