Single Wide Characters; Double Wide Characters; Double High Characters; Effect Of The Attribute Bits - Facit 4431 Service Instruction

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7.4.3.1 Single wide characters
The "A, 0" inputs are selected for the multi-
plexer in case of single wide characters. The
dot clock from D23-6 is given to D22-14 and the
output D22-12 drives the video shift registers.
The sixth half dot jam pulse from D7-11, which
occurs every character cycle is input to D22-11
and the corresponding output at D22-9 is used as
the parallel load input to the shift registers.
Note that the shift clock to these two parallel
to serial shift registers D39 and D38 are inver-
ted. Four bits of the character generator D40,
go to D39 and three interleaved bits go to D38.
It is to be noted that the rising edge of the
load pulse is synchronized with the falling edge
of the shift clock for D39 and therefore, there
is a half clock time before data is shifted out.
Also, D39 is the first one to shift out data and
half a dot clock later D38 is shifted. This im-
plements a half dot shift in the character com-
position.
7.4.3.2 Double wide characters
For the terminal to produce double wide charac-
ters, the dot rate clock must be divided by 2
and where, in single wide characters, the jams
came every 610nS (80 column mode) or 410nS (132
column mode) respectively, they must now occur
every 1.22 microseconds or 820 nanoseconds. The
double wide characters mode is selected by wri-
ting to the latch D30. The Data bus bits D37 and
D39 determine double wide characters and these
bits are ORed in D20-9,10. The output of D20-8
is used to select the AO or A1 inputs to the
multiplexer D22. The A1 set of inputs are enab-
led in the case of double wide characters.
The half dot clock frequency signal from D4-12,
is used as the clock input to the multiplexer at
D22-13; the jam pulse is needed only every other
character cycle and this signal is obtained from
D7-8 and is input to the multiplexer at D22-10.
These signals follow the same gating as in the
case of the single wide characters. As a result,
the data in the shift registers takes twice as
long to clock out in double wide mode as in
single wide mode, resulting in double wide cha-
racters.
7.4.3.3 Double high character
The scan-line circuitry uses -two normal charac-
ter rows (two screen memory locations per cha-
racter) to produce the complete double high
charcters. The operation of the scan line coun-
ter D21 is discussed in the sync generator por-
tion. Since the operation of the 4431 requires
characters to be double high double wide, or
single high double wide, the scan count outputs
of the 74LS192 (D21) have to be modified to
allow the double high characters to be formed.
The outputs of 021 go to the address inputs
A1,A2 A4, and A8 of 019 the 74LS288 bipolar ROM.
The A16 input 019-14, can be considered as the
double high input. This signal comes from D35-3,
which is selected for double high operation by
writing to D30.
When single high characters are being formed,
the outputs DO through D3 (pin 1,2,3,4) of D19
are mirrored by the outputs D37 through D18 (pin
5,6,7 and 9). Also, these are one to one corres-
pondents of the outputs of D21. If double high
characters are selected by a logical 1 at D19-14
the DO through D3 outputs of D19 follow the out-
puts of D21 at half the rate. Therefore, if the
DO through 03 are allowed through the multiplex-
er D18, to the character generator, only the top
half of a character would be displayed over the
entire 10 scan lines of row space. If the select
input of the multiplexer D18-1 is pulled high by
D30-15, to display the bottom half of the cha-
racter, · then, outputs D4 through D7 are a 11 owed
through 07 which translates the D9 outputs from
count 5 to 9 over the 10 scan lines.
7.4.3.4 Effect of the attribute bits
The serial outputs of the video shift registers
at D39-9 and 038-9 are ORed together in D44-4,5
and the video output at D44-6 is modified by the
various attribute information.
Four video attributes are supported by the 4431,
viz., REVERSE VIDEO, INTENSITY, BLINK, and UN-
DERLINE on a character by character basis. This
information is retrieved from the Refresh Dis-
play Memory and is latched into D46. This infor-
mation forms a part of the address to the attri-
bute PROM D13.
Another set of inputs to this PROM consists of
the screen attributes, viz., SCREEN BACKGROUND
which determines whether dark or bright back-
ground is in effect, CURSOR TYPE which selects
line or block cursor, CURSOR BLINK which blinks
the cursor at the selected frequency, and the
CHARACTER BLINK which blinks the character at
the selected frequency. These attributes are
written to the latch D54 by the processor and
the outputs of this latch form a set of inputs
to the attribute PROM.
To display the Underline for the displayed cha-
racter, scan line 8 is decoded from the scan
line multiplexer D18, using the AND gate D37
(D37-11=LINE 8) and is fed to D57-22.
The cursor bit which originates from the row and
column comparators within the CRTC is latched in
'to D41 and becomes an address for the Attribute
PROM. The Attribute PROM acts as a large combi-
national circuitry and outputs five bits of in-
formation based on its inputs. These attributes
form the inputs to the Attribute latch 058. The-
se attributes are latched in when the jam pulse
loads the parallel data into the video shift re-
gisters.