Dot Oscillator; Memory Share Signal - Facit 4431 Service Instruction

After initialization of the CRTC on power up,
positive horizontal sync pulses, with duration
of about 8 microseconds, will be visable at
D49-15 every 64 microseconds. Positive verti-
cal sync pulses, with a duration of about 200
microseconds. appear at D49-11. The data row
counter outputs (DRO-DR4), the character coun-
ter outputs (HO-H7), and the scan counter out-
puts (RO-R3) are generally not used for dis-
playing the characters on the screen. However,
some of these signals are used in generating
the non-maskable interrupt at the appropriate
time as described in Section 7.3.4.
7.3.2 DOT OSCILLATOR
The Dot oscillator D8, provides timing infor-
mation for the video portion of the Facit 4431
a 9.828MHz oscillator is used in 80 column
mode and a 14.976MHz oscillator in 132 column
mode. The appropriate oscillator is enabled by
D5-6, whose input is determined by the MSB of
data word written into the octal latch 74LS273
D64,(see Section 7.2.4 for details about wri-
ting to this latch).
The buffered output at D23-6, is the basic dot
clock for the video section, and is passed as
the input to the modulo 12 counter D4. Since
each character is six dots wide a jam pulse is
caused to occur every sixth dot by ANDing the
A (pin12) and C (pin9) outputs of the counter
in D33-9,10, this pulse is then chopped to one
half its width by the dot clock in D7 and the
output is used in the video generator section
for single and double width character display.
Since in the double wide character mode this
pulse is required only every other character
position, D7-11 is inverted by D45 and gated
with the LSB of the column counter D28-14, in
D7-9,10. Thus, at D7-8, we have a negative
going pulse one dot wide for every chararcter
position.
In addition to the selection of the proper os-
cillator, a change between 132 and 80 chararc-
ters per row requires a different set of para-
meters to be loaded into the CRT controller,
which is handled by the terminal firmware.
17
7.3.3 MEMORY SHARE SIGNAL
The screen refresh memory is accessed in a
transparent manner. This requires that one
half of the character time be devoted to CPU
access, and the other half to the refresh me-
mory circuitry. To synchronize the various
events, a signal called "MEMSHARE", (MEMSH
&
MEMSH(L) on schematic),is generated which acts
as the basic character clock for the CRTC. One
cycle of MEMSHARE has a duration of six dot
clock cycles and is generated as the output of
D5-12, which is the inverted (A and B) or C
signal of the A, B and C outputs of the 7492
counter D4. The inverted MEMSHARE (MEMSH(L)
signal at D20-3 is used in reading the ASCII
data and attributes from the display memory.
The rising edge of the MEMESHARE signal se-
lects the address multiplexors D27, D10, and
D13 to enable the CPU to access memory. At the
same time it increments the column counters
D28, D11 and D12 in preparation for displaying
one scan line of the next character on the
screen.
Since the CPU and the MEMSHARE circuitry are
operationg with two entirely different clocks,
any attempt by the CPU to write to the display
memory while the multiplexors are switching
over should be prevented. For this reason a
signal called OK TO WRITE (OK WR) is generated
which will restrict CPU access to the memory
to the proper time intervals.
The divide by 2 output of the modulo 12 coun-
ter D4-12, is used as the clock signal for
double wide characters and in generating the
OK WR signal.
The OK WR signal is generated as the Q NOT
output of the F/F D3. When this signal goes
low it allows the processor to write to the
RAM memory. The MEMSHARE signal keeps the OK
WR signal high during the refresh portion by
keeping the F/F in reset state. This signifies
that the display RAM is inaccessible by the
CPU during the refresh portion of the MEMSHARE
signal. When the MEMSHARE goes high indicating
CPU access, the OK WR goes low only after one
dot clock delay (one third into the CPU por-
tion of MEMSHARE). This delay ensures that the
multiplexers will have enough time to switch
over.
Note, Section 7.2.4 describes how this signal
is used with the CPU for writing into the
display memory.
Fig 7.2 illustrate the timing signals derived
in the sync generator circuitry.