Micro-Processor Control Uniti - Facit 4431 Service Instruction

14
7 DETAILED FUNCTIONAL DESCRIPTION _ _ _ _ _ _ _ _ _ _ _ _ _ _
1/0 PORTS
SET-UP MODE
- - - - - - - - - - - - - - PRINTER
~.---1-/D-~
- - -
-1
EAR OM
PROGRAM
ROM
(12k x 8)
SCREEN MAP RAM
VIDEO
ATT
(4k
x
4)
1/0 LOGIC
AND SIO
~~M~~~
!
2k
t - - - - - - - - - . - - - - C _ P U _ B u _ s _ _ _ _
~-----~
INTERFACE IRAM
CHARACTER GENERATOR ROM
I
EXTENDED
STANDARD
1
(OPTIONAL)
DISPLAY
GENERATOR
SYNC
GEN'R_
KEYBOARD
UART
L _________________ _
_ _ _ _ _ _ _J
VIDEO SYNC
SERIAL
ASCII
, - ----- 11--
---~LLAN~
I I I
~-~-~ KEYCLICKER
I
KEYBOARD
VIDEO COMBINER CIRCUIT
I I
LOGIC AND
I I I
ENCODER
L ________ _JI
COMPOSITE
VIDEO OUTPUT
I
I
I
;E\Y~~~~~x KEYBOARD
LEDs
I I
L _________ J
FIG 7. 1
Functional Block Diagram
7.1
MICRO-PROCESSOR CONTROL UNIT
Familiarity with microprocessor terminology and
procedures is necessary for understanding this
section. Specific knowledge of the Z80A proces-
sor is desirable but not absolutely essential.
The Facit 4431 uses a Z80A microprocessor (D42)
to control all terminal operations based on the
instructions contained in the program EPROMs
(D73,74,75). The processor has access to all
memory and I/0 mapped devices on the bus, in-
cluding the 2k scratchpad RAM (D72), the Z80
SIO (D48-DART-)and CTC (D50) (see section 7.5),
the EAROM (D63), various hardware latches, and
under control of the bus arbitration circuitry,
the display refresh RAM (051,52) and the attri-
bute RAM (D68,69,67 and D66).
Address decoding for all devices exept the pro-
gram EPROMs and display refresh memory is pro-
vided by D36 (write) and 015 (read). Address
decoding for program EPROMs is described in
section 7.1.3 , and decoding for the display
refresh RAM is described in section 7.2.
7.1.1 CPU CLOCK
Crystal B3 and D9 (a 74LSOO NANO gate) are used
to generate the 4MHz., 50% duty cycle system
clock signal for the microprocessor and the
other Z80 family chips. Transistor V101 provi-
des an active pull-up for the clock by taking
the normal TTL level (which ranges from 3.6 to
4 volts) and pulling it up to full 5 volts,
while maintaining the standard TTL rise time.
(Z80 family chips other than the processor are
discussed in section 7.3 of this manual.)
7.1.2 POWER ON RESET
During power up it is necessary to hold the
reset pin of the Z80 family chips at the logi-
cal 0 level until the 5 Volt power supply is
stabilized to insure that the microprocessor
begins executing instructions at address 0, and
that the Z80 peripheral chips are reset to a
known state. After the 5 volt supply has stabi-
1 i zed, this reset line must rize cleanly.