Video Generator - Facit 4431 Service Instruction

12
• provide shift and load commands to the
video shift registers.
• interrupt the Z80A every vertical retrace,
and every 10 horizontal scans to request
row start information.
The Sync
80 and
troll er,
tor, and
lexer.
CPU
DATA
BUS
CONTROL
FROM
(SG) & (P)
ASCII
DATA
FROM
(M)
ATTR DATA
FROM
(M) & (
SG
)
Generator circuitry consists of the
132 column dot oscillators, CRT Con-
Interrupt Generator, MEMSHARE Genera-
the Refresh Address Generator/Multip-
.L •
SCAN LINE
8 ..
COUNTER
&
CONTROL
..
D18,19,21
.
ASCII
LATCH
.
8 ..
D41
ATTR
LATCH
..
..
D46
CONTROL
FROM
(SG)
t---
4 __..
...
CHARACTER
8 __..
GENERATOR
...
D40
.
-' - - 1
-
ATTR !BUTE
5
GENERATOR
--'
r
SCREEN
AHR.CONTROL
FROM (M)
&
(SG)
[)57
5
6.4 VIDEO GENERATOR
The Video Generator circuit uses the outputs
of the Sync generator and the display memory
circuits to create the appropriate video sig-
nals for each character to be displayed. The
ASCII character code from the display memory,
the scan line count, and the double high/doub-
le wide control lines are combined to generate
the address in the character generator EPROM
where the dot pattern for the character to be
displayed is stored. The dot pattern is then
converted to serial form by the video shift
registers and combined with the attribute data
before geing sent to the monitor. A block dia-
gram of the Video Generator is shown in Fig 6.4.
Z80 A DATA BUS
P)
l
FROM (
l
VIDEO
DIGITAL
SHIFT BRIGHTNESS
..
CONTROL CONTROL
D22
D56
y
4
~
-·
VIDEO VIDEO
SHIFT OUTPUT SIGNAL
VIDEO
i--------
REGISTERS
SIGNAL -
GENERATOR
i--.
COMPOS !TE
VIDEO
OUTPUT
D39,38
~5 __. . . .
D60,35,44
ATTR
5
LATCH
--'
t-
058
FIG 6.4
VIDEO GENERATOR