Analog Devices EVAL-AD5933EBZ User Manual page 19

Evaluation Board User Guide
Measuring Lower Excitation Frequencies
The AD5933 has a flexible internal DDS core and a digital-to-
analog converter (DAC) that together generate the excitation
signal used to measure the impedance (Z
has a 27-bit phase accumulator that allows subhertz (0.1 Hz)
frequency resolution. The output of the phase accumulator is
connected to the input of a read-only memory (ROM).The digital
output of the phase accumulator is used to address individual
memory locations in the ROM. The digital contents of the ROM
represent amplitude samples of a single cycle of a sinusoidal
excitation waveform. The contents of each address within the
ROM look-up table are in turn passed to the input of a DAC that
produces the analog excitation waveform made available at the
VOUT pin. The DDS core (that is, the phase accumulator and the
ROM look-up) and the DAC are all referenced from a single system
clock. The function of the phase accumulator is simply to act as
a system clock divider.
The system clock for the AD5933
in one of two ways.
•
The user can provide a highly accurate and stable clock
(crystal oscillator) at the external clock pin, MCLK (Pin 8).
•
Alternatively, the AD5933
with a typical frequency of 16.776 MHz.
The user can select the preferred system clock by programming
Bit D3 in the control register (Address 0x81, see the
data sheet).
The internal ADC also uses the system clock to digitize the
response signal. The ADC requires 16 clock periods to perform
a single conversion. Therefore, with a maximum system clock
frequency of 16.776 MHz, the ADC can sample the response
signal with a frequency of 1.0485 MHz, that is, a throughput
rate of ≈ 1.04 MSPS. The ADC converts 1024 samples and passes
the digital results to the MAC core for processing. The
MAC core performs a 1024 point DFT to determine the peak
of the response signal at the ADC input. The DFT offers many
advantages over conventional peak detection mechanisms,
including excellent dc rejection, an averaging of errors, and
phase information.
The throughput rate of the AD5933
clock, that is, lower ADC throughput rates, and therefore sampling
frequencies can be achieved by lowering the system clock.
The conventional DFT assumes a sequence of periodic input
data samples to determine the spectral content of the original
continuous signal. In the AD5933,
from the 12-bit ADC for a user-defined range of signal frequencies.
). The DDS core
UNKNOWN
DDS engine can be provided
provides an internal clock oscillator
AD5933
AD5933
ADC scales with the system
these samples obviously come
The conventional DFT correlates the input signal against a series
of test phasor frequencies to determine the fundamental signal
frequency and its harmonics. The frequency of the test phasor is
at integer multiples of a fundamental frequency given by the
following formula:
Test Phasor Frequency = (f
where:
f is the sampling frequency of the ADC.
S
N is the number of samples taken equals 1024.
The correlation is performed for each frequency integer
fundamental. If the resulting correlation of the test phasor
with the input sample set is nonzero, there is signal energy at
this frequency. If no energy is found in a bin, there can be no
energy at that test frequency.
The DFT implemented by the
DFT; this means that the analysis or correlation frequency in
the MAC core is always at the same frequency as the current
output excitation frequency. Therefore, when the system clock
for the AD5933
1.04 MHz. The DSP core requires 1024 samples to perform
the single point DFT. Therefore, the resolution of the DFT is
1.04 MHz/1024 points ≈ 1 kHz. This calculation is based on
a system clock frequency of 16 MHz being applied at MCLK. If
the AD5933 tries to examine excitation frequencies below ≈ 1 kHz,
the errors introduced by the spectral leakage become significant
and result in erroneous impedance readings.
If the input signal does not have an exact integer number of cycles
over the 1024-point sample interval, as shown in Figure 26, there
will not be a smooth transition from the end of one period to
the next, as shown in Figure 27. The leakage is a result of the
discontinuities introduced by the DFT assuming a periodic
input signal like that shown in Figure 27.
SAMPLES SPAN ENTIRE EXCITATION PERIOD
Figure 26. Sample Set Spanning the Entire Excitation Period
SAMPLES DO NOT SPAN ENTIRE EXCITATION PERIOD
Figure 27. Sample Set Not Spanning the Entire Excitation Period
Rev. 0 | Page 19 of 28
/N)
S
AD5933 is called a single point
is 16.776 MHz, the sample rate of the ADC is
SAMPLE DFT ASSUMES A PERIODIC
WINDOW SAMPLE SET
DFT ASSUMES A PERIODIC
SAMPLE SET
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