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ARTERY AT32F421 Series Reference Manual

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®
ARM
-based 32-bit Cortex
ADC, 7 communication interfaces
Feature
 Core: ARM®32-bit Cortex®-M4F CPU
− 120 MHz maximum frequency, with a
Memory Protection Unit (MPU), single-cycle
multiplication and hardware division
− DSP instructions
 Memories
− 16 to 64 KBytes of internal Flash memory
− 4 Kbytes of boot code area used as a
Bootloader or as a general instruction/data
memory (one-time-configured)
− sLib: configurable part of main Flash set as a
library area with code executable but
secured, non-readable
− 8 to 16 KBytes of SRAM
 Clock, reset and power control
− 2.4 V ~ 3.6 V application suppy and I/Os
− Power-on reset (POR)/ low-voltage reset
(LVR), and power voltage monitor (PVM)
− 4 to 25 MHz crystal (HEXT)
− Internal 8 MHz factory-trimmed clock (HICK),
accuracy 1% at T
+105 °C
− Internal 40 kHz RC oscillator
− 32 kHz crystal oscillator (LEXT)
 Low power
− Sleep, Deepsleep, and Standby modes
 1 x 12-bit A/D converter (up to 15 input
channels)
− Conversion range: 0 V to 3.6 V
 1 x COMP, 5 x external input channels
and 1 x internal reference voltage
channel
 DMA: 5-channel DMA controller
− Peripherals supported: timers, ADC, I
SPI, I
2
C and USART
 Debug mode
− Serial wire debug (SWD) and JTAG
 Up to 39 fast GPIOs
− All mapable to external interrupt vectors
− Almost 5 V-tolerant
2021.11.17
®
-M4 MCU with 16 to 64 KB Flash, sLib, 10 timers,
=25 °C, 2 % at T
=-40 to
A
A
2
S,
AT32F421 Series Reference Manual
− All fast I/Os, registers accessible with f
 Up to 10 Timers (TMR)
− 1 x 16-bit 7-channel advanced timer, 6-channel
PWM outout with dead-time generator and
emergency stop
− 5 x 16-bit timers, each with 4 IC/OC/PWM or
pulse counter and encoder input
− 1 x 16-bit basic timer
− 2 x Watchdog timers (WDT and WWDT)
− SysTick timer: 24-bit downcounter
 ERTC: enhanced RTC
 Up to 7 communication interfaces
− 2 x I
2
C interfaces (SMBus/PMBus support)
− 2 x USARTs/UART (ISO7816 interface, LIN,
IrDA and modem control)
− 2 x SPIs, both with I
− Infrared transmitter
 CRC Calculation Unit
 96-bit ID (UID)
 Packaging
− LQFP48 7 x 7 mm
− LQFP32 7 x 7 mm
− QFN32 5 x 5 mm
− QFN32 4 x 4 mm
− QFN28 4 x 4 mm
− TSSOP20 6.5 x 4.4 mm
 List of Models
Internal Flash
AT32F421C8T7, AT32F421K8T7
64 KBytes
AT32F421K8U7, AT32F421K8U7-4
AT32F421F8P7, AT32F421G8U7
AT32F421C6T7, AT32F421K6T7
32 KBytes
AT32F421K6U7, AT32F421K6U7-4
AT32F421F6P7, AT32F421G6U7
AT32F421C4T7, AT32F421K4T7
16 KBytes
AT32F421K4U7, AT32F421K4U7-4
AT32F421F4P7, AT32F421G4U7
Page 1
speed
AHB
2
S interface multiplexed
Model
Ver 2.00

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Summary of Contents for ARTERY AT32F421 Series

  • Page 1 AT32F421 Series Reference Manual ® ® -based 32-bit Cortex -M4 MCU with 16 to 64 KB Flash, sLib, 10 timers, ADC, 7 communication interfaces Feature  Core: ARM®32-bit Cortex®-M4F CPU − All fast I/Os, registers accessible with f speed − 120 MHz maximum frequency, with a ...

  • Page 2: Table Of Contents

    AT32F421 Series Reference Manual Contents System architecture ..............24 System overview ................26 1.1.1 ARM Cortex -M4 processor ............26 1.1.2 Bit band ..................26 1.1.3 Interrupt and exception vectors ............ 28 1.1.4 System Tick (SysTick) ..............30 1.1.5 Reset ..................30 List of abbreviations for registers ..........
  • Page 3 AT32F421 Series Reference Manual 4.1.1 Clock sources ................44 4.1.2 System clock ................45 4.1.3 Peripheral clock ................45 4.1.4 Clock fail detector ............... 46 4.1.5 Auto step-by-step system clock switch .......... 46 4.1.6 Internal clock output ..............46 4.1.7 Interrupts ..................46 Reset ..................
  • Page 4 AT32F421 Series Reference Manual 5.4.1 Unlock/lock ................. 65 5.4.2 Erase operation ................66 5.4.3 Programming operation..............67 5.4.4 Read operation ................68 Flash memory protection .............. 68 5.5.1 Access protection ................ 68 5.5.2 Erase/program protection............. 69 Special functions ................. 69 5.6.1 Security library settings ...............
  • Page 5 AT32F421 Series Reference Manual Introduction ................. 79 Functional overview ..............79 6.2.1 GPIO structure ................79 6.2.2 GPIO reset status ................ 79 6.2.3 General-purpose input configuration ..........80 6.2.4 Analog input/output configuration ..........80 6.2.5 General-purpose output configuration ........... 80 6.2.6 GPIO port protection ..............
  • Page 6 AT32F421 Series Reference Manual 7.2.5 SCFG external interrupt configuration register4 (SCFG_ EXINTC4) 91 External interrupt/Event controller (EXINT) ........92 EXINT introduction ............... 92 Function overview and configuration procedure ......92 EXINT registers ................93 8.3.1 Interrupt enable register (EXINT_INTEN) ........93 8.3.2 Event enable register (EXINT_EVTEN) .........
  • Page 7 AT32F421 Series Reference Manual 10.1 CRC introduction ............... 104 10.2 CRC registers ................104 10.2.1 Data register (CRC_DT).............. 104 10.2.2 Common data register (CRC_CDT) ..........104 10.2.3 Control register (CRC_CTRL) ............105 10.2.4 Initialization register (CRC_IDT) ..........105 C interface ................106 11.1 I...
  • Page 8 AT32F421 Series Reference Manual 12.5 DMA transfer introduction ............130 12.5.1 Transmission using DMA ............130 12.5.2 Reception using DMA ..............130 12.6 Baud rate generation ..............131 12.6.1 Introduction................131 12.6.2 Configuration ................131 12.7 Transmitter ................132 12.7.1 Transmitter introduction .............. 132 12.7.2 Transmitter configuration ............
  • Page 9 AT32F421 Series Reference Manual 13.2.7 Transmitter ................147 13.2.8 Receiver ..................147 13.2.9 Motorola mode ................148 13.2.10 Interrupts ................150 13.2.11 IO pin control ................151 13.2.12 Precautions ................151 13.3 I2S functional description ............151 13.3.1 I S introduction ................151 13.3.2 Operation mode selector .............
  • Page 10 AT32F421 Series Reference Manual 14.1.4 TMR6 registers ................166 14.1.4.1 TMR6 control register1 (TMRx_CTRL1) ........167 14.1.4.2 TMR6 control register2 (TMRx_CTRL2) ........167 14.1.4.3 TMR6 DMA/interrupt enable register (TMRx_IDEN) ....167 14.1.4.4 TMR6 interrupt status register (TMRx_ISTS) ......168 14.1.4.5 TMR6 software event register (TMRx_SW EVT) ......168 14.1.4.6 TMR6 counter value (TMRx_CVAL) ........
  • Page 11 AT32F421 Series Reference Manual 14.3 General-purpose timer (TMR14) ..........190 14.3.1 TMR14 introduction ..............190 14.3.2 TMR14 main features ..............190 14.3.3 TMR14 functional overview ............190 14.3.3.1 Count clock ................190 14.3.3.2 Counting mode ..............191 14.3.3.3 TMR input function ..............192 14.3.3.4 TMR output function ..............
  • Page 12 AT32F421 Series Reference Manual 14.4.4.6 TMR15 software event register (TMR15_SW EVT) ....212 14.4.4.7 TMR15 channel mode register1 (TMR15_CM1) ......212 14.4.4.8 TMR15 channel control register (TMR15_CCTRL) ....215 14.4.4.9 TMR15 Counter value (TMR15_CVAL) ........217 14.4.4.10 TMR15 Division value (TMR15_DIV ) ........217 14.4.4.11...
  • Page 13 AT32F421 Series Reference Manual 14.6 Advanced-control timers (TMR1) ..........235 14.6.1 TMR1 introduction ..............235 14.6.2 TMR1 main features ..............235 14.6.3 TMR1 functional overview ............235 14.6.3.1 Count clock ................235 14.6.3.2 Counting mode ..............237 14.6.3.3 TMR input function ..............240 14.6.3.4 TMR output function ..............
  • Page 14 AT32F421 Series Reference Manual 15.4 Debug mode ................260 15.5 WWDT registers ................ 260 15.5.1 Control register (WWDT_CTRL) ..........260 15.5.2 Configuration register (WWDT_CFG) ........... 261 15.5.3 Status register (WWDT_STS) ............261 Watchdog timer (WDT) ..............262 16.1 WDT introduction ............... 262 16.2 WDT main features ..............
  • Page 15 AT32F421 Series Reference Manual 17.4.7 ERTC write protection register (ERTC_WP) ......... 274 17.4.8 ERTC subsecond register (ERTC_SBS) ........274 17.4.9 ERTC time adjustment register (ERTC_TADJ) ......274 17.4.10 ERTC time stamp time register (ERTC_TSTM) ......274 17.4.11 ERTC time stamp date register (ERTC_TSDT) ......275 17.4.12 ERTC time stamp subsecond register (ERTC_TSSBS) ....
  • Page 16 AT32F421 Series Reference Manual 18.5.3 ADC control register2 (ADC_CTRL2) ........... 287 18.5.4 ADC sampling time register 1 (ADC_SPT1) ........289 18.5.5 ADC sampling time register 2 (ADC_SPT2) ........290 18.5.6 ADC preempted channel data offset register x (ADC_ PCDTOx) (x=1..4) ..............292 18.5.7 ADC voltage monitor high threshold register (ADC_VWHB) ...
  • Page 17 AT32F421 Series Reference Manual 21.4.1 DEBUG device ID (DEBUG_IDCODE) .......... 303 21.4.2 DEBUG control register (DEBUG_CTRL) ........304 Revision history ................306 2021.11.17 Page 17 Ver 2.00...
  • Page 18 AT32F421 Series Reference Manual List of figures Figure 1-1 AT32F421 Series microcontrollers system architecture..............25 Figure 1-2 Internal block diagram of Cortex ® -M4 ..................26 Figure 1-3 Comparison between bit-band region and its alias region: image A ......... 26 Figure 1-4 Comparison between bit-band region and its alias region: image B .........
  • Page 19 AT32F421 Series Reference Manual Figure 13-7 Slave full-duplex communications..................149 Figure 13-8 Slave full-duplex communications..................149 Figure 13-9 Slave half-duplex receive ....................... 149 Figure 13-10 Slave half-duplex transmit ....................150 Figure 13-11 Master half-duplex receive ....................150 Figure 13-12 SPI interrupts ........................150 Figure 13-7 I S block diagram ........................
  • Page 20 AT32F421 Series Reference Manual Figure 14-32 Block diagram of general-purpose TMR14 ................190 Figure 14-33 Counter timing diagram, CK_INT divided by 1 ..............190 Figure 14-34 Counter timing with prescaler value changing from 1 to 4 ..........191 Figure 14-35 Overflow event when PRBEN=0 ..................191 Figure 14-36 Overflow event when PRBEN=1 ..................
  • Page 21 AT32F421 Series Reference Manual Figure 14-77 Block diagram of external clock mode A ................236 Figure 14-78 Counter timing in external clock mode A ................236 Figure 14-79 Block diagram of external clock mode B ................236 Figure 14-80 Counter timing in external clock mode B ................237 Figure 14-81 Counter timing with prescaler value changing from 1 to 4 ..........
  • Page 22 Table 1-1 Bit-band address mapping in SRAM ................... 27 Table 1-2 Bit-band address mapping in the peripheral area ............... 28 Table 1-3 AT32F421 series vector table ...................... 28 Table 1-4 List of abbreviations for registers ....................32 Table 1-5 List of abbreviations for registers ....................32 Table 2-1 Flash memory organization (64 KB) ....................
  • Page 23 AT32F421 Series Reference Manual Table 14-8 Standard CxOUT channel output control bit ................198 Table 14-9 TMR15 internal trigger connection ..................200 Table 14-10 TMR10 register map and reset value ..................208 Table 14-11 Complementary output channel CxOUT and CxCOUT control bits with break function ..216 Table 14-12 TMR16 and TMR17 register map and reset value ..............

  • Page 24: System Architecture

    AT32F421 Series Reference Manual 1 System architecture ® ® AT32F421 series microcontrollers incorporates a 32-bit ARM Cortex -M4 processor core, multiple 16- bit and 32-bit timers, DMA controller, ERTC, communication interfaces such as SPI, I2C, USART, CMP, 12-bit ADC, programmable voltage monitor (PVM) and other peripherals. Cortex ®...

  • Page 25: Figure 1-1 At32F421 Series Microcontrollers System Architecture

    AT32F421 Series Reference Manual Figure 1-1 AT32F421 Series microcontrollers system architecture HEXT 4~25MHz HICK 48/8MHz Cortex-M4 Max. 120MHz (Freq. Max. 120MHz) FCLK HCLK PCLK1 NVIC PCLK2 Flash 64KB @VDD 5Channel Controller Flash POR/LVR GPIOA/B SRAM 16KB /C/F Controller SRAM LDO 1.2V...

  • Page 26: System Overview

    AT32F421 Series Reference Manual 1.1 System overview 1.1.1 ARM Cortex -M4 processor Cortex ® -M4 processor is a low-power consumption processor featuring low gate count, low interrupt latency, and low-cost debug. It supports DSP instruction set, particularly applicable to deep-embedded applications that require quicker response to interrupts.

  • Page 27: Figure 1-4 Comparison Between Bit-Band Region And Its Alias Region: Image B

    AT32F421 Series Reference Manual Figure 1-4 Comparison between bit-band region and its alias region: image B bitband alias region (total 32M bytes) 0x23FF_FFFC 0x23FF_FFF8 0x23FF_FFF4 0x23FF_FFF0 0x23FF_FFEC 0x23FF_FFE8 0x23FF_FFE4 0x23FF_FFE0 0x2200_001C 0x2200_0018 0x2200_0014 0x2200_0010 0x2200_000C 0x2200_0008 0x2200_0004 0x2200_0000 bitband region...

  • Page 28: Interrupt And Exception Vectors

    When it comes to multiple taks, it turns the read-modify-write operations into a hardware-supported atomic operation to avoid the scenario where the read-modify-write opearion is disrupted, resulting in disorder. 1.1.3 Interrupt and exception vectors Table 1-3 AT32F421 series vector table Priority Pos. Priority Name Description...
  • Page 29 AT32F421 Series Reference Manual Configur UsageFault Undefined instruction or illegal state 0x0000_0018 able 0x0000_001C Reserved ~0x0000_002B Configur SVCall Call system service via SWI instruction 0x0000_002C able Configur DebugLENonitor Debug monitor 0x0000_0030 able Reserved 0x0000_0034 Configur PendSV Pendable request for system service...

  • Page 30: System Tick (Systick)

    AT32F421 Series Reference Manual Configur TMR15 TMR15 global interrrupt 0x0000_0090 able Configur TMR16 TMR16 global interrrupt 0x0000_0094 able Configur TMR17 TMR17 global interrrupt 0x0000_0098 able Configur I2C1_EVT 0x0000_009C C1 event interrupt able Configur I2C2_EVT 0x0000_00A0 C2 event interrupt able Configur...

  • Page 31: Figure 1-6 Example Of Msp And Pc Initialization

    0x0000_0000 0x2000_8000 In the AT32F421 series, the main Flash memory, Boot code or SRAM can be remapped to the code area between 0x0000_0000 and 0x07FF_FFFF. nBOOT1 corresponds to the system configuration byte nBOOT1 of the User Sysem Data area. BOOT0 and nBOOT1 are used to determine the specific memory from which CODE starts.

  • Page 32: List Of Abbreviations For Registers

    AT32F421 Series Reference Manual 1.2 List of abbreviations for registers Table 1-4 List of abbreviations for registers Register type Description Software can read and write to this bit. Software can only read this bit. Software can only write to the bit. Reading it returns its reset value.

  • Page 33: Memory Resources

    AT32F421 Series Reference Manual Abbr. Reset value Type Description Bit 31: 0 UID[95: 64] 0xXXXX XXXX UID for bit 95 to bit 64 Note: UID[95:88] is series ID, which is 0x09 for AT32F421. 2 Memory resources 2.1 Internal memory address map Internal memory contains program memory (Flash), data memory (SRAM), peripheral registers and core registers.

  • Page 34: Flash Memory

    AT32F421 Series Reference Manual 2.2 Flash memory AT32F421 series provide up to 64 KB of on-chip Flash memory, supporting a single-cycle 32-bit read operation. Refer to Chapter 5 for more details about Flash memory controller and register configuration. Flash memory organization (64 KB) The main memory contains only bank 1 (64 Kbytes), including 64 pages, 1 Kbyte per page.

  • Page 35: Peripheral Address Map

    AT32F421 Series Reference Manual 2.4 Peripheral address map Table 2-4 Peripheral boundary address Boundary address Peripherals 0x6000 0000 - 0xFFFF FFFF Reserved 0x5004 0000 - 0x5FFF FFFF Reserved 0x5000 0000 - 0x5003 FFFF Reserved 0x4800 1800 – 0x4FFF FFFF Reserved...
  • Page 36 AT32F421 Series Reference Manual Boundary address Peripherals 0x4001 3C00 - 0x4001 4BFF Reserved 0x4001 3800 - 0x4001 3BFF USART1 0x4001 3400 - 0x4001 37FF Reserved 0x4001 3000 - 0x4001 33FF SPI1/I 0x4001 2C00 - 0x4001 2FFF TMR1 timer 0x4001 2800 - 0x4001 2BFF...
  • Page 37 AT32F421 Series Reference Manual Boundary address Peripherals 0x4000 2000 - 0x4000 23FF TMR14 timer 0x4000 1C00 - 0x4000 1FFF Reserved 0x4000 1800 - 0x4000 1BFF Reserved 0x4000 1400 - 0x4000 17FF Reserved 0x4000 1000 - 0x4000 13FF TMR6 timer 0x4000 0C00 - 0x4000 0FFF...

  • Page 38: Power Control (Pwc)

    3 Power control (PWC) 3.1 Introduction For AT32F421 series, its operating voltage supply is 2.6 V ~ 3.6 V, with a temperature range of -40~+105 ℃. To reduce power consumption, this series provides three types of power saving modes, including Sleep, Deepsleep and Standby modes so as to achieve the best trade-off among the conflicting demands of CPU operating time, speed and power consumption.The AT32F421 series has two power domains─...

  • Page 39: Por/Lvr

    AT32F421 Series Reference Manual 3.3 POR/LVR A POR analog module embedded in the VDD/VDDA domain is used to generate a power reset. The power reset signal is released at V when the VDD is increased from 0 V to the operating voltage, or it is triggered at V when the VDD drops from the operating voltage to 0 V.

  • Page 40: Power Domain

    AT32F421 Series Reference Manual Figure 3-3 PVM threshold and output DET_P HYS_P 100 mV hysteresis DET_P PVMOF 3.5 Power domain 1.2 V domain 1.2 V core domain includes a CPU core, SRAM, embedded digital peripherals and Phase Locked Loop (PLL). Such power domain is supplied by LDO (voltage regulator).
  • Page 41 AT32F421 Series Reference Manual 2) If the WFE is executed to enter Sleep mode, the MCU exits Sleep mode as soon as an event occurs. The wakeup event can be generated by the following:  Enabling a peripheral interrupt (it is not enabled in the NVIC) and enabling the SEVONPEND bit.

  • Page 42: Pwc Registers

    AT32F421 Series Reference Manual 3.7 PWC registers The peripheral registers must be accessed by words (32 bit) Table 3-1 PW register map and reset values Register abbr. Offset Reset value PWC_CTRL 0x00 0x0000 0000 PWC_CTRLSTS 0x04 0x0000 0000 PWC_CTRL2 0x20 0x0000 00XX 3.7.1...

  • Page 43: Power Control/Status Register (Pwc_Ctrlsts)

    AT32F421 Series Reference Manual 3.7.2 Power control/status register (PWC_CTRLSTS) Unlike a standard APB read, an additional APB cycles are needed to read this register. Name Reset value Type Description Bit 31: 15 Reserved 0x000000 resd Kept at its default value.

  • Page 44: Clock And Reset Manage (Crm)

    AT32F421 Series Reference Manual 4 Clock and reset manage (CRM) 4.1 Clock AT32F421 series provide different clock sources: HEXT oscillator clock, HICK oscillator clock, PLL clock, LEXT oscillator and LICK oscillator. Figure 4-1 AT32F421 clock tree Peripheral 12S1/2 CLK clock enable...

  • Page 45: System Clock

    AT32F421 Series Reference Manual VCO frequency is output after being divided by post-scaler. Among them, the pre-scaler clock must be a range of between 2 M and 16 MHz, whiel the VCO operating frequency must be a range of between 500 MHz and 1000 MHz.

  • Page 46: Clock Fail Detector

    If a failure is detected on the HEXT clock, the CFD interrupt is generated. Such interrrpt is directly linked to CPU NMI. 4.2 Reset 4.2.1 System reset AT32F421 series provide the following system reset sources:  NRST reset: on the external NRST pin  WDT reset: watchdog overflow ...

  • Page 47: Battery Powered Domain Reset

    AT32F421 Series Reference Manual Figure 4-2 System reset circuit 4.2.2 Battery powered domain reset Battery powered domain has two specific reset sources:  Software reset: triggered by setting the BPDRST bit in the battery powered domain control register (CRM_BPDC) ...

  • Page 48: Clock Control Register (Crm_Ctrl)

    AT32F421 Series Reference Manual 4.3.1 Clock control register (CRM_CTRL) No-wait states, accessible by bytes, half-words or words. Name Reset value Type Description Bit 31: 26 Reserved 0x00 resd Kept at its default value. PLL clock stable This bit is set by hardware after PLL is ready.

  • Page 49: Clock Configuration Register (Crm_Cfg)

    AT32F421 Series Reference Manual 4.3.2 Clock configuration register (CRM_CFG) Name Reset value Type Description Bit 31 Reserved resd Kept at its default value. Clock output selection CLKOUT_SEL[3] is the bit 16 of the CRM_MISC1 register. 0000: None 0001: Reser ved...

  • Page 50: Clock Interrupt Register (Crm_Clkint )

    AT32F421 Series Reference Manual 0xxx: SCLK not divided 1000: SCLK divided by 2 1100: SCLK divided by 64 1001: SCLK divided by 4 1101: SCLK divided by 128 1010: SCLK divided by 8 1110: SCLK divided by 256 1011: SCLK divided by 16 1111: SCLK divided by 512...

  • Page 51: Apb2 Peripheral Reset Register (Crm_Apb2Rst)

    AT32F421 Series Reference Manual 0: No clock failure 1: Clock failure Bit 6: 5 Reserved resd Keep at its default value. PLL stable flag Set by hardware. Bit 4 PLLSTBLF 0: PLL is not ready. 1: PLL is ready. HEXT stable flag Set by hardware.

  • Page 52: Apb1 Peripheral Reset Register1 (Crm_Apb1Rst)

    AT32F421 Series Reference Manual 4.3.5 APB1 peripheral reset register1 (CRM_APB1RST) Access: 0 wait state, accessible by words, half-words and bytes. Name Reset value Type Description Bit 31: 29 Reserved resd Kept at its default value. PWC reset Bit 28 PWCRST...

  • Page 53: Ahb Peripheral Clock Enable Register (Crm_Ahben)

    AT32F421 Series Reference Manual 4.3.6 AHB peripheral clock enable register (CRM_AHBEN) Access: by words, half-words and bytes. Name Reset value Type Description Bit 31: 23 Reserved 0x000 resd Kept at its default value. GPIOF clock enable Bit 22 GPIOFEN 0: Disabled...

  • Page 54: Apb2 Peripheral Clock Enable Register (Crm_Apb2En)

    AT32F421 Series Reference Manual 4.3.7 APB2 peripheral clock enable register (CRM_APB2EN) Access: by words, half-words and bytes. When accessing to peripherals on APB2 bus, wait states are inserted until the completion of the peripheral access on APB2. Name Reset value...

  • Page 55: Apb1 Peripheral Clock Enable Register (Crm_Apb1En)

    AT32F421 Series Reference Manual 4.3.8 APB1 peripheral clock enable register (CRM_APB1EN) Access: by words, half-words and bytes. No-wait states in most cases. However, when accessing to peripherals on APB1, wait-states are inserted until the end of peripheral access on the APB1 bus.

  • Page 56: Battery Powered Domain Control Register (Crm_Bpdc)

    AT32F421 Series Reference Manual 4.3.9 Battery powered domain control register (CRM_BPDC) Access: 0 to 3 wait states, accessible by words, half-words or bytes. Wait states are inserted in the case of consecutive accesses to this register. Note: LEXTEN, LEXTBYPS, ERTCSEL, and ERTCEN bits of the battery powered domain control register (CRM_BPDC) are in the battery powered domain.

  • Page 57: Ahb Peripheral Reset Register (Crm_Ahbrst)

    AT32F421 Series Reference Manual POR/LVR reset flag Sety by hardware. Cleared by writing to the RSTFC bit. Bit 27 PORRSTF 0: No POR/LVR reset occurs 1: POR/LVR reset occurs. NRST pin reset flag Sety by hardware. Cleared by writing to the RSTFC bit.

  • Page 58: Pll Configuration Register (Crm_Pll)

    AT32F421 Series Reference Manual 4.3.12 PLL configuration register (CRM_PLL) Name Reset value Type Description PLL configuration enable 0: Common integer multiplication mode, which is done by PLL_FREF and PLLMULT registers. Bit 31 PLLCFGEN 1: Flexible configuration mode, which is done by LL_MS/PLL_NS/PLL_FR registers.

  • Page 59: Additional Register (Crm_Misc2)

    AT32F421 Series Reference Manual 4.3.14 Additional register (CRM_MISC2) Name Reset value Type Description Bit 31: 10 Reserved 0x000000 resd Kept at its default value. HICK as system clock frequency select When the HICK is selected as the clock source SCLKSEL,...

  • Page 60: Flash Memory Controller (Flash)

    AT32F421 Series Reference Manual 5 Flash memory controller (FLASH) 5.1 FLASH introduction Flash memory is divided into three parts: main Flash memory, information block and Flash memory registers.  Main Flash memory is up to 64 KB Information block consists of 4 KB boot loader and the user system data area. The boot loader ...

  • Page 61: Table 5-4 User System Data Area

    AT32F421 Series Reference Manual Each system data occupies two bytes, where the low bytes corresponds to the contents in the system data area, and the high bytes represent the inverse code that is used to verify the correctness of the selected bit.

  • Page 62: Flash Memory Operation

    AT32F421 Series Reference Manual [31: 24] nEPP3[7: 0]: Inverse code of EPP3[7: 0] [7: 0] Data2[7: 0]: User system data 2 [15: 8] nData2[7: 0]: Inverse code of Data2[7: 0] 0x1FFF_F810 [23: 16] Data3[7: 0]: User system data 3 [31: 24]...

  • Page 63: Figure 5-1 Flash Memory Page Erase Process

    AT32F421 Series Reference Manual Figure 5-1 Flash memory page erase process Start Check the OBF bit in FLASH_STS OBF = 0 ? Write the erased sector address to FLASH_ADDR Set SECERS = 1 and ERSTR =1 in FLASH_CTRL Check the OBF bit in FLASH_STS...

  • Page 64: Programming Operation

    AT32F421 Series Reference Manual Figure 5-2 Flash memory mass erase process Start Check the OBF bit in FLASH_STS OBF = 0? Set BANKERS = 1 and ERSTR =1 in FLASH_CTRL Check the OBF bit in FLASH_STS OBF = 0 ?

  • Page 65: Read Operation

    AT32F421 Series Reference Manual Figure 5-3 Flash memory programming process Start Check the OBF bit in FLASH_STS OBF = 0? Set the FPRGM bit = 1 in FLASH_CTRL Write word/half-word/byte (32bits/16 bits/8bits) data Check the OBF bit in FLASH_STS OBF = 0? Read EPPERR bit、PRGMERR...

  • Page 66: Erase Operation

    AT32F421 Series Reference Manual system data area can be programmed (write/erase). Note: Writing an incorrect key sequence leads to bus error and the Flash memory is also locked until the next reset. Lock procedure: User system data area is locked by clearing the USDULKS bit in the FLASH_CTRL register by software.

  • Page 67: Programming Operation

    AT32F421 Series Reference Manual 5.4.3 Programming operation The User system data area can be programmed with 16 bits or 32 bits at a time. The following process is recommended:  Check the OBF bit in the FLASH_STS register to confirm that there is no other programming operation in progress;...

  • Page 68: Read Operation

    AT32F421 Series Reference Manual 5.4.4 Read operation User system data area can be accessed through AHB bus of the CPU. 5.5 Flash memory protection Flash memory includes access and erase/program protection. 5.5.1 Access protection Flash memory access protection is divided into two parts: high-level and lowe level.

  • Page 69: Erase/Program Protection

    AT32F421 Series Reference Manual 5.5.2 Erase/program protection For 64 K Flash memory and less, erase/program protection is performed on the basis of 4 pages. This is used to protect the contents in the Flash memory against inadvertent operation when the program crash occurs.

  • Page 70: Bootloader Code Area Used As Flash Memory Extension

    AT32F421 Series Reference Manual  Wait until the OBF bit becomes “0” Set a security libaray password in the SLIB_SET_PWD register   Wait until the OBF bit becomes “0”  Program the code to be saved in security library ...

  • Page 71: Flash Memory Registers

    AT32F421 Series Reference Manual 5.7 Flash memory registers These peripheral registers must be accessed by words (32 bits). Table 5-6 Flash memory interface—Register map and reset value Register Offset Reset value FLASH_PSR 0x00 0x0000 0030 FLASH_UNLOCK 0x04 0xXXXX XXXX FLASH_USD_UNLOCK...

  • Page 72: Flash Unlock Register (Flash_Unlock)

    AT32F421 Series Reference Manual The wait states depends on the size of the system clock, and they are in terms of system clocks. 0: Zero wait state 1: One wait state 2: Two wait states 3: Three wait states The system clock sets the wait state on a 32-MHz basis:...

  • Page 73: Flash Control Register (Flash_Ctrl)

    AT32F421 Series Reference Manual 5.7.5 Flash control register (FLASH_CTRL) Register Reset value Type Description Bit 31: 8 Reserved 0x0000 resd Kept at its default value Low power mode enable 0: Low power mode disabled 1: Low power mode enabled Bit 17...

  • Page 74: Flash Address Register (Flash_Addr)

    AT32F421 Series Reference Manual 5.7.6 Flash address register (FLASH_ADDR) Register Reset value Type Description Flash address Bit 31: 0 0x0000 0000 Select the address of the pages to be erased. 5.7.7 User system data register (FLASH_USD) Register Reset value Type...

  • Page 75: Flash Security Library Status Register0 (Slib_Sts0)

    AT32F421 Series Reference Manual 5.7.9 Flash security library status register0 (SLIB_STS0) For Flash memory security library only. Register Reset value Type Description Bit 31: 24 Reserved 0x00 resd Kept at its default value Extension memory sLib instruction start sector 0: Invalid...

  • Page 76: Security Library Additional Status Register (Slib_Misc_Sts)

    AT32F421 Series Reference Manual 5.7.12 Security library additional status register (SLIB_MISC_STS) For Flash memory security library only. Register Reset value Type Description resd Kept at its default value Bit 31:3 Reserved 0x0000 000 Security library unlock flag When this bit is set, it indicates that sLib-related setting...

  • Page 77: Security Library Password Setting Register (Slib_Set_Pwd)

    AT32F421 Series Reference Manual 5.7.16 Security library password setting register (SLIB_SET_PWD) For Flash security library password setting only. Register Reset value Type Description sLib password setting value Note: This register can be written only after sLib is Bit 31: 0...

  • Page 78: Flash Extension Memory Security Library Setting Register (Em_Slib_Set)

    AT32F421 Series Reference Manual 5.7.18 Flash extension memory security library setting register (EM_SLIB_SET) For Flash extension area only. Register Reset value Type Description Kept at its default value Bit 31: 24 Reserved 0x00 resd Extension memory sLib instruction start page...

  • Page 79: General-Purpose I/Os (Gpios)

    6 General-purpose I/Os (GPIOs) 6.1 Introduction AT32F421 series supports up to 39 bidirectional I/O pins, namely PA0-PA15, PB0-PB15, PC13-PC15, PF0-PF1 and PF6-PF7. Each of the GPIO group supports external communication, with control and data collection feature. In addition, their main features also include: ...

  • Page 80: General-Purpose Input Configuration

    AT32F421 Series Reference Manual 6.2.3 General-purpose input configuration Mode IOMC PUPD Floating input Pull-down input Pull-up input When I/O port is configured as input:  Get I/O states by reading the input data register.  Support floating input, pull-up/pull-down input configuration.

  • Page 81: Iomux Structure

    AT32F421 Series Reference Manual 6.2.7 IOMUX structure Most of the pins supports output function mapping for multiple peripherals. It is possible to select the peripheral input/output functions for each pin by using the IOMUX input/output checklist described in the section of IOMUX input/output. The multiplexed function of pins is configured using the corresponding GPIO multiplexed register low (GPIOx_MUXL) (for pin 0 ~ pin 7) or the GPIO multiplexed register high (GPIOx_MUXH) (for pin 8 ~ pin 15).

  • Page 82: Iomux Function Input/Output

    AT32F421 Series Reference Manual 6.2.9 IOMUX function input/output The selection of the valid multiplexed functions for each port is done by the GPIOx_MUXL (for pin 0 to pin 7) or GPIOx_MUXH (for pin 8 to pin 15) registers. Table 6-1 Multiplexed function configuration for port A using GPIO_A MUX...

  • Page 83: Table 6-2 Multiplexed Function Configuration For Port B Using Gpio_B Mux* Register

    AT32F421 Series Reference Manual Table 6-2 Multiplexed function configuration for port B using GPIO_B MUX register MUX0 MUX1 MUX2 MUX3 MUX4 MUX5 MUX6 MUX7 name TMR3_C TMR1_CH USART2 EVENTOUT I2S1_MCLK TMR3_C TMR1_CH SPI2_SCK/I TMR14_CH1 2S2_CK TMR3_ET SPI1_SCK/I2 EVENTO SPI2_SCK/I S1_CK...

  • Page 84: Peripheral Multiplexed Function Configuration

    AT32F421 Series Reference Manual 6.2.10 Peripheral multiplexed function configuration When IOMUX multiplexed function is needed:  To use a peripheral pin in multiplexed output, the corresponding pin should be configured as multiplexed push-pull/open-drain output. To use a peripheral pin in MUX input, the corresponding pin configured as floating input/pull-up/pull- ...

  • Page 85: Gpio Configuration Register (Gpiox_Cfgr) (X=A

    AT32F421 Series Reference Manual GPIOx_PULL(x = B,C,F) 0x0C 0x0000 0000 GPIOx_IDT 0x10 0x0000 XXXX GPIOx_ODT 0x14 0x0000 0000 GPIOx_SCR 0x18 0x0000 0000 GPIOx_WPR 0x1C 0x0000 0000 GPIOx_MUXL 0x20 0x0000 0000 GPIOx_MUXH 0x24 0x0000 0000 GPIOx_CLR 0x28 0x0000 0000 GPIOx_HDRV 0x3C 0x0000 0000 6.3.1...

  • Page 86: Gpio Input Data Register (Gpiox_Idt) (X=A

    AT32F421 Series Reference Manual 6.3.5 GPIO input data register (GPIOx_IDT) (x=A…H) Register Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Always 0. GPIOx input data Bit 15: 0 0xXXXX Indicates the input status of I/O port. Each bit corresponds to an I/O.

  • Page 87: Gpio Multiplexed Function Low Register (Gpiox_Muxl) (X=A

    AT32F421 Series Reference Manual 6.3.9 GPIO multiplexed function low register (GPIOx_MUXL) (x=A..H) Address offset: 0x20 Reset value: 0x00000000 Register Reset value Type Description Multiplexed function select for GPIOx pin y (y=0…7) This field is used to configure multiplexed function IOs.

  • Page 88: System Configuration Controller (Scfg)

    AT32F421 Series Reference Manual 7 System configuration controller (SCFG) 7.1 Introduction This device contains a set of system configuration register. The system configuration controller is mainly used to:  Remap some DMA trigger sources to other DMA channels Manage the external interrupts connected to the GPIOs ...

  • Page 89: Scfg External Interrupt Configuration Register1 (Scfg_ Exintc1)

    AT32F421 Series Reference Manual channel 2. Infrared modulation envelope signal source selection This field is used to select the infrared modulation envelope signal source. Bit 7: 6 IR_SRC_SEL 00: TMR16 01: USART1 10: USART2 11: Reserved Infrared output polarity selection...

  • Page 90: Scfg External Interrupt Configuration Register2 (Scfg_ Exintc2)

    AT32F421 Series Reference Manual 7.2.3 SCFG external interrupt configuration register2 (SCFG_ EXINTC2) Register Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Kept at its default value. EXINT7 input source configuration These bits can be read/written by software. They are used to select the input source for the EXINT7 external interrupt.

  • Page 91: Scfg External Interrupt Configuration Register4 (Scfg_ Exintc4)

    AT32F421 Series Reference Manual These bits can be read/written by software. They are used to select the input source for the EXINT8 external interrupt. 0000: PA[8] 0001: PB[8] 7.2.5 SCFG external interrupt configuration register4 (SCFG_ EXINTC4) Register Reset value Type...

  • Page 92: External Interrupt/Event Controller (Exint)

    AT32F421 Series Reference Manual 8 External interrupt/Event controller (EXINT) 8.1 EXINT introduction EXINT consists of 22 interrupt lines EXINT_LINE[21:0] (Line 18 and Line 20 are reserved), each of which can generate an interrupt or event by edge detection trigger or software trigger. EXINT can...

  • Page 93: Exint Registers

    AT32F421 Series Reference Manual Interrupt initialization procedure Select an interrupt source by setting IOMUX_EXINTCx register (This is required if GPIO is used  as an interrupt source) Select a trigger mode by setting EXINT_POLCFG1 and EXINT_POLCFG2 registers   Enable interrupt or event by setting EXINT_INTEN and EXINT_EVTEN registers Generate software trigger by setting EXINT_SWTRG register (This is applied to only software ...

  • Page 94: Polarity Configuration Register2 (Exint_ Polcfg2)

    AT32F421 Series Reference Manual 8.3.4 Polarity configuration register2 (EXINT_ POLCFG2) Register Reset value Type Description Bit 31: 22 Reserved 0x000 resd Forced to be 0 by hardware. Falling polarity configuration bit on line x These bits are used to select a falling edge to trigger an interrupt and event on line x.

  • Page 95: Dma Controller (Dma)

    AT32F421 Series Reference Manual 9 DMA controller (DMA) 9.1 Introduction Direct memory access (DMA) controller is designed for 32-bit MCU applications with the aim of enhancing system performance and reducing the generation of interrupts. The DMA controller contains 5 DMA channels. Each channel manages memory access requests from one or more peripherals.

  • Page 96: Handshake Mechanism

    AT32F421 Series Reference Manual If the two channels have the same priority level, then the channel with lower number will get priority over the one with higher number. For example, channel 1 has priority over channel 2.  Data transfer direction (DTD) Memory-to-peripheral (M2P), peripheral-to-memory (P2M) ...

  • Page 97: Programmable Data Transfer Width

    AT32F421 Series Reference Manual 9.3.4 Programmable data transfer width Transfer width of the source data and destination data is programmable through the PWIDTH and MWIDTH bits in the DMA_CxCTRL register. When PWIDTH is not equal to MWIDTH, number of data to be transferred can be aligned according to the settings of PWIDTH/MWIDTH.

  • Page 98: Errors

    AT32F421 Series Reference Manual 9.3.5 Errors Table 9-1 DMA error event Error event Transfer error AHB response error occurred during DMA read/write access 9.3.6 Interrupts An interrupt can be generated on DMA half-transfer, transfer complete and transfer error. Each channel has its specific interrupt flag, clear and enable bits, as shown in the table below.

  • Page 99: Dma Registers

    AT32F421 Series Reference Manual 9.4 DMA registers Table 9-4 shows DMA register map and their reset values. These peripheral registers must be accessed by bytes (8 bits), half-words (16 bits) or words (32 bits). Table 9-4 DMA register map and reset value...

  • Page 100: Dma Interrupt Status Register (Dma_Sts)

    AT32F421 Series Reference Manual 9.4.1 DMA interrupt status register (DMA_STS) Access: 0 wait state, accessible by bytes, half-words or words. Register Reset value Type Description Bit 31: 20 Reserved resd Kept at its default value. Channel 5 data transfer error event flag...

  • Page 101: Dma Interrupt Flag Clear Register (Dma_Clr)

    AT32F421 Series Reference Manual Channel 1 data transfer error event flag Bit 3 DTERRF1 0: No transfer error occurred. 1: Transfer error occurred. Channel 1 half transfer event flag Bit 2 HDTF1 0: No half-transfer event occurred. 1: Half-transfer event occurred.

  • Page 102: Dma Channel-X Configuration Register (Dma_Cxctrl) (X = 1

    AT32F421 Series Reference Manual Channel 3 global interrupt flag clear 0: No effect Bit 8 GFC3 rw1c 1: Clear the DTERRF3, HDTF3, FDTF3 and GF3 flag in the DMA_STS register Channel 2 data transfer error flag clear Bit 7 DTERRFC2...

  • Page 103: Dma Channel-X Number Of Data Register (Dma_Cxdtcnt)

    AT32F421 Series Reference Manual 1: Enabled. Circular mode Bit 5 0: Disabled 1: Enabled. Data transfer direction Bit 4 0: Read from peripherals 1: Read from memory Data transfer error interrupt enable Bit 3 DTERRIEN 0: Disabled 1: Enabled. Half-transfer interrupt enable...

  • Page 104: Crc Calculation Unit (Crc)

    AT32F421 Series Reference Manual 10 CRC calculation unit (CRC) 10.1 CRC introduction The Cyclic Redundancy Check (CRC) is an independent peripheral with CRC check feature. It follows CRC32 standard. The CRC_CTRL register is used to select input data toggle (word, REVOD=1) or output data toggle (byte, REVID=01;...

  • Page 105: Control Register (Crc_Ctrl)

    AT32F421 Series Reference Manual 10.2.3 Control register (CRC_CTRL) Register Reset value Type Description Bit 31: 8 Reserved 0x000000 resd Kept at its default value. Reverse output data Set and cleared by software. This bit is used to control Bit 7...

  • Page 106: C Interface

    AT32F421 Series Reference Manual 11 I C interface 11.1 I C introduction C (inter-integrated circuit) bus interface manages the communication between the microcontroller and serial I C bus. It supports master and slave modes, with up to 400 kbit/s of communication speed.

  • Page 107: I 2 C Interface

    AT32F421 Series Reference Manual 11.4 I C interface Figure 11-2 shows the block diagram of I C function Figure 11-2 I C function block diagram Comparator Data Control Shift Register APB Interface Control register Data Clock OADDR Register Control Status...

  • Page 108: C Slave Communication Flow

    AT32F421 Series Reference Manual  In 10-bit mode ― Only matches OADDR1 Support special slave address:  Broadcast call address (0b0000000x): This address is enabled when GCAEN=1.  SMBus device default address (0b1100001x): This address is enabled for SMBus address resolution protocol in SMBus device mode.

  • Page 109: Figure 11-3 Transfer Sequence Of Slave Transmitter

    AT32F421 Series Reference Manual Figure 11-3 Transfer sequence of slave transmitter Example : I2C Slave transfer N bytes to I2C Master . EV2 EV3 7-bit address Address Data1 Data2 DataN NA P Stretch TDBE 10-bit address Address Head Address Address Head...

  • Page 110: Figure 11-4 Transfer Sequence Of Slave Receiver

    AT32F421 Series Reference Manual Slave receiver Figure 11-4 shows the transfer sequence of slave receiver. Figure 11-4 Transfer sequence of slave receiver Example : I2C Slave receive N bytes from I2C Master . 7-bit address Address Data1 Data2 DataN Stretch...

  • Page 111: C Master Communication Flow

    AT32F421 Series Reference Manual 11.4.2 I C master communication flow Master mode Initialization Porgram input clocks to generate correct timings through the CLKFREQ bit in the I2C_CTRL2 register; Program I C communication speed through the I2C_CLKCTRL bit in the clock control register;...
  • Page 112 AT32F421 Series Reference Manual register. EV2: Address is matched successfully (ADDR7F=1). Reading STS1 and then STS2 clears the ADDR7F bit. At this point, the master enters transmit stage, and both DT register and internal shift regiser are empty. The TDBE bit is set 1 by hardware.

  • Page 113: Figure 11-6 Transfer Sequence Of Master Receiver

    AT32F421 Series Reference Manual Figure 11-6 Transfer sequence of master receiver Example : I2C Master receive N bytes from I2C Slave . 7-bit address Address Data1 Data2 DataN NA P Stretch Stretch RDBF 10-bit address Address Address Head Address Head...

  • Page 114: Figure 11-7 Transfer Sequence Of Master Receiver When N>2

    AT32F421 Series Reference Manual the GENSTOP bit in the I2C_CTRL1 register and read the second-to-last byte (N-1). The bus then starts to receive the last one byte. Figure 11-7 Transfer sequence of master receiver when N>2 Example : I2C Master receive N bytes from I2C Slave .

  • Page 115: Figure 11-8 Transfer Sequence Of Master Receiver When N=2

    AT32F421 Series Reference Manual 10. End of communication. When I C interrupt priority is not very high but the number of bytes to receive is equal to 2  Set the MACKCTRL bit in the I2C_CTRL1 register before data reception. When the address is matched, clear ACKEN bit and then the ADDR7F bit.

  • Page 116: Figure 11-9 Transfer Sequence Of Master Receiver When N=1

    AT32F421 Series Reference Manual End of communication. When I C interrupt priority is not very high but the number of bytes to receive is equal to 1  After the address is matched, clear the ACKEN bit and then ADDR7F bit, then set the GENSTOP bit in the I2C_CTRL1 register.

  • Page 117: Data Transfer Using Dma

    AT32F421 Series Reference Manual 11.4.3 Data transfer using DMA C data transfer can be done using DMA controller. An interrupt is generated by enabling the transfer complete interrupt bit. The DATAIEN bit in the I2C_CTRL2 register must be set 0 when using DMA for data transfer.

  • Page 118: Smbus

    AT32F421 Series Reference Manual 11.4.4 SMBus The System Management Bus (SMBus) is a two-wire interface through which various devices can communicate with each other. It is based on I C. With SMBus, the device can provide manufacturer information, tell the system its model/part number, report different types of errors and accept control parameters and so on.

  • Page 119: C Interrupt Requests

    AT32F421 Series Reference Manual When an alert event occurs and the ALERT pin changes from high to low (SMBALERT=1), the slave responses to ARA (Alert Response Address) address (0001100x) Enable ALERT interrupt if necessary (an interrupt is generated when receiving ARA address) Wait until the host gets the slave addresses through ARA Report its own address, but it continues to wait if the arbitration is lost.

  • Page 120: C Debug Mode

    AT32F421 Series Reference Manual 11.4.6 I C debug mode When the microcontroller enters debug mode (Cortex -M4 halted), the SMBUS timeout feature either continues to work or stops, depending on the I2Cx_SMBUS_TIMEOUT configuration bit in the DEBUG module. 11.5 I C registers These peripheral registers must be accessed by words (32 bits).

  • Page 121: Control Register2 (I2C_Ctrl2)

    AT32F421 Series Reference Manual Generate stop condition This bit is set or cleared by software. It is cleared when a Stop condition is detected. It is set by hardware when a timeout error is detected. Bit 9 GENSTOP 0: No Stop condition is generated.

  • Page 122: Own Address Register1 (I2C_Oaddr1)

    AT32F421 Series Reference Manual 1: Enabled Data transfer interrupt enable An interrupt is generated when TDBE =1 or RDBF=1. Bit 10 DATAIEN 0: Disabled 1: Enabled Event interrupt enable 0: Disabled 1: Enabled An interrupt is generated in the following conditions: –...

  • Page 123: Data Register (I2C_Dt)

    AT32F421 Series Reference Manual recognized. 11.5.5 Data register (I2C_DT) Register Reset value Type Description Kept at its default value Bit 15: 8 Reserved 0x00 resd This field is used to store data received or to be transferred. Transmitter mode: Data transfer starts automatically when a byte is written to the DT register.
  • Page 124 AT32F421 Series Reference Manual 1: Acknowledge failure occurs. Set by hardware when no acknowledge is returned. This bit is cleared by software, or by hardware when I2CEN=0. Arbitration lost flag 0: No arbitration lost is detected. 1: Arbitration lost is detected.

  • Page 125: Status Register2 (I2C_Sts2)

    AT32F421 Series Reference Manual received. When STRETCH=0 In reception mode, when a new byte (including ACK pulse) is received and the data register is not read yet (RDBF=1) In transmission mode, when a new byte is sent and the data register is not written yet (TDBE=1) The TDC is set under both conditions.

  • Page 126: Clock Control Register (I2C_ Clkctrl)

    AT32F421 Series Reference Manual Transmission mode 0: Slave mode 1: Master mode Bit 0 TRMODE Set by hardware when the GENSTART is set and a Start condition is sent. Cleared by hardware when a Stop condition is detected. 11.5.8 Clock control register (I2C_ CLKCTRL)

  • Page 127: Universal Synchronous/Asynchronous Receiver/Transmitter (Usart)

    AT32F421 Series Reference Manual 12 Universal synchronous/asynchronous receiver/transmitter (USART) 12.1 USART introduction The universal synchronous/asynchronous receiver/transmitter (USART) acts as a general-purpose interface for communication by means of various configurations and peripherals with different data formats. It supports asynchronous full-duplex and half-duplex as well as synchronous transfer. It offers a programmable baud rate generator, generating up to 7.5 MBits/s of baud rate by setting the system...
  • Page 128 AT32F421 Series Reference Manual ─ Half-duplex, single communication  Programmable communication modes ─ NRZ standard format (Mark/Space) ─ LIN (Local Interconnection Network): LIN master with break generation capability and LIN slave with break detection capability ─ IrDA SIR: Support 3/16 bit duration in normal mode, and configurable duration in infrared low- power mode ─Asynchronous SmartCard protocol defined in ISO7816-3 standard: Support 0.5 or 1.5 stop bits in...

  • Page 129: Full-Duplex/Half-Duplex Selector

    AT32F421 Series Reference Manual 12.2 Full-duplex/half-duplex selector The full-duplex and half-duplex selector enables USART to perform data exchanges with peripherals in full-duplex or half-duplex mode, which is achieved by setting the corresponding registers. In two-wire unindirectional full-duplex mode (by default), TX pin is used for data output, while the RX pin is used for data input.

  • Page 130: Usart Frame Format And Configuration

    AT32F421 Series Reference Manual 12.4 USART frame format and configuration USART data frame consists of start bit, data bit and stop bit, with the last data bit being as a parity bit. USART idle frame size is equal to that of the data frame under current configuration, but all bits are 1.

  • Page 131: Baud Rate Generation

    AT32F421 Series Reference Manual 12.6 Baud rate generation 12.6.1 Introduction USART baud rate generator uses an internal counter based on PCLK. The DIV (USART_BAUDR [15:0] register) represents the overflow value of the counter. Each time the counter is full, it denotes one-bit data.

  • Page 132: Transmitter

    AT32F421 Series Reference Manual 12.7 Transmitter 12.7.1 Transmitter introduction USART transmitter has its individual TEN control bit. The transmitter and receiver share the same baud rate that is programmable. There is a transmit data buffer (TDR) and a transmit shift register in the USART.

  • Page 133: Receiver Configuration

    AT32F421 Series Reference Manual 12.8.2 Receiver configuration Configuration procedure: 1. USART enalbe: UEN bit is set. 2. Full-duplex/half-duplex configuration: Refer to full-duplex/half-duplex selector for more information. 3. Mode configuration: Refer to mode selector for more information. 4. Frame format configuration: Refer to frame format for more information.

  • Page 134: Start Bit And Noise Detection

    AT32F421 Series Reference Manual Note: The REN bit cannot be reset during data reception, or the byte that is currently being received will be lost. 12.8.3 Start bit and noise detection A start bit detection occurs when the REN bit is set. With the oversampling techniques, the USART receiver samples data on the 3rd, 5th, 7th, 8th, 9th and 10th bits to detect the valid start bit and noise.

  • Page 135: Interrupt Requests

    AT32F421 Series Reference Manual Figure 12-2 Tx/Rx swap USART_TX USART_TX USART_RX USART_RX USART USART TRPSWAP=0 TRPSWAP=1 Note: The SWAP (USART_CTRL2[15]) can be modified only when the USART is disabled (UEN=0) 12.10 Interrupt requests USART interrupt generator serves as a control center of USART interrupts. It is used to monitor the interrupt source inside the USART in real time, and to define the generation of interrupts by configuring the corresponding interrupt enable bits.

  • Page 136: I/O Pin Control

    AT32F421 Series Reference Manual 12.11 I/O pin control The following five interfaces are used for USART communication. RX: Serial data input. TX: Serial data output. In single-wire half-duplex and Smartcard mode, the TX pin is used as an I/O for data transmission and reception.

  • Page 137: Status Register (Usart_Sts)

    AT32F421 Series Reference Manual 12.12.1 Status register (USART_STS) Register Reset value Type Description Bit 31: 10 Reserved 0x000000 resd Forced 0 by hardware. CTS change flag This bit is set by hardware when the CTS status line Bit 9 CTSCF rw0c changes.

  • Page 138: Data Register (Usart_Dt)

    AT32F421 Series Reference Manual This bit is set by hardware when parity error occurs. It is cleared by software. USART_STS register followed by a USART_DT read operation) 0: No parity error occurs. 1: Parity error occurs. 12.12.2 Data register (USART_DT)

  • Page 139: Control Register2 (Usart_Ctrl2)

    AT32F421 Series Reference Manual TDC interrupt enable 0: Interrupt is disabled. Bit 6 TDCIEN 1: Interrupt is enabled. RDBF interrupt enable 0: Interrupt is disabled. Bit 5 RDBFIEN 1: Interrupt is enabled. IDLE interrupt enable 0: Interrupt is disabled. Bit 4 IDLEIEN 1: Interrupt is enabled.

  • Page 140: Control Register3 (Usart_Ctrl3)

    AT32F421 Series Reference Manual Clock polarity In synchronous mode or Smartcard mode, this bit is used to select the polarity of the clock output on the clock pin in Bit 10 CLKPOL idle state. 0: Clock output low 1: Clock output high...

  • Page 141: Guard Time And Divider Register (Usart_Gdiv)

    AT32F421 Series Reference Manual Smartcard NACK enable This bit is used to send NACK when parity error occurs. Bit 4 SCNACKEN 0: NACK is disabled when parity error occurs. 1: NACK is enabled when parity error occurs. Single-wire bidirectional half-duplex enable 0: Single-wire bidirectional half-duplex is disabled.

  • Page 142: Serial Peripheral Interface (Spi)

    AT32F421 Series Reference Manual 13 Serial peripheral interface (SPI) 13.1 SPI introduction The SPI interace supports either the SPI protocol or the I S protocoal, depending on software configuration. This chapter gives an introduction of the main features and congiruation procedure of SPI used as SPI and I S respectively.

  • Page 143: Full-Duplex/Half-Duplex Selector

    AT32F421 Series Reference Manual  Programmable data transfer sequence (MSB-first or LSB-first) Programmable error interrupt flags (receiver overflow error, master mode error and CRC error)   Programmable transmit data buffer empty interrupt and receive data buffer full interrupt ...

  • Page 144: Figure 13-4 Single-Wire Unidirectional Receive Only In Spi Slave Mode

    AT32F421 Series Reference Manual Figure 13-4 Single-wire unidirectional receive only in SPI slave mode SPI master SPI slave MISO MISO MOSI MOSI In SPI master mode, it is necessary to wait until the second-to-last RDBF bit is set and then wait another SPI_CPK cycle before disabling SPI.

  • Page 145: Chip Select Controller

    AT32F421 Series Reference Manual 13.2.3 Chip select controller The Chip select controller (CS) is used to enable hardware or software control for chip select signals through software configuration. This controller is used to select master/slave device in multi-processor mode, and to avoid conflicts on the data lines by first enabling the SCK signal and then CS signal. The hardware and software configuration procedure is detailed as follows, along with their respective input/output in master and slave mode.

  • Page 146: Dma Transfer

    AT32F421 Series Reference Manual  CRC calculation polynominal is configured by setting the SPI_CPOLY register. CRC enable: The CRC calculation is enabled by setting the CCEN bit. This operation will reset  the SPI_RCRC and SPI_TCRC registers. Select if or when the NTC bit is set, depending on DMA or CPU data register. See the following ...

  • Page 147: Transmitter

    AT32F421 Series Reference Manual  Configure the destination of DMA transfer: Configure the memory address as the destination of DMA transfer in the DMA control register. Data will be loaded from the SPI_DT register to the programmed destination after reception request is received by DMA.

  • Page 148: Motorola Mode

    AT32F421 Series Reference Manual generated if the RDBFIE bit is set. When the next received data is ready to be moved to the SPI_DT register, if the previous received data is still not read (RDBF=1), then the data overflow occurs. The previous receive data is not lost, but the next received data will do.

  • Page 149: Figure 13-7 Slave Full-Duplex Communications

    AT32F421 Series Reference Manual Figure 13-7 Slave full-duplex communications Sampling Drive MISO MOSI TDBE flag Transmit buffer empty and RDBF flag software can write data BF flag Software needs to read the received data Half-duplex communication – master transmit Configured as follows:...

  • Page 150: Interrupts

    AT32F421 Series Reference Manual CLKPOL=0, CLKPHA=0: SCK idle output low, use the first edge for sampling FBN=0: 8-bit frame Slave transmit: 0xaa, 0xcc, 0xaa Figure 13-10 Slave half-duplex transmit Drive MISO Transmit buffer empty and TDBE flag software can write data BF flag Half-duplex communication –...

  • Page 151: Io Pin Control

    AT32F421 Series Reference Manual 13.2.11 IO pin control When used as SPI, the SPI interface is connected to peripherals through up to four pins. Refer to Section 13.2.2 and Section 13.2.3 for more information on the usage of pins.  MISO: Master In/Slave Out. The pin receives data in SPI master mode, and transmits data in SPI slave mode.

  • Page 152: Operation Mode Selector

    AT32F421 Series Reference Manual ─ Slave device reception ─ Master device transmission ─ Master device reception  Programmable clock polarity Programmable clock frequency (8 KHz to 192 KHz)   Prorammable data bits (16 bit, 24 bit, 32 bit) Programmable channel bits (16 bit, 32 bit) ...

  • Page 153: Audio Protocol Selector

    AT32F421 Series Reference Manual Master device transmission: Set the I2SMSEL bit, and OPERSEL[1:0]=10, the I S will work in master device transmission mode. Figure 13-16 I S master device transmission Master device reception: Set the I2SMSEL bit, and OPERSEL[1: 0]=11, the I S will work in master device repection mode.

  • Page 154: I2S_Clk Controller

    AT32F421 Series Reference Manual  Select channel bits by setting the I2SCBN bit I2SDBN =0: 16 bit I2SDBN =1: 32 bit Note: Read/Write operation mode depends on the selected audio protocols, data bits and channel bits. The following lists all possible configuration combinations and their respective read and write operation mode.

  • Page 155: Figure 13-18 Ck & Mck Source In Master Mode

    AT32F421 Series Reference Manual Figure 13-18 CK & MCK source in master mode Divided by (2xI2SDIV[9:0]+I I2SMCLKOE 2SODD) ~CHLEN Divided by SCLK Divided by 8 (2xI2SDIV[9:0]+I 2SODD) CHLEN Divided by I2SMCLKOE Divided by 4 (2xI2SDIV[9:0]+I 2SODD) Apart from the above-mentioned configuration, the following table lists the values of I2SDIV and I2SODD corresponding to some specific frequencies, as well as their respective error for the users to configure the I2SDIV and I2SODD.

  • Page 156: Dma Transfer

    AT32F421 Series Reference Manual 22050 22203.95 0.698% 22203.95 0.698% 16000 16225.96 1.41% 16225.96 1.41% 11025 11101.97 0.698% 11101.97 0.698% 8000 7959.906 0.501% 7959.906 0.501% 192000 187500 2.34% 187500 2.34% 96000 97826.09 1.90% 93750 2.34% 48000 34615.38 27.88% 48913.04 1.90% 44100 44117.65...

  • Page 157: Transmitter/Receiver

    AT32F421 Series Reference Manual  Configure DMA interrupt generation after half or full transfer in the DMA control registe Enable DMA transfer channel in the DMA control register.  13.3.6 Transmitter/Receiver Whether being used as SPI or I S, there is no difference for CPU. The SPI (in whatever mode) shares the same base address, the same SPI_DT register, the same transmitter and receiver.

  • Page 158: I2S Communication Timings

    AT32F421 Series Reference Manual 13.3.7 I2S communication timings I2S supports four different audio standards: Philips standard, the most significant byte (left-aligned) and the least significant byte (right-aligned) standards, and the PCM standard. Figure 13-19 shows their respective timgins. Figure 13-19 Audio standard timings...

  • Page 159: Spi Registers

    AT32F421 Series Reference Manual 13.4 SPI registers These peripheral registers must be accessed by half-word (16 bits) or word (32 bits). Table 13-2 SPI register map and reset value Register Offset Reset value SPI_CTRL1 0x00 0x0000 SPI_CTRL2 0x04 0x0000 SPI_STS...

  • Page 160: Spi Control Register2 (Spi_Ctrl2)

    AT32F421 Series Reference Manual This bit is used to select for MST transfer first or LSB transfer first. 0: MSB 1: LSB SPI enable Bit 6 SPIEN 0: Disabled 1: Enabled Master clock frequency division In master mode, the peripheral clock divided by the prescaler is used as SPI clock.

  • Page 161: Spi Status Register (Spi_Sts)

    AT32F421 Series Reference Manual 13.4.3 SPI status register (SPI_STS) Register Reset value Type Description Forced to be 0 by hardware Bit 15: 8 Reserved 0x00 resd Busy flag 0: SPI is not busy. Bit 7 1: SPI is busy. Receiver overflow error...

  • Page 162: Spirxcrc Register (Spi_Rcrc)

    AT32F421 Series Reference Manual 13.4.6 SPIRxCRC register (SPI_RCRC) (Not used in I S mode) Register Reset value Type Description Receive CRC When CRC calculation is enabled, this register contains the CRC value computed based on the received data. This register is reset when the CCEN bit in the SPI_CTRL1 register is cleared.

  • Page 163: Spi_I2S Prescaler Register (Spi_I2Sclkp)

    AT32F421 Series Reference Manual 00: 16-bit data length 01: 24-bit data length 10: 32-bit data length 11: Not allowed. S channel bit num This bit can be configured only when the I S is set to 16- bit data; otherwise, it is fixed to 32-bit by hardware.

  • Page 164: Timer

    AT32F421 Series Reference Manual 14 Timer AT32F421 timers include basic timers, general-purpose timers, and advanced timers. Please refer to Section 14.1~ Section 14.6 for the detailed function modes. All functions of different timers are shown in the following tables. Table 14-1 TMR functional comparison...

  • Page 165: General-Purpose Timer (Tmr6)

    AT32F421 Series Reference Manual 14.1 General-purpose timer (TMR6) 14.1.1 TMR6 introduction The basic timer (TMR6) consists of a 16-bit upcounter and the corresponding control logic. without being connected to external I/Os. 14.1.2 TMR6 main features  Souce of counter clock: internal clock ...

  • Page 166: Debug Mode

    AT32F421 Series Reference Manual Figure 14-3 Overflow event when PRBEN=0 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Figure 14-4 Overflow event when PRBEN=1 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Figure 14-5 Counting timing diagram when the prescaler division is 4...

  • Page 167: Tmr6 Control Register1 (Tmrx_Ctrl1)

    AT32F421 Series Reference Manual 14.1.4.1 TMR6 control register1 (TMRx_CTRL1) Register Reset value Type Description Bit 15: 8 Reserved 0x00 resd Kept at its default value. Period buffer enable Bit 7 PRBEN 0: Period buffer is disabled. 1: Period buffer is enabled.

  • Page 168: Tmr6 Interrupt Status Register (Tmrx_Ists)

    AT32F421 Series Reference Manual 14.1.4.4 TMR6 interrupt status register (TMRx_ISTS) Register Reset value Type Description Bit 15: 1 Reserved 0x0000 resd Kept at its default value. Overflow interrupt flag This bit is set by hardware at an update event. It is cleared by software.

  • Page 169: General-Purpose Timer (Tmr3)

    AT32F421 Series Reference Manual 14.2 General-purpose timer (TMR3) 14.2.1 TMR3 introduction The general-purpose timer TMR3 consists of a 16-bit counter supporting up, down, up/down (bidirectional) counting modes, four capture/compare registers, and four independent channels to achieve input capture and programmable PWM output.

  • Page 170: Figure 14-8 Block Diagram Of External Clock Mode A

    AT32F421 Series Reference Manual External clock (TRGIN/EXT) The counter clock can be provided by two external clock sources, namely, TRGIN and EXT signals. When SMSEL=3’111, external clock mode A is selected. Set the STIS[2: 0] bit to select TRGIN signal to drive the counter to start counting.

  • Page 171: Counting Mode

    AT32F421 Series Reference Manual Figure 14-11 Counter timing diagram in external clock mode B TMR_CLK CNT_CLK COUNTER ESDIV[1:0] ESF[3:0] 0000 OVFIF Clear Internal trigger input (ISx) Timer synchronization allows interconnection between several timers. The TMR_CLK of one timer can be provided by the TRGOUT signal output by another timer. Set the STIS[2: 0] bit to select internal trigger signal to enable counting.

  • Page 172: Figure 14-13 Overflow Event When Prben=0

    AT32F421 Series Reference Manual Figure 14-13 Overflow event when PRBEN=0 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Figure 14-14 Overflow event when PRBEN=1 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Downcounting mode In downcounting mode, the counter counts from the value programmed in the TMR3_PR register down to 0, and restarts from the value programmed, and generates a counter underflow event.

  • Page 173: Tmr Input Function

    AT32F421 Series Reference Manual on the edge of the other input. The OWCDIR bit indicates the direction of the counter, as shown in the table below: Table 14-4 Couting direction versus encoder signals C1INFP1 signal C2INFP2 signal Level on opposite signal...

  • Page 174: Tmr Output Function

    AT32F421 Series Reference Manual Input mode In input mode, the TMR3_CxDT register latch the current counter values after the selected triggle signal is detected, and the capture compare interrupt flag bit (CxIF) is set. An interrupt or a DMA request will be generated if the CxIEN and CxDEN bits are enabled.

  • Page 175: Figure 14-21 C1Oraw Toggles When Counter Value Matches The C1Dt Value

    AT32F421 Series Reference Manual  Forced output mode: Set CxOCTRL=3’b100/101 to enable forced output mode. In this case, the CxORAW is forced to be the programmed level, irrespective of the counter value. Despite this, the channel flag bit and DMA request still depend on the compare result.

  • Page 176: Figure 14-23 Up/Down Counting Mode And Pwm Mode A

    AT32F421 Series Reference Manual Figure 14-23 Up/down counting mode and PWM mode A TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL[2：0] C1DT[15：0] C1ORAW CIDT[15：0] C1ORAW ≥32 C1DT[15：0] C1ORAW Figure 14-24 One-pulse mode COUNTER PR[15：0] C1DT[15：0] TRGIN C1ORAW C1OUT CxORAW clear When the CxOSEN bit is set, the CxORAW signal for a given channel is cleared by applying a high level to the EXT input.

  • Page 177: Tmr Synchronization

    AT32F421 Series Reference Manual 14.2.3.5 TMR synchronization The timers are linked together internnaly for timer synchronization. Master timer is selected by setting the PTOS[2: 0] bit; Slave timer is selected by setting the SMSEL[2: 0] bit. Slave mode includes: Slave mode: Reset mode The counter and its prescaler can be reset by a selected trigger signal.

  • Page 178: Figure 14-29 Master/Slave Timer Connection

    AT32F421 Series Reference Manual Master/slave timer interconnection Both Master and slave timer can be configured in different master and slave modes respectively. The combination of both them can be used for various purposes. Figure 14-29 provides an example of interconnection between master timer and slave timer.

  • Page 179: Debug Mode

    AT32F421 Series Reference Manual Starting master and slave timers synchronously by an external trigger: In this example, configure the master timer as master/slave mode synchronously and enable its slave timer synchronization function. This mode is used for synchronization between master timer and slave timer.

  • Page 180: Control Register1 (Tmr3_Ctrl1)

    AT32F421 Series Reference Manual TMR3_PR 0x2C 0x0000 0000 TMR3_C1DT 0x34 0x0000 0000 TMR3_C2DT 0x38 0x0000 0000 TMR3_C3DT 0x3C 0x0000 0000 TMR3_C4DT 0x40 0x0000 0000 TMR3_DMACTRL 0x48 0x0000 TMR3_DMADT 0x4C 0x0000 14.2.4.1 Control register1 (TMR3_CTRL1) Register Reset value Type Description Bit 15: 10...

  • Page 181: Control Register2 (Tmr3_Ctrl2)

    AT32F421 Series Reference Manual 14.2.4.2 Control register2 (TMR3_CTRL2) Register Reset value Type Description Bit 15: 8 Reserved 0x00 resd Kept at its default value. C1IN selection 0: CH1 pin is connected to C1IRAW input Bit 7 C1INSEL 1: The XOR result of CH1, CH2 and CH3 pins is connected...

  • Page 182: Dma/Interrupt Enable Register (Tmr3_Iden)

    AT32F421 Series Reference Manual 1: Enabled Subordinate TMR input selection This field is used to select the subordinate TMR input. 000: Internal selection 0 (IS0) 001: Internal selection 1 (IS1) 010: Internal selection 2 (IS2) 011: Internal selection 3 (IS3)

  • Page 183: Interrupt Status Register (Tmr3_Ists)

    AT32F421 Series Reference Manual Channel 2 interrupt enable Bit 2 C2IEN 0: Disabled 1: Enabled Channel 1 interrupt enable Bit 1 C1IEN 0: Disabled 1: Enabled Overflow interrupt enable Bit 0 OVFIEN 0: Disabled 1: Enabled 14.2.4.5 Interrupt status register (TMR3_ISTS)

  • Page 184: Software Event Register (Tmr3_Sw Evt)

    AT32F421 Series Reference Manual 14.2.4.6 Software event register (TMR3_SWEVT) Register Reset value Type Description Kept at its default value. Bit 15: 7 Reserved 0x000 resd Trigger event triggered by software This bit is set by software to generate a trigger event.
  • Page 185 AT32F421 Series Reference Manual －OWCDIR=1, C1ORAW is high once TMR3_ C1DT <TMR3_CVAL, else low. Note: In the configurations othern than 000’, the C1OUT is connected to C1ORAW. The C1OUT output level is not only subject to the changes of C1ORAW, but also the output polarity set by CCTRL.

  • Page 186: Channel Mode Register2 (Tmr3_Cm2)

    AT32F421 Series Reference Manual Channel 1 input divider This field defines Channel 1 input divider. 00: No divider. An input capture is generated at each active edge. Bit 3: 2 C1IDIV 01: An input compare is generated every 2 active edges...

  • Page 187: Channel Control Register (Tmr3_Cctrl)

    AT32F421 Series Reference Manual This field is used to define the direction of the channel 1 (input or output), and the selection of input pin when C3EN=’0’: 00: Output 01: Input, C3IN is mapped on C3IRAW 10: Input, C3IN is mapped on C4IRAW 11: Input, C3IN is mapped on STCI.

  • Page 188: Division Value (Tmr3_Div)

    AT32F421 Series Reference Manual 14.2.4.11 Division value (TMR3_DIV) Register Reset value Type Description Divider value The counter clock frequency f /(DIV[15: CK_CNT TMR_CLK Bit 15: 0 0x0000 0]+1). DIV contains the value written at an overflow event. 14.2.4.12 Period register (TMR3_PR)

  • Page 189: Channel 4 Data Register (Tmr3_C4Dt)

    AT32F421 Series Reference Manual 14.2.4.16 Channel 4 data register (TMR3_C4DT) Register Reset value Type Description Bit 31: 16 0x0000 Reserved resd Kept at its defaut value Channel 4 data register When the channel 4 is configured as input mode: The C4DT is the CVAL value stored by the last channel...

  • Page 190: General-Purpose Timer (Tmr14)

    AT32F421 Series Reference Manual 14.3 General-purpose timer (TMR14) 14.3.1 TMR14 introduction The general-purpose timer TMR14 consists of a 16-bit counter supporting upcounting mode. The timer can be synchronized together with other timers. 14.3.2 TMR14 main features  Source of count clock : internal clock ...

  • Page 191: Counting Mode

    AT32F421 Series Reference Manual Figure 14-34 Counter timing with prescaler value changing from 1 to 4 TMR_CLK CK_CNT COUNTER DIV[15：0] PR[15：0] OVFIF Clear 14.3.3.2 Counting mode The general-purpose timer TMR14 consists of a 16-bit counter supporting upcounting mode. The TMR14_PR register is loaded with the counter value. The value in the TMR14_PR is immediately moved to the shadow register by deault.

  • Page 192: Tmr Input Function

    AT32F421 Series Reference Manual 14.3.3.3 TMR input function The TMR14 timer has one independent channel that can be configured as input or output. As input, the channel can be used for the filtering, selection, division and input capture of the input signals.

  • Page 193: Tmr Output Function

    AT32F421 Series Reference Manual 14.3.3.4 TMR output function The TMR output consists of a comparator and an output controller. It is used to program the period, duty cycle and polarity of the output signal. Figure 14-39 Capture/compare channel output stage (channel 1)

  • Page 194: Debug Mode

    AT32F421 Series Reference Manual Figure 14-41 Upcounting mode and PWM mode A TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL[2：0] C1DT[15：0] C1ORAW CIDT[15：0] C1ORAW C1DT[15：0] C1ORAW >32 C1DT[15：0] C1ORAW 14.3.3.5 Debug mode When the microcontroller enters debug mode (Cortex -M4 core halted), the TMR14 counter stops counting by setting the TMR14_PAUSE in the DEBUG module.

  • Page 195: Control Register1 (Tmr14_Ctrl1)

    AT32F421 Series Reference Manual 14.3.4.1 Control register1 (TMR14_CTRL1) Register Reset value Type Description Bit 15: 10 Reserved 0x00 resd Kept at its default value Clock divider 00: Normal Bit 9: 8 CLKDIV 01: Divided by 2 10: Divided by 4...

  • Page 196: Software Event Register (Tmr14_Swevt)

    AT32F421 Series Reference Manual − An overflow event is generated when OVFG= 1 in the TMR14_SWEVE register; − An overflow event is generated when the counter CVAL is reinitialized by a trigger event. 14.3.4.4 Software event register (TMR14_SWEVT) Register Reset value...
  • Page 197 AT32F421 Series Reference Manual In PWM mode A or B, this bit is used to accelerate the channel 1 output’s response to the trigger event. 0: Need to compare the CVAL with C1DT before generating an output 1: No need to compare the CVAL and C1DT. An output is generated immediately when a trigger event occurs.

  • Page 198: Channel Control Register (Tmr14_Cctrl)

    AT32F421 Series Reference Manual 14.3.4.6 Channel control register (TMR14_CCTRL) Register Reset value Type Description Bit 15: 4 Reserved resd Kept at its default value. Channel 1 complementary polarity Bit 3 C1CP Pleaser refer to C1P description. Bit 2 Reserved resd Kept at its default value.

  • Page 199: General-Purpose Timer (Tmr15)

    AT32F421 Series Reference Manual 14.4 General-purpose timer (TMR15) 14.4.1 TMR15 introduction The general-purpose timer TMR14 consists of a 16-bit counter supporting upcounting mode. It has two capture/compare registers, and two independent channels to achieve dead-time insert, input capture and programmable PWM output.

  • Page 200: Figure 14-44 Block Diagram Of External Clock Mode A

    AT32F421 Series Reference Manual External clock (TRGIN/EXT) The counter can be clocked by TRGIN signal. When SMSEL=3’111, external clock mode A is selected. Set the STIS[2: 0] bit to select TRGIN signal to drive the counter to start counting. Figure 14-44 Block diagram of external clock mode A...

  • Page 201: Counting Mode

    AT32F421 Series Reference Manual 14.4.3.2 Counting mode The TMR15 timer supports several counting modes to meet different application scenarios. It has an internal 16-bit up counter. The TMR15_PR register is loaded with the counter value. The value in the TMR15_PR is immediately moved to the shadow register by deault. When the periodic buffer is enabled (PRBEN=1), the value in the TMR15_PR register is transferred to the shadow register only at an overflow event.

  • Page 202: Tmr Input Function

    AT32F421 Series Reference Manual 14.4.3.3 TMR input function The TMR15 timer has two independent channels, each of which can be configured as input or output. As input, the channel can be used for the filtering, selection, division and input capture of the input signals.

  • Page 203: Tmr Output Function

    AT32F421 Series Reference Manual 14.4.3.4 TMR output function The TMR output consists of a comparator and an output controller. It is used to program the period, duty cycle and polarity of the output signal. The advanced-control timer output function varies from one channel to one channel.

  • Page 204: Figure 14-54 C1Oraw Toggles When Counter Value Matches The C1Dt Value

    AT32F421 Series Reference Manual gives an example of the combination between upcounting mode and PWM mode A. The Figure 14-55 output signal behaves when PR=0x32 but CxDT is configured with a different value. gives an example of the combination between upcounting mode and one-pulse PWM Figure 14-56 mode B.

  • Page 205: Tmr Break Function

    AT32F421 Series Reference Manual Setting both CxEN and CxCEN bits, and using DTC[7:0] bit to insert dead-time of different durations. After the dead-time insertion, the rising edge of the CxOUT is delayed compared to the rising edge of the reference signal; the rising edge of the CxCOU is delayed compared to the falling edge of the reference signal.

  • Page 206: Tmr Synchronization

    AT32F421 Series Reference Manual Figure 14-58 Example of TMR break function AOEN CxORAW CxEN CxCEN CxIOS CxCIOS CxOUT Delay CxCOUT Delay Delay 14.4.3.6 TMR synchronization The timers are linked together internnaly for timer synchronization. Master timer is selected by setting the PTOS[2: 0] bit;...

  • Page 207: Debug Mode

    AT32F421 Series Reference Manual Figure 14-60 Example of suspend mode TMR_CLK CI1F1 TMR_EN CNT_CLK COUNTER PR[15:0] DIV[15:0] STIS[2：0] SMSEL[2：0] Slave mode: Trigger mode The counter can start counting on the rising edge of a selected trigger input (TMR_EN=1) Figure 14-61 Example of trigger mode...

  • Page 208: Tmr15 Registers

    AT32F421 Series Reference Manual 14.4.4 TMR15 registers These peripheral registers must be accessed by word (32 bits). TMR15 registers are mapped into a 16-bit addressable space. Table 14-10 TMR10 register map and reset value Register name Register Reset value TMR15_CTRL1...

  • Page 209: Control Register2 (Tmr15_Ctrl2)

    AT32F421 Series Reference Manual 14.4.4.2 Control register2 (TMR15_CTRL2) Register Reset value Type Description Bit 31: 11 Reserved resd Kept at its default value. Bit 10 C2IOS Channel 2 idle output state Channel 1 complementary idle output state Output OFF (OEN = 0), after dead-timer generation:...

  • Page 210: Tmr15 Dma/Interrupt Enable Register (Tmr15_Iden)

    AT32F421 Series Reference Manual Bit 3 Reserved resd Kept at its default value Subordinate TMR mode selection 000: Slave mode is disabled 100: Reset mode — Rising edge of the TRGIN input reinitializes the counter 101: Suspend mode — The counter starts counting when...

  • Page 211: Tmr15 Interrupt Status Register (Tmr15_Ists)

    AT32F421 Series Reference Manual 14.4.4.5 TMR15 interrupt status register (TMR15_ISTS) Register Reset value Type Description Kept at its default value. Bit 15: 11 Reserved resd Channel 2 recapture flag Bit 10 C2RF rw0c Please refer to C1RF description. Channel 1 recapture flag This bit indicates whether a recapture is detected when C1IF=1.

  • Page 212: Tmr15 Software Event Register (Tmr15_Sw Evt)

    AT32F421 Series Reference Manual Overflow event is generated when the counter value CVAL is re-initiated by a trigger event. 14.4.4.6 TMR15 software event register (TMR15_SWEVT) Register Reset value Type Description Kept at its default value. Bit 15: 8 Reserved resd Brake event triggered by software This bit is set to generate a brake event by software.
  • Page 213 AT32F421 Series Reference Manual Channel 1 output switch enable Bit 7 C1OSEN 0: C1ORAW is not affected b EXT input 1: When EXT nput level is high, C1ORAW is cleared. Channel 1 output control This field defines the behavior of the original signal C1ORAW.
  • Page 214 AT32F421 Series Reference Manual Input capture mode: Register Reset value Type Description Channel 2 digital filter Bit 15: 12 C2DF Channel 2 input divider Bit 11: 10 C2IDIV Channel 2 configuration This field is used to define the direction of the channel 2 (input or output), and the selection of input pin when C2EN=’0’:...

  • Page 215: Tmr15 Channel Control Register (Tmr15_Cctrl)

    AT32F421 Series Reference Manual 14.4.4.8 TMR15 channel control register (TMR15_CCTRL) Register Reset value Type Description Kept at its default value. Bit 15: 8 Reserved resd Channel 2 complementary polarity Bit 7 C2CP This bit defines the active edge for input signals. Refer to C1P description.

  • Page 216: Table 14-11 Complementary Output Channel Cxout And Cxcout Control Bits With Break Function

    AT32F421 Series Reference Manual Table 14-11 Complementary output channel CxOUT and CxCOUT control bits with break function Control bit Output state (1) FCSODIS FCSOEN CxEN CxCEN OEN bit CxOUT output state CxCOUT output state Output disabled Output disabled (no driven by the timer)

  • Page 217: Tmr15 Counter Value (Tmr15_Cval)

    AT32F421 Series Reference Manual 14.4.4.9 TMR15 Counter value (TMR15_CVAL) Register Reset value Type Description Bit 15: 0 CVAL Counter value 14.4.4.10 TMR15 Division value (TMR15_DIV) Register Reset value Type Description Divider value The counter clock frequency f /(DIV[15: CK_CNT TMR_CLK 0]+1).

  • Page 218: Tmr15 Break Register (Tmr15_Brk)

    AT32F421 Series Reference Manual 14.4.4.15 TMR15 break register (TMR15_BRK) Register Reset value Type Description Bit 31: 17 Reserved resd Kept at its default value. Brake input filter This field is used to configure the filter for brake input. If the number of filter is N, it indicates that the input edge can pass through the filter only after N sampling events.

  • Page 219: Tmr15 Dma Control Register (Tmr15_Dmactrl)

    AT32F421 Series Reference Manual 01: Write protection level 3, and the following bits are write protected: TMR1_BRK: DTC, BRKEN, BRKV and AOEN TMR1_CTRL2: CxIOS and CxCIOS 10: Write protection level 2. The following bits and all bits in leve 3 are write protected:...

  • Page 220: General-Purpose Timer (Tmr16 And Tmr17)

    AT32F421 Series Reference Manual 14.5 General-purpose timer (TMR16 and TMR17) 14.5.1 TMR16 and TMR17 introduction The general-purpose timers TMR16 and TMR17 consist of a 16-bit counter supporting upcounting mode. Each of them has a capture/compare register, and an independent channels to achieve dead-time insert, input capture and programmable PWM output.

  • Page 221: Tmr Input Function

    AT32F421 Series Reference Manual Upcounting mode In upcounting mode, the counter counts from 0 to the value programmed in the TMRx_PR register, restarts from 0, and generates a counter overflow event, with the OVFIF bit being set. If the overflow event is disabled, the register is no longer reloaded with the preload and re-loaded value after counter overflow occurs, otherwise, the prescaler and re-loaded value will be updated at an overflow event.

  • Page 222: Tmr Output Function

    AT32F421 Series Reference Manual Figure 14-68 Channel 1 input stage Filter Downcounter C1IRAW Capture/ Polarity C1IPS C1IFP1 compare divider C1IN selection select C1IF_rising Edge detector C1IF_falling Input mode In input mode, the TMRx_CxDT registers latch the current counter values after the selected triggle signal is detected, and the capture compare interrupt flag bit (CxIF) is set.

  • Page 223: Figure 14-70 C1Oraw Toggles When Counter Value Matches The C1Dt Value

    AT32F421 Series Reference Manual  Output compare mode: Set CxOCTRL=3’b001/010/011 to enable output compare mode. In this case, when the counter value matches the value of the CxDT register, the CxORAW is forced high, low or toggling.  One-pulse mode：This is a particular case of PWM mode. Set OCMEN=1 to enable one-pulse mode.

  • Page 224: Tmr Break Function

    AT32F421 Series Reference Manual Figure 14-72 One-pulse mode COUNTER PR[15：0] C1DT[15：0] TRGIN C1ORAW C1OUT Dead-time insertion The channel 1 of the TMR16 and TMR17 contains a set of reverse channel output. This function is enabled by the CxCEN bit and its polarity is defined by CxCP. Refer to Table 14-13 for more information about the output state of CxOUT and CxCOUT.

  • Page 225: Debug Mode

    AT32F421 Series Reference Manual of synchronization logic on OEN, the dead-time duration is usually longer than usual (around 2 clk_tmr clock cycles) ― If FCSODIS=0, the timer releases the enable output, otherwise, it keeps the enable output; the enable output becomes high as soon as one of the CxEN and CxCEN bits becomes high.

  • Page 226: Tmr16 And Tmr17 Registers

    AT32F421 Series Reference Manual 14.5.4 TMR16 and TMR17 registers These peripheral registers must be accessed by word (32 bits). TMR16 and TMR17 register are mapped into a 16-bit addressable space. Table 14-12 TMR16 and TMR17 register map and reset value...

  • Page 227: Tmr16 And Tmr17 Control Register2 (Tmrx_Ctrl2)

    AT32F421 Series Reference Manual 14.5.4.2 TMR16 and TMR17 control register2 (TMRx_CTRL2) Register Reset value Type Description Bit 30: 10 Reserved resd Kept at its default value. Channel 1 complementary idle output state OEN = 0 after dead-time: Bit 9 C1CIOS...

  • Page 228: Tmr16 And Tmr17 Interrupt Status Register (Tmrx_Ists)

    AT32F421 Series Reference Manual 14.5.4.4 TMR16 and TMR17 interrupt status register (TMRx_ISTS) Register Reset value Type Description Bit 15: 10 Reserved resd Kept at its default value. Channel 1 recapture flag This bit indicates whether a recapture is detected when C1IF=1.

  • Page 229: Tmr16 And Tmr17 Channel Mode Register1 (Tmrx_Cm1)

    AT32F421 Series Reference Manual 0: No effect 1: Generate a channel 1 event. Overflow event triggered by software This bit is set by software to generate an overflow event. Bit 0 OVFSWTR 0: No effect 1: Generate an overflow event.
  • Page 230 AT32F421 Series Reference Manual This field is used to define the direction of the channel 1 (input or output), and the selection of input pin when C1EN=’0’: 00: Output 01: Input, C1IN is mapped on C1IRAW 10: Input, C1IN is mapped on C2IRAW 11: Input, C1IN is mapped on STCI.

  • Page 231: Tmr16 And Tmr17 Channel Control Register (Tmrx_Cctr L)

    AT32F421 Series Reference Manual 14.5.4.7 TMR16 and TMR17 channel control register (TMRx_CCTRL) Register Reset value Type Description Bit 15: 4 Reserved resd Kept its default value. Channel 1 complementary polarity Bit 3 C1CP 0: C1COUT is active high. 1: C1COUT is active low.

  • Page 232: Tmr16 And Tmr17 Counter Value (Tmrx_Cval)

    AT32F421 Series Reference Manual Output disabled (no driven by the timer) Asynchronously: CxOUT=CxP, Cx_EN=0, CxCOUT=CxCP, CxCEN=0; If the clock is present: after a dead-time, CxOUT=CxIOS, CxCOUT=CxCIOS, assuming that CxIOS and CxCIOS do not correspond to CxOUT and CxCOUT active level.

  • Page 233: Tmr16 And Tmr17 Break Register (Tmrx_Brk)

    AT32F421 Series Reference Manual 14.5.4.13 TMR16 and TMR17 break register (TMRx_BRK) Register Reset value Type Description Bit 31: 16 Reserved resd Kept at its default value. Output enable This bit is used to enable the output of CxOUT and CxCOUT for those channels that are configured as output.

  • Page 234: Tmr16 And Tmr17 Dma Control Register (Tmrx_Dmactrl)

    AT32F421 Series Reference Manual 14.5.4.14 TMR16 and TMR17 DMA control register (TMRx_DMACTRL) Register Reset value Type Description Bit 15:13 Reserved resd Kept at its default value. DMA transfer bytes This field defines the number of DMA transfers: 00000: 1 byte...

  • Page 235: Advanced-Control Timers (Tmr1)

    AT32F421 Series Reference Manual 14.6 Advanced-control timers (TMR1) 14.6.1 TMR1 introduction The advanced-control timer TMR1 consists of a 16-bit counter supporting up, down or up/down counting modes, four capture/compare registers, and four independent channels to achieve embedded dead-time, input capture and programmable PWM output.

  • Page 236: Figure 14-76 Control Circuit With Ck_Int Divided By 1

    AT32F421 Series Reference Manual Figure 14-76 Control circuit with CK_INT divided by 1 CK_INT TMREN COUNTER External clock (TRGIN/EXT) The counter clock can be provided by two external clock sources, namely, TRGIN and EXT signals. When SMSEL=3’111, external clock mode A is selected. Set the STIS[2: 0] bit to select TRGIN signal to drive the counter to start counting.

  • Page 237: Counting Mode

    AT32F421 Series Reference Manual Figure 14-80 Counter timing in external clock mode B TMR_CLK CNT_CLK COUNTER ESDIV[1:0] ESF[3:0] 0000 OVFIF Clear Internal trigger input (ISx) Timer synchronization allows interconnection between several timers. The TMR_CLK of one timer can be provided by the TRGOUT signal output by another timer. Set the STIS[2: 0] bit to select internal trigger signal to enable counting.

  • Page 238: Figure 14-82 Overflow Event When Prben=0

    AT32F421 Series Reference Manual Figure 14-82 Overflow event when PRBEN=0 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Figure 14-83 Overflow event when PRBEN=1 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Downcounting mode In downcounting mode, the counter counts from the value programmed in the TMR1_PR register down to 0, and restarts from the value programmed in the TMR1_PR register, and generates a counter underflow event.

  • Page 239: Figure 14-86 Ovfif When Rpr=2

    AT32F421 Series Reference Manual Repetition counter mode: The repletion counter mode is enabled when the repetition counter value is not equal to 0. In this mode, the repetition counter is decremented at each counter overflow. An overflow event is generated when the repetition counter reaches 0.

  • Page 240: Tmr Input Function

    AT32F421 Series Reference Manual 14.6.3.3 TMR input function The TMR1 has four independent channels. Each channel can be configured as input or output. As input, the channel can be used for the filtering, selection, division and input capture of the input signals.

  • Page 241: Tmr Output Function

    AT32F421 Series Reference Manual 14.6.3.4 TMR output function The TMR output consists of a comparator and an output controller. It is used to program the period, duty cycle and polarity of the output signal. Figure 14-90 Output stage for channel 1 to 3...

  • Page 242: Figure 14-92 C1Oraw Toggles When Counter Value Matches The C1Dt Value

    AT32F421 Series Reference Manual gives an example of the combination between up/down counting mode and PWM mode Figure 14-94 A. The output signal behaves when PR=0x32 but CxDT is configured with a different value. gives an example of the combination between upcounting mode and one-pulse PWM Figure 14-95 mode B.

  • Page 243: Figure 14-95 One-Pulse Mode

    AT32F421 Series Reference Manual Figure 14-95 One-pulse mode COUNTER PR[15：0] C1DT[15：0] TRGIN C1ORAW C1OUT CxORAW clear When the CxOSEN bit is set, the CxORAW signal for a given channel is cleared by applying a high level to the EXT input. The CxORAW signal remains unchanged until the next overflow event.

  • Page 244: Tmr Break Function

    AT32F421 Series Reference Manual 14.6.3.5 TMR break function When the break function is enabled (BRKEN=1), the CxOUT and CxCOUT are jointly controlled by OEN, FCSODIS, FCSOEN, CxIOS and CxCIOS. But, CxOUT and CxCOUT cannot be set both to active level at the same time.

  • Page 245: Debug Mode

    AT32F421 Series Reference Manual Figure 14-99 Example of reset mode TMR_CLK COUNTER PR[15:0] DIV[15:0] STIS[2：0] SMSEL[2：0] CI1F1 OVFIF TRGIF Slave mode: Suspend mode In this mode, the counter is controlled by a selected trigger input. The counter starts counting when the trigger input is high and stops as soon as the trigger input is low.

  • Page 246: Tmr1 Registers

    AT32F421 Series Reference Manual 14.6.4 TMR1 registers These peripheral registers must be accessed by word (32 bits). TMR1 register are mapped into a 16-bit addressable space. Table 14-16 TMR1 register map and reset value Register Offset Reset value TMR1_CTRL1 0x00...

  • Page 247: Tmr1 Control Register2 (Tmr1_Ctrl2)

    AT32F421 Series Reference Manual 0: Up； 1: Down One cycle mode enable This bit is use to select whether to stop counting at an Bit 3 OCMEN update event 0: The counter does not stop at an update event 1: The counter stops at an update event...

  • Page 248: Tmr1 Slave Timer Control Register (Tmr1_Stctrl)

    AT32F421 Series Reference Manual This bit acts on channels that have complementary output. 0: CxEN, CxCEN and CxOCTRL bits are not buffered. 1: CxEN, CxCEN and CxOCTRL bits are not buffered. 14.6.4.3 TMR1 slave timer control register (TMR1_STCTRL) Register Reset value...

  • Page 249: Tmr1 Dma/Interrupt Enable Register (Tmr1_Iden)

    AT32F421 Series Reference Manual reinitializes the counter 101: Suspend mode - The counter starts counting when the TRGIN is high 110: Trigger mode - A trigger event is generated at the rising edge of the TRGIN input 111: External clock mode A - Rising edge of the TRGIN...

  • Page 250: Tmr1 Interrupt Status Register (Tmr1_Ists)

    AT32F421 Series Reference Manual 14.6.4.5 TMR1 interrupt status register (TMR1_ISTS) Register Reset value Type Description Bit 15: 13 Reserved resd Kept at its default value. Channel 4 recapture flag C4RF rw0c Bit 12 Please refer to C1RF description. Channel 3 recapture flag...

  • Page 251: Tmr1 Software Event Register (Tmr1_Sw Evt)

    AT32F421 Series Reference Manual 14.6.4.6 TMR1 software event register (TMR1_SWEVT) Register Reset value Type Description Bit 15: 8 Reserved 0x00 resd Kept at its default value. Break event triggered by software This bit is set by software to generate a break event.
  • Page 252 AT32F421 Series Reference Manual 000: Disconnected. C1ORAW is disconnected from C1OUT; 001: C1ORAW is high when TMR1_CVAL=TMR1_C1DT 010: C1ORAW is low when TMR1_CVAL=TMR1_C1DT 011: Switch C1ORAW level when TMR1_CVAL=TMR1_C1DT 100: C1ORAW is forced low 101: C1ORAW is forced high. 110: PWM mode A －OWCDIR=0, C1ORAW is high once...

  • Page 253: Tmr1 Channel Mode Register2 (Tmr1_Cm2)

    AT32F421 Series Reference Manual 0000: No filter, sampling is done at f ������ 1000: f /8, N=6 ���������������� ������ 0001: f , N=2 ���������������� ����_������ 1001: f /8, N=8 ���������������� ������ 0010: f , N=4 ���������������� ����_������ 1010: f /16, N=5 ����������������...

  • Page 254: Tmr1 Channel Control Register (Tmr1_Cctrl)

    AT32F421 Series Reference Manual This field is used to define the direction of the channel 1 (input or output), and the selection of input pin when C3EN=’0’: 00: Output 01: Input, C3IN is mapped on C3IRAW 10: Input, C3IN is mapped on C4IRAW 11: Input, C3IN is mapped on STCI.

  • Page 255: Table 14-17 Complementary Output Channel Cxout And Cxcout Control Bits With Break Function

    AT32F421 Series Reference Manual When the channel 1 is configured as output mode: 0: C1OUT is active high 1: C1OUT is active low When the channel 1 is configured as input mode: 0: C1IN active edge is on its rising edge. When used as external trigger, C1IN is not inverted.

  • Page 256: Tmr1 Counter Value (Tmr1_Cval)

    AT32F421 Series Reference Manual Note: If the two outputs of a channel are not used (CxEN = CxCEN = 0), CxIOS, CxCIOS, CxP and CxCP must be cleared. Note: The state of the external I/O pins connected to the complementary CxOUT and CxCOUT channels depends on the CxOUT and CxCOUT channel state and the GPIO and the IOMUX registers.

  • Page 257: Tmr1 Channel 3 Data Register (Tmr1_C3Dt)

    AT32F421 Series Reference Manual 14.6.4.16 TMR1 channel 3 data register (TMR1_C3DT) Register Reset value Type Description Channel 3 data register When the channel 3 is configured as input mode: The C3DT is the CVAL value stored by the last channel...

  • Page 258: Tmr1 Dma Control Register (Tmr1_Dmactrl)

    AT32F421 Series Reference Manual TMR1_BRK: DTC, BRKEN, BRKV and AOEN TMR1_CTRL2: CxIOS and CxCIOS 10: Write protection level 2. The following bits and all bits in leve 3 are write protected: TMR1_CCTRL: CxP and CxCP TMR1_BRK: FCSODIS and FCSOEN 11: Write protection level 1. The following bits and all bits...

  • Page 259: Window Watchdog Timer (Wwdt)

    AT32F421 Series Reference Manual 15 Window watchdog timer (WWDT) 15.1 WWDT introduction The window watchdog downcounter must be reloaded in a limited time window to prevent the watchdog circuits from generating a system reset. The window watch dog is used to detect the occurrence of system malfunctions.

  • Page 260: Debug Mode

    AT32F421 Series Reference Manual Table 15-1 Minimum and maximum timeout value when PCLK1=72 MHz Prescaler Min. Timeout value Max. Timeout value 56.5μs 3.64ms 113.5μs 7.28ms 227.5μs 14.56ms 455μs 29.12ms Figure 15-2 Window watchdog timing diagram 15.4 Debug mode When the microcontroller enters debug mode (Cortex -M4 core halted), the WWDT counter stops counting by setting the WWDT_PAUSE in the DEBUG module.

  • Page 261: Configuration Register (Wwdt_Cfg)

    AT32F421 Series Reference Manual 15.5.2 Configuration register (WWDT_CFG) Register Reset value Type Description Bit 31: 10 Reserved 0x000000 resd Kept at its default value. Reload counter interrupt Bit 9 RLDIEN 0: Disabled 1: Enabled Clock division value 00: PCLK1 divided by 4096...

  • Page 262: Watchdog Timer (Wdt)

    AT32F421 Series Reference Manual 16 Watchdog timer (WDT) 16.1 WDT introduction The WDT is driven by a dedicated low-speed clock (LICK). Due to the lower clock accuracy of LICK, the WDT is best suited to the applications that have lower timing accuracy and can run independently outside the main application.

  • Page 263: Debug Mode

    AT32F421 Series Reference Manual Table 16-1 WDT timeout period (LICK=40kHz) Min.timeout (ms) Max. timeout (ms) Prescaler divider DIV[2: 0] bits RLD[11: 0] = 0x000 RLD[11: 0] = 0xFFF 409.6 819.2 1638.4 3276.8 6553.6 /128 13107.2 /256 (6 or 7) 26214.4 16.4 Debug mode...

  • Page 264: Reload Register (Wdt_Rld)

    AT32F421 Series Reference Manual 16.5.3 Reload register (WDT_RLD) (Reset in Standby mode) Register Reset value Type Description Bit 31: 12 Reserved 0x00000 resd Kept at its default value. Reload value The write protection must be unlocked in order to enable...

  • Page 265: Enhanced Real-Time Clock (Ertc)

    AT32F421 Series Reference Manual 17 Enhanced real-time clock (ERTC) 17.1 ERTC introduction The real-time clock provides a calendar clock function. The time and date can be modified by modifying the ERTC_TIME and ERTC_DATE register. The ERTC module is in battery powered domain, which means that it keeps running and free from the influence of system reset and VDD power off as long as VBAT is powered.

  • Page 266: Ertc Initialization

    AT32F421 Series Reference Manual ck_a ck_b To obtain ck_b with frequency of 1 Hz, DIVA=127, DIVB=255, and 32.768 kH LEXT should be used. This ck_b is then used for calendar update. 17.3.2 ERTC initialization ERTC register write protection After a power-on reset, all ERTC registers are write protected except ERTC_STS[14:8], ERTC_TAMP and ERTC_BPRx registers.
  • Page 267 AT32F421 Series Reference Manual 2. Wait until the initialization flag INITF bit is set 3. Configure DIVB and DIVA. 4. Configure the clock and calendar values. 5. Leave the initialization mode by clearing the IMEN bit. Wait until the UPDF bit is set, indicating the completion of the calendar update.

  • Page 268: Ertc Calibration

    AT32F421 Series Reference Manual 17.3.3 ERTC calibration Smooth digital calibration: Smooth digital calibration has a higher and well-distributed performance than the coarse digital calibration. The calibration is performed by increasing or decreasing ERTC_CLK in an evenly manner. The smooth digital calibration period is around 2 ERTC_CLK (32 seconds) when the ERTC_CLK is 32.768 kHz.

  • Page 269: Tamper Detection

    AT32F421 Series Reference Manual 17.3.5 Tamper detection The ERTC offers one tamper detection mode: TAMP1. It can be configured as a level detection with filter or edge detection. TAMP1 is mapped onto the tamper pin ERTC_MUX1. The TP1F will be set when a valid tamper event is detected. An interrupt will also be generated if a tamper detection interrupt is enabled.

  • Page 270: Ertc Registers

    AT32F421 Series Reference Manual Table 17-2 ERTC low-power mode wakeup Wake Clock sources Events Wake up Sleep Wakeup Standby Deepsleep Alarm clock A √ × × HEXT Time stamp √ × × Tamper event √ × × Alarm clock A √...

  • Page 271: Ertc Date Register (Ertc_Date)

    AT32F421 Series Reference Manual Bit 15 Reserved resd Kept at its default value. Bit 14: 12 Minute tens Bit 11: 8 Minute units Bit 7 Reserved resd Kept at its default value. Bit 6: 4 Second tens Bit 3: 0 Second units 17.4.2 ERTC date register (ERTC_DATE)

  • Page 272: Ertc Initialization And Status Register (Ertc_Sts)

    AT32F421 Series Reference Manual Note: The next second takes effect when this bit is set (don’t set this bit when the hour is being incremented) Timestamp interrupt enable Bit 15 TSIEN 0: Timestamp interrupt disabled 1: Timestamp interrupt enabled Bit 14: 13...

  • Page 273: Ertc Divider Register (Ertc_Div)

    AT32F421 Series Reference Manual Bit 10: 9 Reserved resd Kept at its default value. Alarm clock A flag 0: No alarm clock event Bit 8 ALAF rw0c 1: Alarm clock event occurs Note: The clearing operation of this bit takes effect after two APB_CLK cycles.

  • Page 274: Ertc Write Protection Register (Ertc_Wp)

    AT32F421 Series Reference Manual AM/PM 0: AM Bit 22 AMPM 1: PM Note: This bit is applicable for 12-hour format only. It is 0 for 24-hour format. Bit 21: 20 Hour tens Bit 19: 16 Hour units Minute mask Bit 15...

  • Page 275: Ertc Time Stamp Date Register (Ertc_Tsdt)

    AT32F421 Series Reference Manual Bit 11: 8 MU Minute units Bit 7 Reserved resd Kept at its default value Bit 6: 4 Second tens Bit 3: 0 Second units Note: The content of this register is valid only when the TSF is set in the ERTC_STS register. It is cleared when TSF bit is reset.
  • Page 276 AT32F421 Series Reference Manual Tamper detection pull-up Bit 15 TPPU 0: Tamper detection pull-up enabled 1: Tamper detection pull-up disabled Tamper detection pre-charge time 0: 1 ERTC_CLK cycle Bit 14: 13 TPPR 1: 2 ERTC_CLK cycles 2: 4 ERTC_CLK cycles...

  • Page 277: Ertc Alarm Clock A Subsecond Register (Ertc_Alasbs)

    AT32F421 Series Reference Manual 17.4.15 ERTC alarm clock A subsecond register (ERTC_ ALASBS) Register Reset value Type Description Bit 31: 28 Reserved resd Kept at its default value Sub-second mask 0: No comparison. Alarm A doesn’t care about subseconds. 1: SBS[0] is compared...

  • Page 278: Analog-To-Digital Converter (Adc)

    AT32F421 Series Reference Manual 18 Analog-to-digital converter (ADC) 18.1 ADC introduction The ADC is a peripheral that converts an analog input signal into a 12-bit digital signal. Its sampling rate is as high as 2 MSPS. It has up to 18 channels for sampling and conversion.

  • Page 279: Adc Functional Overview

    AT32F421 Series Reference Manual Figure 18-1 ADC1 block diagram ADCDIV OCTESEL ADC prescaler PCLK2 ADCCLK TMR1_CH1 TMR1_CH2 OCTEN TMR1_CH3 TMR3_TRGOUT TMR15_CH1 EXINT11 ADC_IN0 OCSWTRG Trigger ADC_IN1 detection GPIO Ordinary ADC_IN14 conversion start Temp.sensor INTRV Channel manegement Ordinary Analog-to- channels V DDA...

  • Page 280: Internal Temperature Sensor

    AT32F421 Series Reference Manual channel conversion is interrupted, giving the priority to the preempted channel, and the ordinary channel continues its conversion at the end of the preempted channel conversion. If the ordinary channel trigger occurs during the preempted channel conversion, the ordinary channel conversion won’t start until the end of the preempted channel conversion.

  • Page 281: Trigger

    AT32F421 Series Reference Manual Calibration After power-on, enable ADC calibration by setting the ADCAL bit in the ADC_CTRL2 register. When the calibration is complete, the ADCAL bit is cleared by hardware and the conversion is started by software trigger. After each calibration, the calibration value is stored in ADC_ODT register, and then value is automatically sent back to the ADC so as to eliminate capacitance errors.

  • Page 282: Sampling And Conversion Sequence

    AT32F421 Series Reference Manual 18.4.2.3 Sampling and conversion sequence The sampling period can be configured by setting the CSPTx bit in the ADC_SPT1 and ADC_SPT2 registers. A single one conversion time is calculated with the following formula: A single one conversion tiem ( ADCCLK cycle ) = sampling time + 12.5 Example: If the CSPTx selects 1.5 cycles, then one conversion needs 1.5+12.5=14 ADCCLK cycles...

  • Page 283: Repetition Mode

    AT32F421 Series Reference Manual Figure 18-5 Preempted group auto conversion mode Sampling OCLEN=2, OSN1=ADC_IN5, OSN2=ADC_IN0, OSN3=ADC_IN5 Conversion PCLEN=1, PSN3=ADC_IN14, PSN4=ADC_IN1 Ordinary channel trigger ADC_IN5 ADC_IN0 ADC_IN5 ADC_IN14 ADC_IN1 CCE and CCE flag set PCCE flag set 18.4.3.3 Repetition mode The repetition mode is enabled by setting the RPEN bit in the ADC_CTRL2 register. When a trigger signal is detected, the ordinary channels will be converted repeatedly.

  • Page 284: Data Management

    AT32F421 Series Reference Manual Figure 18-7 Partition mode OCLEN=4, OCPCNT=1, OSN1=ADC_IN5, OSN2=ADC_IN0, OSN3=ADC_IN2, OSN4=ADC_IN1, OSN5=ADC_IN7 Ordinary channel Ordinary channel Ordinary channel Ordinary channel trigger trigger trigger trigger ADC_IN5 ADC_IN0 ADC_IN2 ADC_IN1 ADC_IN7 ADC_IN5 ADC_IN0 CCE flag set CCE flag set...

  • Page 285: Voltage Monitoring

    AT32F421 Series Reference Manual 18.4.5 Voltage monitoring The OCVMEN bit or PCVMEN bit in the ADC_CTRL1 register is used to enable voltage monitoring based on the converted data. The VMOR bit will be set if the converted result is outside the high threshold (ADC_VMHB register) or less than the low threshold (ADC_VMLB register).

  • Page 286: Adc Status Register (Adc_Sts)

    AT32F421 Series Reference Manual 18.5.1 ADC status register (ADC_STS) Accessible by words. Register Reset value Type Description Bit 31: 5 Reserved 0x0000000 resd Kept at its default value. Ordinary channel conversion start flag This bit is set by hardware and cleared by software (writing...

  • Page 287: Adc Control Register2 (Adc_Ctrl2)

    AT32F421 Series Reference Manual partitioned mode on ordinary channels. 0: Partitioned mode disabled on ordinary channels 1: Partitioned mode enabled on ordinary channels Preempted group automatic conversion enable after ordinary group Bit 10 PCAUTOEN 0: Preempted group automatic conversion disabled...
  • Page 288 AT32F421 Series Reference Manual 1: Enabled Trigger event select for ordinary channels conversion 000: Timer 1 CH1 event 001: Timer 1 CH2 event 010: Timer 1 CH3 event Bit 19: 17 OCTESEL 011: Unused. Do not configure. 100: Timer 3 TRGOUT event...

  • Page 289: Adc Sampling Time Register 1 (Adc_Spt1)

    AT32F421 Series Reference Manual When this bit is in OFF state, write an ON command can wake up The ADC from power-down mode. When this bit in ON state, write another ON command can start a regular group conversion. The application should pay attention to the fact that there...

  • Page 290: Adc Sampling Time Register 2 (Adc_Spt2)

    AT32F421 Series Reference Manual 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles Sample time selection of channel ADC_IN12 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles Bit 8: 6 CSPT12 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles...
  • Page 291 AT32F421 Series Reference Manual Sample time selection of channel ADC_IN7 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles Bit 23: 21 CSPT7 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles Sample time selection of channel ADC_IN6 000: 1.5 cycles...

  • Page 292: Adc Preempted Channel Data Offset Register

    AT32F421 Series Reference Manual 111: 239.5 cycles Sample time selection of channel ADC_IN1 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles Bit 5: 3 CSPT1 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles Sample time selection of channel ADC_IN0 000: 1.5 cycles...

  • Page 293: Adc Ordinary Sequence Register 1 (Adc_ Osq1)

    AT32F421 Series Reference Manual 18.5.9 ADC ordinary sequence register 1 ( ADC_ OSQ1) Accessible by words. Register Reset value Type Description Bit 31: 24 Reserved 0x00 resd Kept at its default value Ordinary conversion sequence length 0000: 1 conversion 0001: 2 conversions...

  • Page 294: Adc Preempted Sequence Register (Adc_ Psq)

    AT32F421 Series Reference Manual 18.5.12 ADC preempted sequence register ( ADC_ PSQ) Accessible by words. Register Reset value Type Description Bit 31: 30 Reserved resd Kept at its default value Preempted conversion sequence length 00: 1 conversion 01: 2 conversions...

  • Page 295: Comparator (Comp)

    AT32F421 Series Reference Manual 19 Comparator (COMP) 19.1 COMP introduction AT32F421 embeds a ultra-low-power comparator (CMP). They can be used for various purposes, such as, external analog signal monitor/control and wakeup from low-power mode, and working with other timers for pulse width measurement and PWM signal control.

  • Page 296: Design Tips

    AT32F421 Series Reference Manual 19.4 Design tips The following information can be used for design reference:  Input/Output configuration As a comparator input, the I/Os must be configuread as an analog mode. The comparator output can be remapped onto external I/Os.

  • Page 297: Glitch Filter

    AT32F421 Series Reference Manual 19.5.2 Glitch filter The interference filter can be used to filter glitches and noise. The sensitivity of the filter is controlled by the H_PULSE_CNT and L_PULSE_CNT bits. The sensitivity of the filter affects the number of the same consecutive sampling. The level change of a certain signal would not be regarded as valid before the consecutive sampling is detected on the filter input.

  • Page 298: Comparator Control And Status Reg Ister 1 (Comp_Ctrlsts)

    AT32F421 Series Reference Manual 19.6.1 Comparator control and status register 1 (COMP_CTRLSTS) Register Reset value Type Description Comparator write protected This bit can be written only once. It is set by software and cleared by system reset. It will latch all the contents in the...

  • Page 299: Glitch Filter Enable Register (G_Filter_En)

    AT32F421 Series Reference Manual 100: PA4 101: PA5 110: PA0 111: PA2 Comparator speed selection This bit is used to control the operating mode of the comparator in order to adjust speed and power consumption. Bit 3: 2 CMPSSEL 00: High speed/maximum power consumption...

  • Page 300: Glitch Filter Low Pulse Count (Low-Pulse)

    AT32F421 Series Reference Manual 19.6.4 Glitch filter low pulse count (LOW-PULSE) Register Reset value Type Description Bit 15: 6 Reserved 0x000 resd Kept at its default value. Low pulse Count level filter input sigal must wait H_PULSE_CNT+1 cycles before becoming active input, so that the output can turn low level.

  • Page 301: Infrared Timer (Irtmr)

    AT32F421 Series Reference Manual 20 Infrared timer (IRTMR) The IRTMR (Infrared Timer) is used to generate the IR_OUT signal that drives the infrared LED so as to achieve infrared control. The IR_OUT signals consists of a low-frequency modulation envelope and high-frequency carrier signals.

  • Page 302: Debug (Debug)

    AT32F421 Series Reference Manual 21 Debug (DEBUG) 21.1 Debug introduction Cortex™-M4 core provides poweful debugging features including halt and single step support, as well as trace function that is used for checking the details of the program execution. The debug features are implemented with a serial wire debug interface.
  • Page 303 AT32F421 Series Reference Manual 21.4.1 DEBUG device ID (DEBUG_IDCODE) MCU integrates an ID code that is used to identify MCU’s revision code. The DEBUG_IDCODE register is mapped on the external PPB bus at address 0xE0042000. This code is accessible by the JTAG or SW debug port or by the user code.
  • Page 304 AT32F421 Series Reference Manual 21.4.2 DEBUG control register (DEBUG_CTRL) This register is asynchronously reset by POR Reset (not reset by system reset). It can be written by the debugger under reset. Register Reset value Type Description Kept at its default value.
  • Page 305 AT32F421 Series Reference Manual mode 1: The whole 1.2V digital circuit is not unpowered in Standby mode, and the system clock is provided by the internal RC oscillator (HICK) Debug Deepsleep mode control bit 0: In Deepsleep mode, all clcoks in the 1.2V domain are disabled.
  • Page 306 AT32F421 Series Reference Manual 22 Revision history Document Revision History Date Version Revision Note Initial release. 2021.11.17 2.00 2021.11.17 Page 306 Ver 2.00...
  • Page 307 No license, express or implied, to any intellectual property right is granted by ARTERY herein regardless of the existence of any previous representation in any forms. If any part of this document involves third party’s products or services, it does NOT imply that ARTERY authorizes the use of the third party’s products or services, or permits any of the intellectual property, or guarantees any uses of the third party’s products or services...

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