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ARTERY AT32F421C8T7 Reference Manual

Arm-based 32-bit cortex-m4 mcu with 16 to 64 kb flash, slib, 10 timers, adc, 7 communication interfaces
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®
ARM
-based 32-bit Cortex
ADC, 7 communication interfaces
Feature
 Core: ARM®32-bit Cortex®-M4F CPU
− 120 MHz maximum frequency, with a
Memory Protection Unit (MPU), single-cycle
multiplication and hardware division
− DSP instructions
 Memories
− 16 to 64 KBytes of internal Flash memory
− 4 Kbytes of boot code area used as a
Bootloader or as a general instruction/data
memory (one-time-configured)
− sLib: configurable part of main Flash set as a
library area with code executable but
secured, non-readable
− 8 to 16 KBytes of SRAM
 Clock, reset and power control
− 2.4 V ~ 3.6 V application supply and I/Os
− Power-on reset (POR)/ low-voltage reset
(LVR), and power voltage monitor (PVM)
− 4 to 25 MHz crystal (HEXT)
− Internal 8 MHz factory-trimmed clock (HICK),
accuracy 1% at T
+105 °C
− Internal 40 kHz RC oscillator
− 32 kHz crystal oscillator (LEXT)
 Low power
− Sleep, Deepsleep, and Standby modes
 1 x 12-bit A/D converter (up to 15 input
channels)
− Conversion range: 0 V to 3.6 V
 1 x COMP, 5 x external input channels
and 1 x internal reference voltage
channel
 2 x operational amplifiers
 DMA: 5-channel DMA controller
− Peripherals supported: timers, ADC, I
SPI, I
2
C and USART
 Debug mode
− Serial wire debug (SWD) and JTAG
 Up to 39 fast GPIOs
− All mappable to external interrupt vectors
2022.11.11
®
-M4 MCU with 16 to 64 KB Flash, sLib, 10 timers,
=25 °C, 2 % at T
=-40 to
A
A
2
S,
AT32F421 Series Reference Manual
− Almost 5 V-tolerant
− All fast I/Os, registers accessible with f
 Up to 10 Timers (TMR)
− 1 x 16-bit 7-channel advanced timer, 6-channel
PWM output with dead-time generator and
emergency stop
− 5 x 16-bit timers, each with 4 IC/OC/PWM or
pulse counter and encoder input
− 1 x 16-bit basic timer
− 2 x Watchdog timers (WDT and WWDT)
− SysTick timer: 24-bit downcounter
 ERTC: enhanced RTC
 Up to 7 communication interfaces
− 2 x I
2
C interfaces (SMBus/PMBus support)
− 2 x USARTs/UART (ISO7816 interface, LIN,
IrDA and modem control)
− 2 x SPIs, both with I
− Infrared transmitter
 CRC Calculation Unit
 96-bit ID (UID)
 Packaging
− LQFP48 7 x 7 mm
− LQFP32 7 x 7 mm
− QFN32 5 x 5 mm
− QFN32 4 x 4 mm
− QFN28 4 x 4 mm
− TSSOP20 6.5 x 4.4 mm
 List of Models
Internal Flash
AT32F421C8T7, AT32F421K8T7
AT32F421K8U7, AT32F421K8U7-4
64 KBytes
AT32F421F8P7, AT32F421G8U7,
AT32F4212C8T7
AT32F421C6T7, AT32F421K6T7
32 KBytes
AT32F421K6U7, AT32F421K6U7-4
AT32F421F6P7, AT32F421G6U7
AT32F421C4T7, AT32F421K4T7
16 KBytes
AT32F421K4U7, AT32F421K4U7-4
AT32F421F4P7, AT32F421G4U7
Page 1
speed
AHB
2
S interface multiplexed
Model
Rev 2.02

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Summary of Contents for ARTERY AT32F421C8T7

  • Page 1  List of Models  1 x COMP, 5 x external input channels and 1 x internal reference voltage Internal Flash Model channel AT32F421C8T7, AT32F421K8T7  2 x operational amplifiers AT32F421K8U7, AT32F421K8U7-4 64 KBytes AT32F421F8P7, AT32F421G8U7,  DMA: 5-channel DMA controller AT32F4212C8T7 −...

  • Page 2: Table Of Contents

    AT32F421 Series Reference Manual Contents System architecture ..............25 System overview ................27 1.1.1 ARM Cortex -M4 processor ............27 1.1.2 Bit band ..................27 1.1.3 Interrupt and exception vectors ............ 29 1.1.4 System Tick (SysTick) ..............31 1.1.5 Reset ..................31 List of abbreviations for registers ..........
  • Page 3 AT32F421 Series Reference Manual 4.1.1 Clock sources ................45 4.1.2 System clock ................46 4.1.3 Peripheral clock ................46 4.1.4 Clock fail detector ............... 47 4.1.5 Auto step-by-step system clock switch .......... 47 4.1.6 Internal clock output ..............47 4.1.7 Interrupts ..................47 Reset ..................
  • Page 4 AT32F421 Series Reference Manual 5.4.1 Unlock/lock ................. 66 5.4.2 Erase operation ................66 5.4.3 Programming operation..............68 5.4.4 Read operation ................69 Flash memory protection .............. 69 5.5.1 Access protection ................ 69 5.5.2 Erase/program protection............. 70 Read access................70 Special functions ................. 70 5.7.1 Security library settings ...............
  • Page 5 AT32F421 Series Reference Manual General-purpose I/Os (GPIOs) ............82 Introduction ................. 82 Functional overview ..............82 6.2.1 GPIO structure ................82 6.2.2 GPIO reset status ................ 82 6.2.3 General-purpose input configuration ..........83 6.2.4 Analog input/output configuration ..........83 6.2.5 General-purpose output configuration ........... 83 6.2.6 GPIO port protection ..............
  • Page 6 AT32F421 Series Reference Manual 7.2.4 SCFG external interrupt configuration register3 (SCFG_ EXINTC3) 93 7.2.5 SCFG external interrupt configuration register4 (SCFG_ EXINTC4) 94 External interrupt/Event controller (EXINT) ........95 EXINT introduction ............... 95 Function overview and configuration procedure ......95 EXINT registers ................96 8.3.1 Interrupt enable register (EXINT_INTEN) ........
  • Page 7 AT32F421 Series Reference Manual 10.1 CRC introduction ............... 107 10.2 CRC registers ................107 10.2.1 Data register (CRC_DT).............. 107 10.2.2 Common data register (CRC_CDT) ..........107 10.2.3 Control register (CRC_CTRL) ............108 10.2.4 Initialization register (CRC_IDT) ..........108 C interface ................109 11.1 I C introduction ................
  • Page 8 AT32F421 Series Reference Manual 12.4 USART frame format and configuration ........136 12.5 DMA transfer introduction ............137 12.5.1 Transmission using DMA ............137 12.5.2 Reception using DMA ..............137 12.6 Baud rate generation ..............138 12.6.1 Introduction................138 12.6.2 Configuration ................138 12.7 Transmitter ................
  • Page 9 AT32F421 Series Reference Manual 13.2.6 DMA transfer ................153 13.2.7 Transmitter ................154 13.2.8 Receiver ..................154 13.2.9 Motorola mode ................155 13.2.10 Interrupts ................157 13.2.11 IO pin control ................158 13.2.12 Precautions ................158 13.3 I2S functional description ............158 13.3.1 I S introduction ................
  • Page 10 AT32F421 Series Reference Manual 14.1.3.3 Debug mode ................. 173 14.1.4 TMR6 registers ................174 14.1.4.1 TMR6 control register1 (TMRx_CTRL1) ........175 14.1.4.2 TMR6 control register2 (TMRx_CTRL2) ........175 14.1.4.3 TMR6 DMA/interrupt enable register (TMRx_IDEN) ....175 14.1.4.4 TMR6 interrupt status register (TMRx_ISTS) ......176 14.1.4.5 TMR6 software event register (TMRx_SW EVT) ......
  • Page 11 AT32F421 Series Reference Manual 14.2.4.18 DMA data register (TMR3_DMADT) ........202 14.3 General-purpose timer (TMR14) ..........203 14.3.1 TMR14 introduction ..............203 14.3.2 TMR14 main features ..............203 14.3.3 TMR14 functional overview ............203 14.3.3.1 Count clock ................203 14.3.3.2 Counting mode ..............204 14.3.3.3 TMR input function ..............
  • Page 12 AT32F421 Series Reference Manual 14.4.4.4 TMR15 DMA/interrupt enable register (TMR15_IDEN) ....229 14.4.4.5 TMR15 interrupt status register (TMR15_ISTS) ....... 230 14.4.4.6 TMR15 software event register (TMR15_SW EVT) ....231 14.4.4.7 TMR15 channel mode register1 (TMR15_CM1) ......231 14.4.4.8 TMR15 channel control register (TMR15_CCTRL) ....234 14.4.4.9 TMR15 Counter value (TMR15_CVAL) ........
  • Page 13 AT32F421 Series Reference Manual 14.5.4.14 TMR16 and TMR17 DMA control register (TMRx_DMACTRL) 255 14.5.4.15 TMR16 and TMR17 DMA data register (TMRx_DMADT) ..255 14.6 Advanced-control timers (TMR1) ..........256 14.6.1 TMR1 introduction ..............256 14.6.2 TMR1 main features ..............256 14.6.3 TMR1 functional overview ............
  • Page 14 AT32F421 Series Reference Manual 15.3 WWDT functional overview ............287 15.4 Debug mode ................288 15.5 WWDT registers ................ 288 15.5.1 Control register (WWDT_CTRL) ..........288 15.5.2 Configuration register (WWDT_CFG) ........... 289 15.5.3 Status register (WWDT_STS) ............289 Watchdog timer (WDT) ..............290 16.1 WDT introduction ...............
  • Page 15 AT32F421 Series Reference Manual 17.4.6 ERTC alarm clock A register (ERTC_ALA) ........301 17.4.7 ERTC write protection register (ERTC_WP) ......... 302 17.4.8 ERTC subsecond register (ERTC_SBS) ........302 17.4.9 ERTC time adjustment register (ERTC_TADJ) ......302 17.4.10 ERTC time stamp time register (ERTC_TSTM) ......302 17.4.11 ERTC time stamp date register (ERTC_TSDT) ......
  • Page 16 AT32F421 Series Reference Manual 18.5.2 ADC control register1 (ADC_CTRL1) ........... 314 18.5.3 ADC control register2 (ADC_CTRL2) ........... 315 18.5.4 ADC sampling time register 1 (ADC_SPT1) ........317 18.5.5 ADC sampling time register 2 (ADC_SPT2) ........318 18.5.6 ADC preempted channel data offset register x (ADC_ PCDTOx) (x=1..4) 18.5.7 ADC voltage monitor high threshold register (ADC_VWHB) ...
  • Page 17 AT32F421 Series Reference Manual Debug (DEBUG) ................332 22.1 Debug introduction ..............332 22.2 Debug and trace ................ 332 22.3 I/O pin control................332 22.4 DEBUG registers ............... 332 22.4.1 DEBUG device ID (DEBUG_IDCODE) .......... 333 22.4.2 DEBUG control register (DEBUG_CTRL) ........334 Revision history ................
  • Page 18 AT32F421 Series Reference Manual List of figures Figure 1-1 AT32F421 Series microcontrollers system architecture..............26 Figure 1-2 Internal block diagram of Cortex ® -M4 ..................27 Figure 1-3 Comparison between bit-band region and its alias region: image A ......... 27 Figure 1-4 Comparison between bit-band region and its alias region: image B .........
  • Page 19 AT32F421 Series Reference Manual Figure 12-10 TDC/TDBE behavior when transmitting ................139 Figure 12-11 Data sampling for noise detection ..................142 Figure 12-12 Tx/Rx swap ........................... 142 Figure 12-13 USART interrupt map diagram ..................... 143 Figure 13-1 SPI block diagram ........................149 Figure 13-2 SPI two-wire unidirectional full-duplex connection ..............
  • Page 20 AT32F421 Series Reference Manual Figure 14-22 Input/output channel 1 main circuit ..................185 Figure 14-23 Channel 1 input stage ......................185 Figure 14-24 PWM input mode configuration .................... 186 Figure 14-25 PWM input mode ........................186 Figure 14-26 Capture/compare channel output stage (channel 1 to 4) ............ 187 Figure 14-27 C1ORAW toggles when counter value matches the C1DT value ........
  • Page 21 AT32F421 Series Reference Manual Figure 14-67 Upcounting mode and PWM mode A ................... 222 Figure 14-68 One-pulse mode ........................223 Figure 14-69 Complementary output with dead-time insertion ..............224 Figure 14-70 TMR control output ....................... 225 Figure 14-71 Example of TMR brake function ................... 225 Figure 14-72 Example of reset mode ......................
  • Page 22 AT32F421 Series Reference Manual Figure 14-112 Output stage for channel 4 ....................267 Figure 14-113 C1ORAW toggles when counter value matches the C1DT value ........268 Figure 14-114 Upcounting mode and PWM mode A ................. 268 Figure 14-115 Up/down counting mode and PWM mode A ..............268 Figure 14-116 One-pulse mode .........................
  • Page 23 AT32F421 Series Reference Manual List of tables Table 1-1 Bit-band address mapping in SRAM ................... 28 Table 1-2 Bit-band address mapping in the peripheral area ............... 29 Table 1-3 AT32F421 series vector table ...................... 29 Table 1-4 List of abbreviations for registers ....................33 Table 1-5 List of abbreviations for registers ....................
  • Page 24 AT32F421 Series Reference Manual Table 14-8 Standard CxOUT channel output control bit ................212 Table 14-9 TMR15 internal trigger connection ..................216 Table 14-10 TMR15 register map and reset value ..................227 Table 14-11 Complementary output channel CxOUT and CxCOUT control bits with brake function ..235 Table 14-12 TMR16 and TMR17 register map and reset value ..............

  • Page 25: System Architecture

    AT32F421 Series Reference Manual 1 System architecture ® ® AT32F421 series microcontrollers incorporates a 32-bit ARM Cortex -M4 processor core, multiple 16- bit and 32-bit timers, DMA controller, ERTC, communication interfaces such as SPI, I2C, USART, CMP, 12-bit ADC, programmable voltage monitor (PVM) and other peripherals. Cortex ®...

  • Page 26: Figure 1-1 At32F421 Series Microcontrollers System Architecture

    AT32F421 Series Reference Manual Figure 1-1 AT32F421 Series microcontrollers system architecture HEXT 4~25MHz HICK 48/8MHz Cortex-M4 Max. 120MHz (Freq. Max. 120MHz) FCLK HCLK PCLK1 NVIC PCLK2 Flash 64KB @VDD 5Channel Controller Flash POR/LVR GPIOA/B SRAM 16KB /C/F Controller SRAM LDO 1.2V APB1 APB2 Bridge...

  • Page 27: System Overview

    AT32F421 Series Reference Manual 1.1 System overview 1.1.1 ARM Cortex -M4 processor Cortex ® -M4 processor is a low-power consumption processor featuring low gate count, low interrupt latency, and low-cost debug. It supports DSP instruction set, particularly applicable to deep-embedded applications that require quicker response to interrupts.

  • Page 28: Figure 1-4 Comparison Between Bit-Band Region And Its Alias Region: Image B

    AT32F421 Series Reference Manual Figure 1-4 Comparison between bit-band region and its alias region: image B bitband alias region (total 32M bytes) 0x23FF_FFFC 0x23FF_FFF8 0x23FF_FFF4 0x23FF_FFF0 0x23FF_FFEC 0x23FF_FFE8 0x23FF_FFE4 0x23FF_FFE0 0x2200_001C 0x2200_0018 0x2200_0014 0x2200_0010 0x2200_000C 0x2200_0008 0x2200_0004 0x2200_0000 bitband region (total 1M bytes) 0x200F_FFFD 0x200F_FFFF...

  • Page 29: Interrupt And Exception Vectors

    AT32F421 Series Reference Manual 0x2000_0004.2 0x2200_0088.0 … … 0x200F_FFFC.31 0x23FF_FFFC.0 Table 1-2 shows the mapping between bit-band region and alias region in the peripheral area: Table 1-2 Bit-band address mapping in the peripheral area Bit-band region Equivalent alias address 0x4000_0000.0 0x4200_0000.0 0x4000_0000.1 0x4200_0004.0...
  • Page 30 AT32F421 Series Reference Manual Configurable UsageFault Undefined instruction or illegal state 0x0000_0018 0x0000_001C Reserved ~0x0000_002B Configurable SVCall Call system service via SWI instruction 0x0000_002C Configurable DebugLENonitor Debug monitor 0x0000_0030 Reserved 0x0000_0034 Configurable PendSV Pendable request for system service 0x0000_0038 Configurable SysTick System tick timer 0x0000_003C...

  • Page 31: System Tick (Systick)

    AT32F421 Series Reference Manual Configurable SPI2 SPI2 global interrupt 0x0000_00A8 Configurable USART1 USART1 global interrupt 0x0000_00AC Configurable USART2 USART2 global interrupt 0x0000_00B0 Configurable Reserved 0x0000_00B4 Configurable Reserved 0x0000_00B8 Configurable Reserved 0x0000_00BC Configurable I2C1_ERR C1 error interrupt 0x0000_00C0 Configurable Reserved 0x0000_00C4 Configurable I2C2_ERR C2 error interrupt...

  • Page 32: Figure 1-6 Example Of Msp And Pc Initialization

    AT32F421 Series Reference Manual Figure 1-6 Example of MSP and PC initialization Other Memory Initial SP Value 0x2000_8000 0x2000_8000 1st push data 0x2000_7FFC Stack grows 0x2000_7FF8 2nd push data downward Stack Memory 0x2000_7C00 Other Memory Code Boot Code 0x0000_0100 Other Exception Vectors 0x0000_0101 0x0000_0004...

  • Page 33: List Of Abbreviations For Registers

    AT32F421 Series Reference Manual 1.2 List of abbreviations for registers Table 1-4 List of abbreviations for registers Register type Description Software can read and write to this bit. Software can only read this bit. Software can only write to the bit. Reading it returns its reset value. Software can read this bit.

  • Page 34: Memory Resources

    AT32F421 Series Reference Manual Abbr. Reset value Type Description Bit 31: 0 UID[95: 64] 0xXXXX XXXX UID for bit 95 to bit 64 Note: UID[95:88] is series ID, which is 0x09 for AT32F421. 2 Memory resources 2.1 Internal memory address map Internal memory contains program memory (Flash), data memory (SRAM), peripheral registers and core registers.

  • Page 35: Flash Memory

    AT32F421 Series Reference Manual 2.2 Flash memory AT32F421 series provide up to 64 KB of on-chip Flash memory, supporting a single-cycle 32-bit read operation. Refer to Chapter 5 for more details about Flash memory controller and register configuration. Flash memory organization (64 KB) The main memory contains only bank 1 (64 Kbytes), including 64 sectors, 1 Kbyte per sector.

  • Page 36: Peripheral Address Map

    AT32F421 Series Reference Manual 2.4 Peripheral address map Table 2-4 Peripheral boundary address Boundary address Peripherals 0x6000 0000 - 0xFFFF FFFF Reserved 0x5004 0000 - 0x5FFF FFFF Reserved 0x5000 0000 - 0x5003 FFFF Reserved 0x4800 1800 – 0x4FFF FFFF Reserved 0x4800 1400 - 0x4800 17FF GPIOF 0x4800 0C00 - 0x4800 13FF...
  • Page 37 AT32F421 Series Reference Manual Boundary address Peripherals 0x4001 3C00 - 0x4001 4BFF Reserved 0x4001 3800 - 0x4001 3BFF USART1 0x4001 3400 - 0x4001 37FF Reserved 0x4001 3000 - 0x4001 33FF SPI1/I 0x4001 2C00 - 0x4001 2FFF TMR1 timer 0x4001 2800 - 0x4001 2BFF Reserved 0x4001 2400 - 0x4001 27FF 0x4001 2000 - 0x4001 23FF...
  • Page 38 AT32F421 Series Reference Manual Boundary address Peripherals 0x4000 1C00 - 0x4000 1FFF Reserved 0x4000 1800 - 0x4000 1BFF Reserved 0x4000 1400 - 0x4000 17FF Reserved 0x4000 1000 - 0x4000 13FF TMR6 timer 0x4000 0C00 - 0x4000 0FFF Reserved 0x4000 0800 - 0x4000 0BFF Reserved 0x4000 0400 - 0x4000 07FF TMR3 timer...

  • Page 39: Power Control (Pwc)

    AT32F421 Series Reference Manual 3 Power control (PWC) 3.1 Introduction For the AT32F421 series, its operating voltage supply is 2.6 V ~ 3.6 V, with a temperature range of - 40~+105 C. To reduce power consumption, this series provides three types of power saving modes, including Sleep, Deepsleep and Standby modes so as to achieve the best trade-off among the conflicting demands of CPU operating time, speed and power consumption.

  • Page 40: Por/Lvr

    AT32F421 Series Reference Manual 3.3 POR/LVR A POR analog module embedded in the VDD/VDDA domain is used to generate a power reset. The power reset signal is released at V when the VDD is increased from 0 V to the operating voltage, or it is triggered at V when the VDD drops from the operating voltage to 0 V.

  • Page 41: Power Domain

    AT32F421 Series Reference Manual Figure 3-3 PVM threshold and output DET_P HYS_P 100 mV hysteresis DET_P PVMOF 3.5 Power domain 1.2 V domain 1.2 V core domain includes a CPU core, SRAM, embedded digital peripherals and Phase Locked Loop (PLL). Such power domain is supplied by LDO (voltage regulator). VDD/VDDA domain VDD/VDDA domain includes VDD domain and VDDA domain.
  • Page 42 AT32F421 Series Reference Manual 2) If the WFE is executed to enter Sleep mode, the MCU exits Sleep mode as soon as an event occurs. The wakeup event can be generated by the following:  Enabling a peripheral interrupt (it is not enabled in the NVIC) and enabling the SEVONPEND bit. When the MCU resumes, the peripheral interrupt pending bit and NVIC channel pending bit must be cleared.

  • Page 43: Pwc Registers

    AT32F421 Series Reference Manual 3.7 PWC registers The peripheral registers must be accessed by words (32 bit) Table 3-1 PW register map and reset values Register abbr. Offset Reset value PWC_CTRL 0x00 0x0000 0000 PWC_CTRLSTS 0x04 0x0000 0000 PWC_CTRL2 0x20 0x0000 00XX 3.7.1 Power control register (PWC_CTRL)

  • Page 44: Power Control/Status Register (Pwc_Ctrlsts)

    AT32F421 Series Reference Manual 3.7.2 Power control/status register (PWC_CTRLSTS) Unlike a standard APB read, an additional APB cycles are needed to read this register. Name Reset value Type Description Bit 31: 15 Reserved 0x000000 resd Kept at its default value. Standby wake-up pin 7 enable 0: Disabled (this pin is used for general-purpose I/O) 1: Enabled (this pin is forced in input pull-down mode, and...

  • Page 45: Clock And Reset Manage (Crm)

    AT32F421 Series Reference Manual 4 Clock and reset manage (CRM) 4.1 Clock AT32F421 series provide different clock sources: HEXT oscillator clock, HICK oscillator clock, PLL clock, LEXT oscillator and LICK oscillator. Figure 4-1 AT32F421 clock tree HEXT_IN Peripheral HEXT 12S1/2 CLK clock enable CPU SysTick HEXT OSC...

  • Page 46: System Clock

    AT32F421 Series Reference Manual 500 MHz and 1000 MHz. Before enabling PLL, it is mandatory to configure PLL parameters for the reason that the configuration parameters cannot be altered once PLL is enabled. The PLL clock signal is not released before it becomes stable. PLL formula as follows: PLL output clock = PLL input clock x PLL frequency multiplication factor / (PLL prescaler factor x PLL post-scalar factor)

  • Page 47: Clock Fail Detector

    AT32F421 Series Reference Manual 4.1.4 Clock fail detector The clock fail detector (CFD) is designed to respond to HEXT clock failure when the HEXT is used as a system clock, directly or indirectly. If a failure is detected on the HEXT clock, a clock failure event is sent to the brake input of TMR1 and an interrupt is generated.

  • Page 48: Battery Powered Domain Reset

    AT32F421 Series Reference Manual Figure 4-2 System reset circuit 4.2.2 Battery powered domain reset Battery powered domain has two specific reset sources:  Software reset: triggered by setting the BPDRST bit in the battery powered domain control register (CRM_BPDC)  VDD power on, if VDD has been powered off.

  • Page 49: Clock Control Register (Crm_Ctrl)

    AT32F421 Series Reference Manual 4.3.1 Clock control register (CRM_CTRL) No-wait states, accessible by bytes, half-words or words. Name Reset value Type Description Bit 31: 26 Reserved 0x00 resd Kept at its default value. PLL clock stable This bit is set by hardware after PLL is ready. Bit 25 PLLSTBL 0: PLL clock is not ready.

  • Page 50: Clock Configuration Register (Crm_Cfg)

    AT32F421 Series Reference Manual 4.3.2 Clock configuration register (CRM_CFG) Name Reset value Type Description Bit 31 Reserved resd Kept at its default value. Clock output selection CLKOUT_SEL[3] is the bit 16 of the CRM_MISC1 register. 0000: None 0001: Reserved 0010: LICK 0011: LEXT Bit 26:24 CLKOUT_SEL...

  • Page 51: Clock Interrupt Register (Crm_Clk Int)

    AT32F421 Series Reference Manual ensure that the APB1 clock frequency does not exceed 120 MHz AHB division The divided SCLK is used as AHB clock. 0xxx: SCLK not divided Bit 7: 4 AHBDIV 1000: SCLK divided by 2 1100: SCLK divided by 64 1001: SCLK divided by 4 1101: SCLK divided by 128 1010: SCLK divided by 8...

  • Page 52: Apb2 Peripheral Reset Register (Crm_Apb2Rst)

    AT32F421 Series Reference Manual 1: Enabled Clock Failure Detection flag This bit is set by hardware when the HEXT Bit 7 CFDF clock failure occurs. 0: No clock failure 1: Clock failure Bit 6: 5 Reserved resd Keep at its default value. PLL stable flag Set by hardware.

  • Page 53: Apb1 Peripheral Reset Register1 (Crm_Apb1Rst)

    AT32F421 Series Reference Manual 1: Reset SCFG and CMP 4.3.5 APB1 peripheral reset register1 (CRM_APB1RST) Access: 0 wait state, accessible by words, half-words and bytes. Name Reset value Type Description Bit 31: 29 Reserved resd Kept at its default value. PWC reset Bit 28 PWCRST...

  • Page 54: Apb2 Peripheral Clock Enable Register (Crm_Apb2En)

    AT32F421 Series Reference Manual 0: Disabled 1: Enabled Bit 5 Reserved resd Kept at its default value. FLASH clock enable This bit is used to enable Flash clock in Sleep or Bit 4 FLASHEN Deepsleep mode. 0: Disabled 1: Enabled Bit 3 Reserved resd...

  • Page 55: Apb1 Peripheral Clock Enable Register (Crm_Apb1En)

    AT32F421 Series Reference Manual 4.3.8 APB1 peripheral clock enable register (CRM_APB1EN) Access: by words, half-words and bytes. No-wait states in most cases. However, when accessing to peripherals on APB1, wait-states are inserted until the end of peripheral access on the APB1 bus. Name Reset value Type...

  • Page 56: Battery Powered Domain Control Register (Crm_Bpdc)

    AT32F421 Series Reference Manual 4.3.9 Battery powered domain control register (CRM_BPDC) Access: 0 to 3 wait states, accessible by words, half-words or bytes. Wait states are inserted in the case of consecutive accesses to this register. Note: LEXTEN, LEXTBYPS, ERTCSEL, and ERTCEN bits of the battery powered domain control register (CRM_BPDC) are in the battery powered domain.

  • Page 57: Ahb Peripheral Reset Register (Crm_Ahbrst)

    AT32F421 Series Reference Manual POR/LVR reset flag Set by hardware. Cleared by writing to the RSTFC bit. Bit 27 PORRSTF 0: No POR/LVR reset occurs 1: POR/LVR reset occurs. NRST pin reset flag Set by hardware. Cleared by writing to the RSTFC bit. Bit 26 NRSTF 0: No NRST pin reset occurs...

  • Page 58: Additional Register (Crm_Misc1)

    AT32F421 Series Reference Manual PLL multiplication factor Bit 16: 8 PLL_NS 0x01F PLL_NS range (31~500) PLL pre-division Bit 7: 4 PLL_MS PLL_MS range (1~15) Bit 3 Reserved resd Kept at its default value. PLL post-division factor PLL_FR range (0~5) 000: PLL post-division=1, divided by 1 001: PLL post-division=2, divided by 2 010: PLL post-division=4, divided by 4 Bit 2: 0...

  • Page 59: Additional Register (Crm_Misc2)

    AT32F421 Series Reference Manual 4.3.14 Additional register (CRM_MISC2) Name Reset value Type Description Bit 31: 10 Reserved 0x000000 resd Kept at its default value. HICK as system clock frequency select When the HICK is selected as the clock source SCLKSEL, Bit 9 HICK_TO_SCLK the frequency of SCLK is:...

  • Page 60: Embedded Flash Memory Controller (Flash)

    AT32F421 Series Reference Manual 5 Embedded Flash memory controller (FLASH) 5.1 FLASH introduction Flash memory is divided into three parts: main Flash memory, information block and Flash memory registers.  Main Flash memory is up to 64 KB Information block consists of 4 KB boot memory and the user system data area. The boot ...

  • Page 61: Table 5-4 User System Data Area

    AT32F421 Series Reference Manual User system data area The system data will be read from the information block of Flash memory whenever a system reset occurs, and saved in the user system data register (FLASH_USD) and erase/programming protection status register (FLASH_EPPS). Each system data occupies two bytes in which the low bytes represent the system data, and the high bytes represent the inverse code of system data.

  • Page 62: Flash Memory Operation

    AT32F421 Series Reference Manual EPP3[7:0]: Flash erase/write protection byte 3 (stored in the bit [31: 24] of the FLASH_EPPS register) Bit 6:0 are reserved. [23: 16] Bit 7 is used to protect Flash memory extension area 0: Erase/write protection is enabled 1: Erase/write protection is disabled [31: 24] nEPP3[7: 0]: Inverse code of EPP3[7: 0]...

  • Page 63: Figure 5-1 Flash Memory Sector Erase Process

    AT32F421 Series Reference Manual Figure 5-1 Flash memory sector erase process Start Check the OBF bit in FLASH_STS OBF = 0 ? Write the erased sector address to FLASH_ADDR Set SECERS = 1 and ERSTR =1 in FLASH_CTRL Check the OBF bit in FLASH_STS OBF = 0 ? Read EPPERR bit and ODF bit in FLASH_STS...

  • Page 64: Programming Operation

    AT32F421 Series Reference Manual Figure 5-2 Flash memory mass erase process Start Check the OBF bit in FLASH_STS OBF = 0? Set BANKERS = 1 and ERSTR =1 in FLASH_CTRL Check the OBF bit in FLASH_STS OBF = 0 ? Read EPPERR bit and ODF bit in FLASH_STS 5.2.3...

  • Page 65: Read Operation

    AT32F421 Series Reference Manual Figure 5-3 Flash memory programming process Start Check the OBF bit in FLASH_STS OBF = 0? Set the FPRGM bit = 1 in FLASH_CTRL Write word/half-word/byte (32bits/16 bits/8bits) data Check the OBF bit in FLASH_STS OBF = 0? Read EPPERR bit、PRGMERR bit and ODF bit in FLASH_STS 5.2.4...

  • Page 66: User System Data Area

    AT32F421 Series Reference Manual 5.4 User system data area 5.4.1 Unlock/lock After reset, user system data area is protected, by default. Write and erase operations can be performed only after the Flash memory is unlocked and then the user system data area is unlocked. Unlock procedure: Flash memory block can be unlocked by writing KEY1 (0x45670123) and KEY2 (0xCDEF89AB) to the FLASH_UNLOCK register;...

  • Page 67: Figure 5-4 System Data Area Erase Process

    AT32F421 Series Reference Manual Figure 5-4 System data area erase process Start Check the OBF bit in FLASH_STS OBF = 0? Set USDERS = 1 and ERSTR =1 in FLASH_CTRL Check the OBF bit in FLASH_STS OBF = 0 ? Read ODF bit in FLASH_STS 2022.11.11 Page 67...

  • Page 68: Programming Operation

    AT32F421 Series Reference Manual 5.4.3 Programming operation The User system data area can be programmed with 16-bit or 32-bit data at one time. The following process is recommended:  Check that no Flash memory operation is ongoing by checking the OBF bit in the FLASH_STS register ...

  • Page 69: Read Operation

    AT32F421 Series Reference Manual 5.4.4 Read operation User system data area can be accessed through AHB bus of the CPU. 5.5 Flash memory protection Flash memory includes access and erase/program protection. 5.5.1 Access protection Flash memory access protection is divided into two parts: high-level and low-level. Once enabled, only the Flash program is allowed to read Flash memory data.

  • Page 70: Erase/Program Protection

    AT32F421 Series Reference Manual 5.5.2 Erase/program protection For 64 K Flash memory and less, erase/program protection is performed on the basis of 4 sectors. This is used to protect the contents in the Flash memory against inadvertent operation when the program crash occurs.

  • Page 71: Boot Memory Used As Memory Extension Area

    AT32F421 Series Reference Manual this register, security library should be unlocked first by writing 0xA35F6D24 to the SLIB_UNLOCK register. Then check the SLIB_ULKF bit in the SLIB_MISC_STS register to verify if it is unlocked successfully. If successful, write the programmed value into the security library setting register. To enable security library , follow the steps below: ...

  • Page 72: Crc Verify

    AT32F421 Series Reference Manual 5.7.3 CRC verify The sLib code or user code go through optional CRC check on the basis of a sector level. CRC verify procedure as follows: Check that no Flash memory operation is ongoing by checking the OBF bit in the FLASH_STS ...

  • Page 73: Flash Performance Select Register (Flash_Psr)

    AT32F421 Series Reference Manual 5.8.1 Flash performance select register (FLASH_PSR) Abbr. Reset value Type Description Bit 31: 9 Reserved 0x000000 resd Kept at its default value. Prefetch latency disable 0: Prefetch latency of Flash is enabled, meaning that accessing buffer requires one system clock cycle Bit 8 PFT_LAT_DIS 1: Prefetch latency of Flash is disabled, meaning that...

  • Page 74: Flash Status Register (Flash_Sts)

    AT32F421 Series Reference Manual 5.8.4 Flash status register (FLASH_STS) Abbr. Reset value Type Description Bit 31: 6 Reserved 0x0000000 resd Kept at its default value Operation done flag This bit is set by hardware when Flash memory Bit 5 rw1c operations (program/erase) are complete.

  • Page 75: Flash Control Register (Flash_Ctrl)

    AT32F421 Series Reference Manual 5.8.5 Flash control register (FLASH_CTRL) Register Reset value Type Description Bit 31: 8 Reserved 0x0000 resd Kept at its default value Low power mode enable 0: Low power mode disabled 1: Low power mode enabled Bit 17 LPMEN When this bit is set, the Flash controller lets Flash memory go to low-power mode as soon as MCU enters...

  • Page 76: Flash Address Register (Flash_Addr)

    AT32F421 Series Reference Manual 5.8.6 Flash address register (FLASH_ADDR) Register Reset value Type Description Flash address Bit 31: 0 0x0000 0000 This is used to select the address of the sectors to be erased. 5.8.7 User system data register (FLASH_USD) Register Reset value Type...

  • Page 77: Flash Security Library Status Register 0 (Slib_Sts0)

    AT32F421 Series Reference Manual 5.8.9 Flash security library status register 0 (SLIB_STS0) For Flash memory security library only. Register Reset value Type Description Bit 31: 24 Reserved 0x00 resd Kept at its default value Extension memory sLib instruction start sector 00000000: sector 0 00000001: sector 1 Bit 23: 16...

  • Page 78: Security Library Password Clear Register (Slib_Pwd_Clr)

    AT32F421 Series Reference Manual 00000000001: sector 1 00000000010: sector 2 … 00000001111: sector 15 (the last sector of 16KB main Flash memory) … 00000011111: sector 31 (the last sector of 32KB main Flash memory) … 00000111111: sector 63 (the last sector of 64KB main Flash memory) 5.8.11 Security library password clear register (SLIB_PWD_CLR)

  • Page 79: Flash Crc Control Register (Flash_Crc_Ctrl)

    AT32F421 Series Reference Manual 5.8.14 Flash CRC control register (FLASH_CRC_CTRL) For main Flash memory and its extension area only. Register Reset value Type Description Kept at its default value. Bit 31:17 Reserved 0x0000 resd CRC start This bit is used to enable CRC check for user code or sLib code.
  • Page 80 AT32F421 Series Reference Manual … 00000001111: Sector 15 (the last sector of 16KB main Flash memory) … 00000011111: Sector 31 (the last sector of 32KB main Flash memory) … 00000111111: Sector 63 (the last sector of 64KB main Flash memory) 11111111111: No sLib instruction area Security library start sector setting These bits are used to set the security library start sector.

  • Page 81: Boot Memory Mode Setting Register (Btm_Mode_Set)

    AT32F421 Series Reference Manual 5.8.18 Flash extension memory security library setting register (EM_SLIB_SET) For Flash extension area only. Register Reset value Type Description Kept at its default value Bit 31: 24 Reserved 0x00 resd Extension memory sLib instruction start sector 00000000: Sector 0 00000001: Sector 1 00000010: Sector 2...

  • Page 82: General-Purpose I/Os (Gpios)

    AT32F421 Series Reference Manual 6 General-purpose I/Os (GPIOs) 6.1 Introduction AT32F421 series supports up to 39 bidirectional I/O pins, namely PA0-PA15, PB0-PB15, PC13-PC15, PF0-PF1 and PF6-PF7. Each of the GPIO group supports external communication, with control and data collection feature. In addition, their main features also include: ...

  • Page 83: General-Purpose Input Configuration

    AT32F421 Series Reference Manual 6.2.3 General-purpose input configuration Mode IOMC PUPD Floating input Pull-down input Pull-up input When I/O port is configured as input:  Get I/O states by reading the input data register.  Support floating input, pull-up/pull-down input configuration. ...

  • Page 84: Iomux Structure

    AT32F421 Series Reference Manual 6.2.7 IOMUX structure Most of the pins supports output function mapping for multiple peripherals. It is possible to select the peripheral input/output functions for each pin by using the IOMUX input/output checklist described in the section of IOMUX input/output. The multiplexed function of pins is configured using the corresponding GPIO multiplexed register low (GPIOx_MUXL) (for pin 0 ~ pin 7) or the GPIO multiplexed register high (GPIOx_MUXH) (for pin 8 ~ pin 15).

  • Page 85: Iomux Function Input/Output

    AT32F421 Series Reference Manual 6.2.9 IOMUX function input/output The selection of the valid multiplexed functions for each port is done by the GPIOx_MUXL (for pin 0 to pin 7) or GPIOx_MUXH (for pin 8 to pin 15) registers. Table 6-1 Multiplexed function configuration for port A using GPIO_A MUX register MUX0 MUX1...

  • Page 86: Table 6-2 Multiplexed Function Configuration For Port B Using Gpio_B Mux* Register

    AT32F421 Series Reference Manual Table 6-2 Multiplexed function configuration for port B using GPIO_B MUX register MUX0 MUX1 MUX2 MUX3 MUX4 MUX5 MUX6 MUX7 name TMR3_C TMR1_CH USART2 EVENTOUT I2S1_MCLK TMR3_C TMR1_CH SPI2_SCK/I TMR14_CH1 2S2_CK TMR3_ET SPI1_SCK/I2 EVENTO SPI2_SCK/I S1_CK 2S2_CK SPI1_MISO/I TMR3_C...

  • Page 87: Peripheral Multiplexed Function Configuration

    AT32F421 Series Reference Manual 6.2.10 Peripheral multiplexed function configuration When IOMUX multiplexed function is needed:  To use a peripheral pin as a multiplexed output, the corresponding pin should be configured as multiplexed push-pull/open-drain output. To use a peripheral pin as a MUX input, the corresponding pin configured as floating input/pull- ...

  • Page 88: Gpio Configuration Register (Gpiox_Cfgr) (X=A

    AT32F421 Series Reference Manual GPIOA_PULL 0x0C 0x2400 0000 GPIOx_PULL(x = B,C,F) 0x0C 0x0000 0000 GPIOx_IDT 0x10 0x0000 XXXX GPIOx_ODT 0x14 0x0000 0000 GPIOx_SCR 0x18 0x0000 0000 GPIOx_WPR 0x1C 0x0000 0000 GPIOx_MUXL 0x20 0x0000 0000 GPIOx_MUXH 0x24 0x0000 0000 GPIOx_CLR 0x28 0x0000 0000 GPIOx_HDRV 0x3C...

  • Page 89: Gpio Input Data Register (Gpiox_Idt) (X=A

    AT32F421 Series Reference Manual 6.3.5 GPIO input data register (GPIOx_IDT) (x=A…H) Register Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Always 0. GPIOx input data Bit 15: 0 0xXXXX Indicates the input status of I/O port. Each bit corresponds to an I/O.

  • Page 90: Gpio Multiplexed Function Low Register (Gpiox_Muxl) (X=A

    AT32F421 Series Reference Manual 6.3.9 GPIO multiplexed function low register (GPIOx_MUXL) (x=A..H) Address offset: 0x20 Reset value: 0x00000000 Register Reset value Type Description Multiplexed function select for GPIOx pin y (y=0…7) This field is used to configure multiplexed function IOs. 0000: MUX0 0001: MUX1 0010: MUX2...

  • Page 91: System Configuration Controller (Scfg)

    AT32F421 Series Reference Manual 7 System configuration controller (SCFG) 7.1 Introduction This device contains a set of system configuration register. The system configuration controller is mainly used to:  Remap some DMA trigger sources to other DMA channels Manage the external interrupts connected to the GPIOs ...

  • Page 92: Scfg External Interrupt Configuration Register1 (Scfg_ Exintc1)

    AT32F421 Series Reference Manual channel 1) 1: Remap (ADC DMA request is mapped on DMA channel 2. Infrared modulation envelope signal source selection This field is used to select the infrared modulation envelope signal source. Bit 7: 6 IR_SRC_SEL 00: TMR16 01: USART1 10: USART2 11: Reserved...

  • Page 93: Scfg External Interrupt Configuration Register2 (Scfg_ Exintc2)

    AT32F421 Series Reference Manual 7.2.3 SCFG external interrupt configuration register2 (SCFG_ EXINTC2) Register Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Kept at its default value. EXINT7 input source configuration These bits can be read/written by software. They are used to select the input source for the EXINT7 external interrupt.

  • Page 94: Scfg External Interrupt Configuration Register4 (Scfg_ Exintc4)

    AT32F421 Series Reference Manual interrupt. 0000: PA[9] 0001: PB[9] EXINT8 input source configuration These bits can be read/written by software. They are used to select the input source for the EXINT8 external Bit 3: 0 EXINT8 0x0000 interrupt. 0000: PA[8] 0001: PB[8] 7.2.5 SCFG external interrupt configuration register4 (SCFG_...

  • Page 95: External Interrupt/Event Controller (Exint)

    AT32F421 Series Reference Manual 8 External interrupt/Event controller (EXINT) 8.1 EXINT introduction EXINT consists of 22 interrupt lines EXINT_LINE[21:0] (Line 18 and Line 20 are reserved), each of which can generate an interrupt or event by edge detection trigger or software trigger. EXINT can enable or disable an interrupt or event independently through software configuration, and adopt different edge detection modes (rising edge, falling edge or both edges) as well different trigger modes (edge detection, software trigger or both triggers) to respond to the trigger source and generate an...

  • Page 96: Exint Registers

    AT32F421 Series Reference Manual Interrupt initialization procedure Select an interrupt source by setting IOMUX_EXINTCx register (This is required if GPIO is used  as an interrupt source) Select a trigger mode by setting EXINT_POLCFG1 and EXINT_POLCFG2 registers   Enable interrupt or event by setting EXINT_INTEN and EXINT_EVTEN registers Generate software trigger by setting EXINT_SWTRG register (This is applied to only software ...

  • Page 97: Polarity Configuration Register2 (Exint_ Polcfg2)

    AT32F421 Series Reference Manual 8.3.4 Polarity configuration register2 (EXINT_ POLCFG2) Register Reset value Type Description Bit 31: 22 Reserved 0x000 resd Forced to be 0 by hardware. Falling polarity configuration bit on line x These bits are used to select a falling edge to trigger an interrupt and event on line x.

  • Page 98: Dma Controller (Dma)

    AT32F421 Series Reference Manual 9 DMA controller (DMA) 9.1 Introduction Direct memory access (DMA) controller is designed for 32-bit MCU applications with the aim of enhancing system performance and reducing the generation of interrupts. The DMA controller contains 5 DMA channels. Each channel manages memory access requests from one or more peripherals.

  • Page 99: Handshake Mechanism

    AT32F421 Series Reference Manual If the two channels have the same priority level, then the channel with lower number will get priority over the one with higher number. For example, channel 1 has priority over channel 2.  Data transfer direction (DTD) Memory-to-peripheral (M2P), peripheral-to-memory (P2M) ...

  • Page 100: Programmable Data Transfer Width

    AT32F421 Series Reference Manual 9.3.4 Programmable data transfer width Transfer width of the source data and destination data is programmable through the PWIDTH and MWIDTH bits in the DMA_CxCTRL register. When PWIDTH is not equal to MWIDTH, number of data to be transferred can be aligned according to the settings of PWIDTH/MWIDTH.

  • Page 101: Errors

    AT32F421 Series Reference Manual 9.3.5 Errors Table 9-1 DMA error event Error event Transfer error AHB response error occurred during DMA read/write access 9.3.6 Interrupts An interrupt can be generated on DMA half-transfer, transfer complete and transfer error. Each channel has its specific interrupt flag, clear and enable bits, as shown in the table below.

  • Page 102: Dma Registers

    AT32F421 Series Reference Manual 9.4 DMA registers Table 9-4 shows DMA register map and their reset values. These peripheral registers must be accessed by bytes (8 bits), half-words (16 bits) or words (32 bits). Table 9-4 DMA register map and reset value Register Offset Reset value...

  • Page 103: Dma Interrupt Status Register (Dma_Sts)

    AT32F421 Series Reference Manual 9.4.1 DMA interrupt status register (DMA_STS) Access: 0 wait state, accessible by bytes, half-words or words. Register Reset value Type Description Bit 31: 20 Reserved resd Kept at its default value. Channel 5 data transfer error event flag Bit 19 DTERRF5 0: No transfer error occurred.

  • Page 104: Dma Interrupt Flag Clear Register (Dma_Clr)

    AT32F421 Series Reference Manual Channel 1 data transfer error event flag Bit 3 DTERRF1 0: No transfer error occurred. 1: Transfer error occurred. Channel 1 half transfer event flag Bit 2 HDTF1 0: No half-transfer event occurred. 1: Half-transfer event occurred. Channel 1 transfer complete event flag Bit 1 FDTF1...

  • Page 105: Dma Channel-X Configuration Register (Dma_Cxctrl)

    AT32F421 Series Reference Manual Channel 3 global interrupt flag clear 0: No effect Bit 8 GFC3 rw1c 1: Clear the DTERRF3, HDTF3, FDTF3 and GF3 flag in the DMA_STS register Channel 2 data transfer error flag clear Bit 7 DTERRFC2 rw1c 0: No effect 1: Clear the DTERRF2 flag in the DMA_STS register...

  • Page 106: Dma Channel-X Number Of Data Register (Dma_Cxdtcnt) (X = 1

    AT32F421 Series Reference Manual 1: Enabled. Circular mode Bit 5 0: Disabled 1: Enabled. Data transfer direction Bit 4 0: Read from peripherals 1: Read from memory Data transfer error interrupt enable Bit 3 DTERRIEN 0: Disabled 1: Enabled. Half-transfer interrupt enable Bit 2 HDTIEN 0: Disabled...

  • Page 107: Crc Calculation Unit (Crc)

    AT32F421 Series Reference Manual 10 CRC calculation unit (CRC) 10.1 CRC introduction The Cyclic Redundancy Check (CRC) is an independent peripheral with CRC check feature. It follows CRC32 standard. The CRC_CTRL register is used to select input data toggle (word, REVOD=1) or output data toggle (byte, REVID=01;...

  • Page 108: Control Register (Crc_Ctrl)

    AT32F421 Series Reference Manual 10.2.3 Control register (CRC_CTRL) Register Reset value Type Description Bit 31: 8 Reserved 0x000000 resd Kept at its default value. Reverse output data Set and cleared by software. This bit is used to control Bit 7 REVOD resd whether or not to reverse output data.

  • Page 109: C Interface

    AT32F421 Series Reference Manual 11 I C interface 11.1 I C introduction C (inter-integrated circuit) bus interface manages the communication between the microcontroller and serial I C bus. It supports master and slave modes, with up to 400 Kbit/s of communication speed. 11.2 I C main features ...

  • Page 110: I 2 C Interface

    AT32F421 Series Reference Manual 11.4 I C interface Figure 11-2 shows the block diagram of I C function Figure 11-2 I C function block diagram Comparator Data Control Shift Register APB Interface Control register Data Clock OADDR Register Control Status I2C_DMA_req_tx register Clock...

  • Page 111: C Slave Communication Flow

    AT32F421 Series Reference Manual  In 10-bit mode ― Only matches OADDR1 Support special slave address:  Broadcast call address (0b0000000x): This address is enabled when GCAEN=1.  SMBus device default address (0b1100001x): This address is enabled for SMBus address resolution protocol in SMBus device mode.

  • Page 112: Figure 11-3 Transfer Sequence Of Slave Transmitter

    AT32F421 Series Reference Manual Figure 11-3 Transfer sequence of slave transmitter Example : I2C Slave transfer N bytes to I2C Master . EV2 EV3 7-bit address Address Data1 Data2 DataN NA P Stretch TDBE 10-bit address Address Head Address Address Head Stretch EV2 EV3 Stretch...

  • Page 113: Figure 11-4 Transfer Sequence Of Slave Receiver

    AT32F421 Series Reference Manual Slave receiver Figure 11-4 shows the transfer sequence of slave receiver. Figure 11-4 Transfer sequence of slave receiver Example : I2C Slave receive N bytes from I2C Master . 7-bit address Address Data1 Data2 DataN Stretch RDBF 10-bit address Address Head...

  • Page 114: C Master Communication Flow

    AT32F421 Series Reference Manual 11.4.2 I C master communication flow Master mode Initialization Program input clocks to generate correct timings through the CLKFREQ bit in the I2C_CTRL2 register; Program I C communication speed through the I2C_CLKCTRL bit in the clock control register; Program the maximum rising time of bus through the I2C_TMRISE register;...
  • Page 115 AT32F421 Series Reference Manual register. EV2: Address is matched successfully (ADDR7F=1). Reading STS1 and then STS2 clears the ADDR7F bit. At this point, the master enters transmit stage, and both DT register and internal shift register are empty. The TDBE bit is set 1 by hardware. EV3: When the data is written to the DT register, it is directly moved to the shift register and the SCL bus is released.

  • Page 116: Figure 11-6 Transfer Sequence Of Master Receiver

    AT32F421 Series Reference Manual Figure 11-6 Transfer sequence of master receiver Example : I2C Master receive N bytes from I2C Slave . 7-bit address Address Data1 Data2 DataN NA P Stretch Stretch RDBF 10-bit address Address Address Head Address Head Stretch Stretch Stretch...

  • Page 117: Figure 11-7 Transfer Sequence Of Master Receiver When N>2

    AT32F421 Series Reference Manual the GENSTOP bit in the I2C_CTRL1 register and read the second-to-last byte (N-1). The bus then starts to receive the last one byte. Figure 11-7 Transfer sequence of master receiver when N>2 Example : I2C Master receive N bytes from I2C Slave . 7-bit address Address Data1...

  • Page 118: Figure 11-8 Transfer Sequence Of Master Receiver When N=2

    AT32F421 Series Reference Manual 10. End of communication. When I C interrupt priority is not very high but the number of bytes to receive is equal to 2  Set the MACKCTRL bit in the I2C_CTRL1 register before data reception. When the address is matched, clear ACKEN bit and then the ADDR7F bit.

  • Page 119: Figure 11-9 Transfer Sequence Of Master Receiver When N=1

    AT32F421 Series Reference Manual End of communication. When I C interrupt priority is not very high but the number of bytes to receive is equal to 1  After the address is matched, clear the ACKEN bit and then ADDR7F bit, then set the GENSTOP bit in the I2C_CTRL1 register.

  • Page 120: Data Transfer Using Dma

    AT32F421 Series Reference Manual 11.4.3 Data transfer using DMA C data transfer can be done using DMA controller. An interrupt is generated by enabling the transfer complete interrupt bit. The DATAIEN bit in the I2C_CTRL2 register must be set 0 when using DMA for data transfer.

  • Page 121: Smbus

    AT32F421 Series Reference Manual 11.4.4 SMBus The System Management Bus (SMBus) is a two-wire interface through which various devices can communicate with each other. It is based on I C. With SMBus, the device can provide manufacturer information, tell the system its model/part number, report different types of errors and accept control parameters and so on.

  • Page 122: C Interrupt Requests

    AT32F421 Series Reference Manual When an alert event occurs and the ALERT pin changes from high to low (SMBALERT=1), the slave responses to ARA (Alert Response Address) address (0001100x) Enable ALERT interrupt if necessary (an interrupt is generated when receiving ARA address) Wait until the host gets the slave addresses through ARA Report its own address, but it continues to wait if the arbitration is lost.

  • Page 123: C Debug Mode

    AT32F421 Series Reference Manual 11.4.6 I C debug mode When the microcontroller enters debug mode (Cortex -M4 halted), the SMBUS timeout feature either continues to work or stops, depending on the I2Cx_SMBUS_TIMEOUT configuration bit in the DEBUG module. 11.5 I C registers These peripheral registers must be accessed by words (32 bits).

  • Page 124: Control Register2 (I2C_Ctrl2)

    AT32F421 Series Reference Manual Generate stop condition This bit is set or cleared by software. It is cleared when a Stop condition is detected. It is set by hardware when a timeout error is detected. Bit 9 GENSTOP 0: No Stop condition is generated. 1: Stop condition is generate.

  • Page 125: Own Address Register1 (I2C_Oaddr1)

    AT32F421 Series Reference Manual 1: Enabled Data transfer interrupt enable An interrupt is generated when TDBE =1 or RDBF=1. Bit 10 DATAIEN 0: Disabled 1: Enabled Event interrupt enable 0: Disabled 1: Enabled An interrupt is generated in the following conditions: –...

  • Page 126: Data Register (I2C_Dt)

    AT32F421 Series Reference Manual recognized. 11.5.5 Data register (I2C_DT) Register Reset value Type Description Kept at its default value Bit 15: 8 Reserved 0x00 resd This field is used to store data received or to be transferred. Transmitter mode: Data transfer starts automatically when a byte is written to the DT register.
  • Page 127 AT32F421 Series Reference Manual 1: Acknowledge failure occurs. Set by hardware when no acknowledge is returned. This bit is cleared by software, or by hardware when I2CEN=0. Arbitration lost flag 0: No arbitration lost is detected. 1: Arbitration lost is detected. Bit 9 ARLOST rw0c...

  • Page 128: Status Register2 (I2C_Sts2)

    AT32F421 Series Reference Manual received. When STRETCH=0 In reception mode, when a new byte (including ACK pulse) is received and the data register is not read yet (RDBF=1) In transmission mode, when a new byte is sent and the data register is not written yet (TDBE=1) The TDC is set under both conditions.

  • Page 129: Clock Control Register (I2C_ Clkctrl)

    AT32F421 Series Reference Manual cleared by hardware on detection of a Stop condition. Transmission mode 0: Slave mode 1: Master mode Bit 0 TRMODE Set by hardware when the GENSTART is set and a Start condition is sent. Cleared by hardware when a Stop condition is detected.

  • Page 130: Universal Synchronous/Asynchronous Receiver/Transmitter (Usart)

    AT32F421 Series Reference Manual 12 Universal synchronous/asynchronous receiver/transmitter (USART) 12.1 USART introduction The universal synchronous/asynchronous receiver/transmitter (USART) acts as a general-purpose interface for communication by means of various configurations and peripherals with different data formats. It supports asynchronous full-duplex and half-duplex as well as synchronous transfer. It offers a programmable baud rate generator, generating up to 7.5 Mbits/s of baud rate by setting the system frequency and frequency divider.
  • Page 131 AT32F421 Series Reference Manual ─ Half-duplex, single communication  Programmable communication modes ─ NRZ standard format (Mark/Space) ─ LIN (Local Interconnection Network): ─ IrDA SIR: ─Asynchronous SmartCard protocol defined in ISO7816-3 standard: Support 0.5 or 1.5 stop bits in Smartcard mode ─...

  • Page 132: Full-Duplex/Half-Duplex Selector

    AT32F421 Series Reference Manual 12.2 Full-duplex/half-duplex selector The full-duplex and half-duplex selector enables USART to perform data exchanges with peripherals in full-duplex or half-duplex mode, which is achieved by setting the corresponding registers. In two-wire unidirectional full-duplex mode (by default), TX pin is used for data output, while the RX pin is used for data input.

  • Page 133: Figure 12-2 Bff And Ferr Detection In Lin Mode

    AT32F421 Series Reference Manual Figure 12-2 BFF and FERR detection in LIN mode CASE1：BREAK frame occurring after idle frame Idle frame frame1 frame0 RX pin BREAK 1 frame time RDBF/ FERR CASE2：BREAK frame occurring while a frame is being received frame1 frame0 RX pin...

  • Page 134: Figure 12-4 Irda Data(3/16) - Normal Mode

    AT32F421 Series Reference Manual Figure 12-4 IrDA DATA(3/16) – normal mode 4. Hardware flow control mode: RTS and CTS flow control can be enabled by setting RTSEN=1 and CTSEN=1, respectively. This is to control serial data flow between two devices. RTS: the RTS becomes active (pull-down means low) as soon as the USART receiver is ready to receive a data.

  • Page 135: Figure 12-6 Mute Mode Using Idle Line Or Address Mark Detection

    AT32F421 Series Reference Manual Figure 12-6 Mute mode using Idle line or Address mark detection Idle line detection(WUM = 0)： frame2 3 4 frame0 frame1 frame5 RX pin Idle RDBF Normal mode Mute mode Address mark detection(WUM = 1)： frame1 2 3 4 frame0 ADDR=1 ADDR=0...

  • Page 136: Usart Frame Format And Configuration

    AT32F421 Series Reference Manual 12.4 USART frame format and configuration USART data frame consists of start bit, data bit and stop bit, with the last data bit being as a parity bit. USART idle frame size is equal to that of the data frame under current configuration, but all bits are 1. USART brake frame size is the current data frame size plus its stop bit.

  • Page 137: Dma Transfer Introduction

    AT32F421 Series Reference Manual Figure 12-9 Stop bit configuration Clock PEN = 1, Next STOPBN = 00 Data frame Parity bit Start Start 1 Stop bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 1 Stop bit PEN = 1,...

  • Page 138: Baud Rate Generation

    AT32F421 Series Reference Manual transfer in the DMA control register. Data will be loaded from the USART_DT register to the programmed destination after reception request is received by DMA. Configure the source of DMA transfer: Configure the USART_DT register address as the source of DMA transfer in the DMA control register.

  • Page 139: Transmitter

    AT32F421 Series Reference Manual 12.7 Transmitter 12.7.1 Transmitter introduction USART transmitter has its individual TEN control bit. The transmitter and receiver share the same baud rate that is programmable. There is a transmit data buffer (TDR) and a transmit shift register in the USART.

  • Page 140: Receiver

    AT32F421 Series Reference Manual 12.8 Receiver 12.8.1 Receiver introduction USART receiver has its individual REN control bit (bit 2 in the USART_CTRL1 register). The transmitter and receiver share the same baud rate that is programmable. There is a receive data buffer (RDR) and a receive shift register in the USART.

  • Page 141: Start Bit And Noise Detection

    AT32F421 Series Reference Manual buffer. In non-DMA mode, both FERR and RDBF are set at the same time. The latter will generate an  interrupt. In DMA mode, an interrupt is generated if the ERRIEN. When an overrun error occurs: ...

  • Page 142: Tx/Rx Swap

    AT32F421 Series Reference Manual Figure 12-11 Data sampling for noise detection 12.9 Tx/Rx swap When the TRPSWAP bit (USART_CTRL2[15]) is set, Tx/Rx pin can be swapped. Two common scenes are listed below:  If the Tx/Rx were reversed while the user attempts to connect the device externally to a RS-232 chip, it is possible to swap the Tx/Rx through the TRPSWAP bit, without the need of hardware intervention.

  • Page 143: I/O Pin Control

    AT32F421 Series Reference Manual Figure 12-13 USART interrupt map diagram TDBE TDBEIEN TDCIEN CTSCF CTSCFIEN USART interrupt IDLEF IDLEIEN RDBFIEN ROERR RDBFIEN RDBF PERRIEN PERR BFIEN FERR NERR ERRIEN ROERR DMAREN 12.11 I/O pin control The following five interfaces are used for USART communication. RX: Serial data input.

  • Page 144: Status Register (Usart_Sts)

    AT32F421 Series Reference Manual 12.12.1 Status register (USART_STS) Register Reset value Type Description Bit 31: 10 Reserved 0x000000 resd Forced 0 by hardware. CTS change flag This bit is set by hardware when the CTS status line Bit 9 CTSCF rw0c changes.

  • Page 145: Data Register (Usart_Dt)

    AT32F421 Series Reference Manual This bit is set by hardware when parity error occurs. It is cleared by software. USART_STS register followed by a USART_DT read operation) 0: No parity error occurs. 1: Parity error occurs. 12.12.2 Data register (USART_DT) Register Reset value Type...

  • Page 146: Control Register2 (Usart_Ctrl2)

    AT32F421 Series Reference Manual 1: Interrupt is enabled. TDC interrupt enable 0: Interrupt is disabled. Bit 6 TDCIEN 1: Interrupt is enabled. RDBF interrupt enable 0: Interrupt is disabled. Bit 5 RDBFIEN 1: Interrupt is enabled. IDLE interrupt enable 0: Interrupt is disabled. Bit 4 IDLEIEN 1: Interrupt is enabled.

  • Page 147: Control Register3 (Usart_Ctrl3)

    AT32F421 Series Reference Manual 1: Clock is enabled. Clock polarity In synchronous mode or Smartcard mode, this bit is used to select the polarity of the clock output on the clock pin in Bit 10 CLKPOL idle state. 0: Clock output low 1: Clock output high Clock phase This bit is used to select the phase of the clock output on...

  • Page 148: Guard Time And Divider Register (Usart_Gdiv)

    AT32F421 Series Reference Manual 1: Smartcard mode is enabled. Smartcard NACK enable This bit is used to send NACK when parity error occurs. Bit 4 SCNACKEN 0: NACK is disabled when parity error occurs. 1: NACK is enabled when parity error occurs. Single-wire bidirectional half-duplex enable 0: Single-wire bidirectional half-duplex is disabled.

  • Page 149: Serial Peripheral Interface (Spi)

    AT32F421 Series Reference Manual 13 Serial peripheral interface (SPI) 13.1 SPI introduction The SPI interface supports either the SPI protocol or the I S protocol, depending on software configuration. This chapter gives an introduction of the main features and configuration procedure of SPI used as SPI and I S respectively.

  • Page 150: Full-Duplex/Half-Duplex Selector

    AT32F421 Series Reference Manual  Programmable data transfer sequence (MSB-first or LSB-first) Programmable error interrupt flags (receiver overflow error, master mode error and CRC error)   Programmable transmit data buffer empty interrupt and receive data buffer full interrupt  Support transmission and reception using DMA ...

  • Page 151: Figure 13-4 Single-Wire Unidirectional Receive Only In Spi Slave Mode

    AT32F421 Series Reference Manual Figure 13-4 Single-wire unidirectional receive only in SPI slave mode In SPI master mode, it is necessary to wait until the second-to-last RDBF bit is set and then wait another SPI_CPK cycle before disabling SPI. The last RDBF must be set before entering power-saving mode (or gating SPI system clock).

  • Page 152: Chip Select Controller

    AT32F421 Series Reference Manual 13.2.3 Chip select controller The Chip select controller (CS) is used to enable hardware or software control for chip select signals through software configuration. This controller is used to select master/slave device in multi-processor mode, and to avoid conflicts on the data lines by first enabling the SCK signal and then CS signal. The hardware and software configuration procedure is detailed as follows, along with their respective input/output in master and slave mode.

  • Page 153: Dma Transfer

    AT32F421 Series Reference Manual  CRC calculation polynomial is configured by setting the SPI_CPOLY register. CRC enable: The CRC calculation is enabled by setting the CCEN bit. This operation will reset  the SPI_RCRC and SPI_TCRC registers. Select if or when the NTC bit is set, depending on DMA or CPU data register. See the following ...

  • Page 154: Transmitter

    AT32F421 Series Reference Manual  Configure the destination of DMA transfer: Configure the memory address as the destination of DMA transfer in the DMA control register. Data will be loaded from the SPI_DT register to the programmed destination after reception request is received by DMA. ...

  • Page 155: Motorola Mode

    AT32F421 Series Reference Manual generated if the RDBFIE bit is set. When the next received data is ready to be moved to the SPI_DT register, if the previous received data is still not read (RDBF=1), then the data overflow occurs. The previous receive data is not lost, but the next received data will do.

  • Page 156: Figure 13-7 Slave Full-Duplex Communications

    AT32F421 Series Reference Manual Figure 13-7 Slave full-duplex communications Sampling Drive MISO MOSI TDBE flag Transmit buffer empty and RDBF flag software can write data BF flag Software needs to read the received data Half-duplex communication – master transmit Configured as follows: MSTEN=1: Master enable SLBEN=1: Single line bidirectional mode CLKPOL=0, CLKPHA=0: SCK idle output low, use the first edge for sampling...

  • Page 157: Interrupts

    AT32F421 Series Reference Manual CLKPOL=0, CLKPHA=0: SCK idle output low, use the first edge for sampling FBN=0: 8-bit frame Slave transmit: 0xaa, 0xcc, 0xaa Figure 13-10 Slave half-duplex transmit Drive MISO Transmit buffer empty and TDBE flag software can write data BF flag Half-duplex communication –...

  • Page 158: Io Pin Control

    AT32F421 Series Reference Manual 13.2.11 IO pin control When used as SPI, the SPI interface is connected to peripherals through up to four pins. Refer to Section 13.2.2 and Section 13.2.3 for more information on the usage of pins.  MISO: Master In/Slave Out. The pin receives data in SPI master mode, and transmits data in SPI slave mode.

  • Page 159: Operation Mode Selector

    AT32F421 Series Reference Manual ─ Master device transmission ─ Master device reception Programmable clock polarity   Programmable clock frequency (8 KHz to 192 KHz)  Programmable data bits (16 bit, 24 bit, 32 bit)  Programmable channel bits (16 bit, 32 bit) ...

  • Page 160: Audio Protocol Selector

    AT32F421 Series Reference Manual Master device transmission: Set the I2SMSEL bit, and OPERSEL[1:0]=10, the I S will work in master device transmission mode. Figure 13-16 I S master device transmission Master device reception: Set the I2SMSEL bit, and OPERSEL[1: 0]=11, the I S will work in master device reception mode.

  • Page 161: I2S_Clk Controller

    AT32F421 Series Reference Manual  Select channel bits by setting the I2SCBN bit I2SDBN =0: 16 bit I2SDBN =1: 32 bit Note: Read/Write operation mode depends on the selected audio protocols, data bits and channel bits. The following lists all possible configuration combinations and their respective read and write operation mode.

  • Page 162: Figure 13-18 Ck & Mck Source In Master Mode

    AT32F421 Series Reference Manual Figure 13-18 CK & MCK source in master mode Divided by (2xI2SDIV[9:0]+I I2SMCLKOE 2SODD) ~CHLEN Divided by SCLK Divided by 8 (2xI2SDIV[9:0]+I 2SODD) CHLEN Divided by I2SMCLKOE Divided by 4 (2xI2SDIV[9:0]+I 2SODD) Apart from the above-mentioned configuration, the following table lists the values of I2SDIV and I2SODD corresponding to some specific frequencies, as well as their respective error for the users to configure the I2SDIV and I2SODD.

  • Page 163: Dma Transfer

    AT32F421 Series Reference Manual 22050 22203.95 0.698% 22203.95 0.698% 16000 16225.96 1.41% 16225.96 1.41% 11025 11101.97 0.698% 11101.97 0.698% 8000 7959.906 0.501% 7959.906 0.501% 192000 187500 2.34% 187500 2.34% 96000 97826.09 1.90% 93750 2.34% 48000 34615.38 27.88% 48913.04 1.90% 44100 44117.65 0.04% 43269.23...

  • Page 164: Transmitter/Receiver

    AT32F421 Series Reference Manual  Configure DMA interrupt generation after half or full transfer in the DMA control register Enable DMA transfer channel in the DMA control register.  13.3.6 Transmitter/Receiver Whether being used as SPI or I S, there is no difference for CPU. The SPI (in whatever mode) shares the same base address, the same SPI_DT register, the same transmitter and receiver.

  • Page 165: I2S Communication Timings

    AT32F421 Series Reference Manual 13.3.7 I2S communication timings I2S supports four different audio standards: Philips standard, the most significant byte (left-aligned) and the least significant byte (right-aligned) standards, and the PCM standard. Figure 13-19 shows their respective timings. Figure 13-19 Audio standard timings 16CK Left Right...

  • Page 166: Spi Registers

    AT32F421 Series Reference Manual 13.4 SPI registers These peripheral registers must be accessed by half-word (16 bits) or word (32 bits). Table 13-2 SPI register map and reset value Register Offset Reset value SPI_CTRL1 0x00 0x0000 SPI_CTRL2 0x04 0x0000 SPI_STS 0x08 0x0002 SPI_DT...

  • Page 167: Spi Control Register2 (Spi_Ctrl2)

    AT32F421 Series Reference Manual LSB transmit first This bit is used to select for MST transfer first or LSB Bit 7 transfer first. 0: MSB 1: LSB SPI enable Bit 6 SPIEN 0: Disabled 1: Enabled Master clock frequency division In master mode, the peripheral clock divided by the prescaler is used as SPI clock.

  • Page 168: Spi Status Register (Spi_Sts)

    AT32F421 Series Reference Manual 13.4.3 SPI status register (SPI_STS) Register Reset value Type Description Forced to be 0 by hardware Bit 15: 8 Reserved 0x00 resd Busy flag 0: SPI is not busy. Bit 7 1: SPI is busy. Receiver overflow error 0: No overflow error Bit 6 ROERR...

  • Page 169: Spirxcrc Register (Spi_Rcrc)

    AT32F421 Series Reference Manual 13.4.6 SPIRxCRC register (SPI_RCRC) (Not used in I S mode) Register Reset value Type Description Receive CRC When CRC calculation is enabled, this register contains the CRC value computed based on the received data. This register is reset when the CCEN bit in the SPI_CTRL1 register is cleared.

  • Page 170: Spi_I2S Prescaler Register (Spi_I2Sclkp)

    AT32F421 Series Reference Manual 00: 16-bit data length 01: 24-bit data length 10: 32-bit data length 11: Not allowed. S channel bit num This bit can be configured only when the I S is set to 16- bit data; otherwise, it is fixed to 32-bit by hardware. Bit 0 I2SCBN 0: 16-bit wide...

  • Page 171: Timer

    AT32F421 Series Reference Manual 14 Timer AT32F421 timers include basic timers, general-purpose timers, and advanced timers. Please refer to Section 14.1~ Section 14.6 for the detailed function modes. All functions of different timers are shown in the following tables. Table 14-1 TMR functional comparison Capture/ Timer Counter...

  • Page 172: General-Purpose Timer (Tmr6)

    AT32F421 Series Reference Manual 14.1 General-purpose timer (TMR6) 14.1.1 TMR6 introduction The basic timer (TMR6) consists of a 16-bit upcounter and the corresponding control logic. without being connected to external I/Os. 14.1.2 TMR6 main features  Source of counter clock: internal clock ...

  • Page 173: Debug Mode

    AT32F421 Series Reference Manual Setting the TMREN bit (TMREN=1) enables the timer to start counting. Base on synchronization logic, however, the actual enable signal TMR_EN is set 1 clock cycle after the TMREN is set. Figure 14-3 Counter structure PRBEN DIV_shadow TMRx_DIV Preload...

  • Page 174: Tmr6 Registers

    AT32F421 Series Reference Manual counting when the TMRx_PAUSE bit is set. 14.1.4 TMR6 registers These peripheral registers must be accessed by word (32 bits). Table 14-2, all the TMR6 registers are mapped to a 16-bit addressable space. Table 14-2 TMR6 register map and reset value Register Offset Reset value...

  • Page 175: Tmr6 Control Register1 (Tmrx_Ctrl1)

    AT32F421 Series Reference Manual 14.1.4.1 TMR6 control register1 (TMRx_CTRL1) Register Reset value Type Description Bit 15: 8 Reserved 0x00 resd Kept at its default value. Period buffer enable Bit 7 PRBEN 0: Period buffer is disabled. 1: Period buffer is enabled. Bit 6: 4 Reserved resd...

  • Page 176: Tmr6 Interrupt Status Register (Tmrx_Ists)

    AT32F421 Series Reference Manual 14.1.4.4 TMR6 interrupt status register (TMRx_ISTS) Register Reset value Type Description Bit 15: 1 Reserved 0x0000 resd Kept at its default value. Overflow interrupt flag This bit is set by hardware at an overflow event. It is cleared by software.

  • Page 177: General-Purpose Timer (Tmr3)

    AT32F421 Series Reference Manual 14.2 General-purpose timer (TMR3) 14.2.1 TMR3 introduction The general-purpose timer TMR3 consists of a 16-bit counter supporting up, down, up/down (bidirectional) counting modes, four capture/compare registers, and four independent channels to achieve input capture and programmable PWM output. 14.2.2 TMR3 main features ...

  • Page 178: Figure 14-8 Count Clock Block Diagram

    AT32F421 Series Reference Manual Figure 14-8 Count clock block diagram Encoder mode (SMSEL=3'b001/010/011) CK_INT(form CRM) CI1FP1/CI2FP2 STIS[1:0] External clock mode A STIS[2] (SMSEL=3'b111) Internal trigger DIV_counter CK_CNT CNT_counter STIS[1:0] TRGIN C1INC C1IFP1 polarity edge External trigger External clock mode B detector C2IPF2 (ECMBEN=1)

  • Page 179: Figure 14-10 Block Diagram Of External Clock Mode A

    AT32F421 Series Reference Manual TMRx_STCTRL register) and external signal filter (by setting the ESF[3:0] bit in the TMRx_STCTRL register). – Set the TRGIN signal source by setting the STIS[1:0] bit in the TMRx_STCTRL register. – Enable external clock mode A by setting SMSEL=3’b111 in the TMRx_STCTRL register. –...

  • Page 180: Figure 14-13 Counting In External Clock Mode B, With Pr=0X32 And Div=0X0

    AT32F421 Series Reference Manual Figure 14-13 Counting in external clock mode B, with PR=0x32 and DIV=0x0 TMR_CLK CK_CNT COUNTER ESDIV[1:0] ESF[3:0] 0000 OVFIF Clear Internal trigger input (ISx) Timer synchronization allows interconnection between several timers. The TMR_CLK of one timer can be provided by the TRGOUT signal output by another timer.

  • Page 181: Counting Mode

    AT32F421 Series Reference Manual 14.2.3.2 Counting mode The TMR3 timer supports several counting modes to meet different application scenarios. It has an internal 16-bit up, down, up/down counter. The TMRx_PR register is used to configure the counting period. The value in the TMRx_PR is immediately moved to the shadow register by default.

  • Page 182: Figure 14-17 Overflow Event When Prben=1

    AT32F421 Series Reference Manual Figure 14-17 Overflow event when PRBEN=1 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Downcounting mode Set CMSEL[1:0]=2’b00 and OWCDIR=1’b1 in the TMRx_CTRL1 register to enable downcounting mode. In downcounting mode, the counter counts from the value programmed in the TMRx_PR register down to 0, and restarts from the value programmed, and generates a counter underflow event.

  • Page 183: Figure 14-19 Counter Timing Diagram, Internal Clock Divided By 1, Tmrx_Pr=0X32

    AT32F421 Series Reference Manual Figure 14-19 Counter timing diagram, internal clock divided by 1, TMRx_PR=0x32 TMR_CLK COUNTER OWCDIR PR[15:0] DIV[15:0] TWCMSEL [1：0] OVFIF Clear Clear Clear Encoder interface mode To enable the encoder interface mode, write SMSEL[2: 0]= 3’b001/3’b010/3’b011. In this mode, the two inputs (C1IN/C2IN) are required.

  • Page 184: Tmr Input Function

    AT32F421 Series Reference Manual – Set the DIV[15:0] bit in the TMRx_DIV register to set the counting frequency. – Set the IOs corresponding to TMRx_CH1 and TMRx_CH2 as multiplexed mode. – Set the TMREN bit in the TMRx_CTRL1 register to enable the counter. Table 14-4 Counting direction versus encoder signals C1INFP1 signal C2INFP2 signal...

  • Page 185: Figure 14-22 Input/Output Channel 1 Main Circuit

    AT32F421 Series Reference Manual Figure 14-22 Input/output channel 1 main circuit C1INSEL TMRx_CH3 edge detector input divider STCI TMRx_CH2 C1IRAW C1DF C1P/C1CP C1IDIV C1EN C1IFP1 C1IN TMRx_CH1 filter C2IFP1 Capture trigger C1DT_shadow CNT counter Capture C1DT Compare C1DT preload C1OCTRL C1OBEN Overflow event C1ORAW...

  • Page 186: Tmr Output Function

    AT32F421 Series Reference Manual  Set C1C=2‘b01 to set C1IN as C1IFP1;  Set C1P=1’b0 to set C1IFP1 rising edge active;  Set C2C=2‘b10 to set C2IN as C1IFP2;  Set C2P=1’b1 to set C1IFP2 falling edge active;  Set STIS=3’b101 to set C1IFP1 as the slave timer trigger signal; ...

  • Page 187: Figure 14-26 Capture/Compare Channel Output Stage (Channel 1 To 4)

    AT32F421 Series Reference Manual Figure 14-26 Capture/compare channel output stage (channel 1 to 4) Output mode CNT_value controller Polarity CNT_value=CxDT Output enable selection TMRx_CM1 Compare CxORAW /CM2 CNT_value>CxDT CxEN CxOUT CxDT To the master mode controller Output mode Write CxC[2: 0]≠2’b00 to configure the channel as output to implement multiple output modes. In this case, the counter value is compared with the value in the TMR3_CxDT register, and the intermediate signal CxORAW is generated according to the output mode selected by CxOCTRL[2: 0], which is sent to IO after being processed by the output control circuit.

  • Page 188: Figure 14-27 C1Oraw Toggles When Counter Value Matches The C1Dt Value

    AT32F421 Series Reference Manual gives an example of the combination between upcounting mode and PWM mode A. The Figure 14-28 output signal behaves when PR=0x32 but CxDT is configured with a different value. gives an example of the combination between up/down counting mode and PWM mode Figure 14-29 A.

  • Page 189: Figure 14-30 One-Pulse Mode

    AT32F421 Series Reference Manual Figure 14-30 One-pulse mode COUNTER PR[15：0] C1DT[15：0] TRGIN C1ORAW C1OUT Master timer event output When TMR is selected as the master timer, the following signal sources can be selected as TRGOUT signal to output to the salve timer, by setting the PTOS bit in the TMRxCTRL2 register. –...

  • Page 190: Tmr Synchronization

    AT32F421 Series Reference Manual 14.2.3.5 TMR synchronization The timers are linked together internally for timer synchronization. Master timer is selected by setting the PTOS[2: 0] bit; Slave timer is selected by setting the SMSEL[2: 0] bit. Slave mode includes: Slave mode: Reset mode The counter and its prescaler can be reset by a selected trigger signal.

  • Page 191: Figure 14-35 Master/Slave Timer Connection

    AT32F421 Series Reference Manual Master/slave timer interconnection Both Master and slave timer can be configured in different master and slave modes respectively. The combination of both them can be used for various purposes. Figure 14-35 provides an example of interconnection between master timer and slave timer. Figure 14-35 Master/slave timer connection Master Timer Slave Timer...

  • Page 192: Debug Mode

    AT32F421 Series Reference Manual Starting master and slave timers synchronously by an external trigger: In this example, configure the master timer as master/slave mode synchronously and enable its slave timer synchronization function. This mode is used for synchronization between master timer and slave timer.

  • Page 193: Control Register1 (Tmr3_Ctrl1)

    AT32F421 Series Reference Manual TMR3_PR 0x2C 0x0000 0000 TMR3_C1DT 0x34 0x0000 0000 TMR3_C2DT 0x38 0x0000 0000 TMR3_C3DT 0x3C 0x0000 0000 TMR3_C4DT 0x40 0x0000 0000 TMR3_DMACTRL 0x48 0x0000 TMR3_DMADT 0x4C 0x0000 14.2.4.1 Control register1 (TMR3_CTRL1) Register Reset value Type Description Bit 15: 10 Reserved 0x00 resd...

  • Page 194: Control Register2 (Tmr3_Ctrl2)

    AT32F421 Series Reference Manual 14.2.4.2 Control register2 (TMR3_CTRL2) Register Reset value Type Description Bit 15: 8 Reserved 0x00 resd Kept at its default value. C1IN selection 0: CH1 pin is connected to C1IRAW input Bit 7 C1INSEL 1: The XOR result of CH1, CH2 and CH3 pins is connected to C1IRAW input Master TMR output selection This field is used to select the TMRx signal sent to the...

  • Page 195: Dma/Interrupt Enable Register (Tmr3_Iden)

    AT32F421 Series Reference Manual 1: Enabled Subordinate TMR input selection This field is used to select the subordinate TMR input. 000: Internal selection 0 (IS0) 001: Internal selection 1 (IS1) 010: Internal selection 2 (IS2) 011: Internal selection 3 (IS3) Bit 6: 4 STIS 100: C1IRAW input detector (C1INC)

  • Page 196: Interrupt Status Register (Tmr3_Ists)

    AT32F421 Series Reference Manual Channel 2 interrupt enable Bit 2 C2IEN 0: Disabled 1: Enabled Channel 1 interrupt enable Bit 1 C1IEN 0: Disabled 1: Enabled Overflow interrupt enable Bit 0 OVFIEN 0: Disabled 1: Enabled 14.2.4.5 Interrupt status register (TMR3_ISTS) Register Reset value Type...

  • Page 197: Software Event Register (Tmr3_Sw Evt)

    AT32F421 Series Reference Manual 14.2.4.6 Software event register (TMR3_SWEVT) Register Reset value Type Description Kept at its default value. Bit 15: 7 Reserved 0x000 resd Trigger event triggered by software This bit is set by software to generate a trigger event. Bit 6 TRGSWTR 0: No effect...
  • Page 198 AT32F421 Series Reference Manual －OWCDIR=0, C1ORAW is low once TMR3_ C1DT >TMR3_CVAL, else high; －OWCDIR=1, C1ORAW is high once TMR3_ C1DT <TMR3_CVAL, else low. Note: In the configurations other than 000’, the C1OUT is connected to C1ORAW. The C1OUT output level is not only subject to the changes of C1ORAW, but also the output polarity set by CCTRL.

  • Page 199: Channel Mode Register2 (Tmr3_Cm2)

    AT32F421 Series Reference Manual 0111: f /4, N=8 ���������������� ������ 1111: f /32, N=8 ���������������� ������ Channel 1 input divider This field defines Channel 1 input divider. 00: No divider. An input capture is generated at each active edge. Bit 3: 2 C1IDIV 01: An input compare is generated every 2 active edges 10: An input compare is generated every 4 active edges...

  • Page 200: Channel Control Register (Tmr3_Cctrl)

    AT32F421 Series Reference Manual Bit 3: 2 C3IDIV Channel 3 input divider Channel 3 configuration This field is used to define the direction of the channel 1 (input or output), and the selection of input pin when C3EN=’0’: Bit 1:0 00: Output 01: Input, C3IN is mapped on C3IFP3 10: Input, C3IN is mapped on C4IFP3...

  • Page 201: Division Value (Tmr3_Div)

    AT32F421 Series Reference Manual 14.2.4.11 Division value (TMR3_DIV) Register Reset value Type Description Divider value The counter clock frequency f /(DIV[15: CK_CNT TMR_CLK Bit 15: 0 0x0000 0]+1). DIV contains the value written at an overflow event. 14.2.4.12 Period register (TMR3_PR) Register Reset value Type...

  • Page 202: Channel 4 Data Register (Tmr3_C4Dt)

    AT32F421 Series Reference Manual 14.2.4.16 Channel 4 data register (TMR3_C4DT) Register Reset value Type Description Bit 31: 16 0x0000 Reserved resd Kept at its default value Channel 4 data register When the channel 4 is configured as input mode: The C4DT is the CVAL value stored by the last channel 4 input event (C1IN) Bit 15: 0 C4DT...

  • Page 203: General-Purpose Timer (Tmr14)

    AT32F421 Series Reference Manual 14.3 General-purpose timer (TMR14) 14.3.1 TMR14 introduction The general-purpose timer TMR14 consists of a 16-bit counter supporting upcounting mode. The timer can be synchronized together with other timers. 14.3.2 TMR14 main features  Source of count clock : internal clock ...

  • Page 204: Counting Mode

    AT32F421 Series Reference Manual Figure 14-41 Counter timing with prescaler value changing from 1 to 4 TMR_CLK CK_CNT COUNTER DIV[15：0] PR[15：0] OVFIF Clear 14.3.3.2 Counting mode The general-purpose timer TMR14 consists of a 16-bit counter supporting upcounting mode. The TMRx_PR register is used to configure the counting period. The value in the TMRx_PR is immediately moved to the shadow register by default.

  • Page 205: Tmr Input Function

    AT32F421 Series Reference Manual Figure 14-43 Overflow event when PRBEN=0 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Figure 14-44 Overflow event when PRBEN=1 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear 14.3.3.3 TMR input function The TMR14 timer has one independent channel that can be configured as input or output. As input, each channel input signal is processed as below: –...

  • Page 206: Tmr Output Function

    AT32F421 Series Reference Manual Figure 14-46 Channel 1 input stage STCI C1IPS C1IF C1IFP1 C1IN C2IFP1 C1SWTR Input mode In input mode, the TMRx_CxDT registers latch the current counter values after the selected trigger signal is detected, and the capture compare interrupt flag bit (CxIF) is set. An interrupt/DMA request will be generated if the CxIEN bit and CxDEN bit are enabled.

  • Page 207: Debug Mode

    AT32F421 Series Reference Manual – Set CxEN bit and CxCEN bit in the TMRx_CCTRL register to enable channel output; – Set the OEN bit in the TMRx_BRK register to enable TMRx output; – Set the corresponding GPIO of TMR output channel as the multiplexed mode; –...

  • Page 208: Control Register1 (Tmr14_Ctrl1)

    AT32F421 Series Reference Manual These peripheral registers must be accessed by word (32 bits). All TMR14 registers are mapped into a 16-bit addressable space. Table 14-7 TMR14 register map and reset value Register name Register Reset value TMR14_CTRL1 0x00 0x0000 TMR14_IDEN 0x0C 0x0000...

  • Page 209: Software Event Register (Tmr14_Swevt)

    AT32F421 Series Reference Manual This bit indicates whether a recapture is detected when C1IF=1. This bit is set by hardware, and cleared by writing “0”. 0: No capture is detected 1: Capture is detected. Bit 8: 2 Reserved 0x00 resd Kept at its default value.
  • Page 210 AT32F421 Series Reference Manual 110: PWM mode A – OWCDIR=0, C1ORAW is high once TMR14_C1DT>TMR14_CVAL, else low; － OWCDIR=1, C1ORAW is low once TMR14_ C1DT <TMR14_CVAL, else high; 111: PWM mode B － OWCDIR=0, C1ORAW is low once TMR14_ C1DT >TMR14_CVAL, else high;...
  • Page 211 AT32F421 Series Reference Manual 00: No divider. An input capture is generated at each active edge. 01: An input compare is generated every 2 active edges 10: An input compare is generated every 4 active edges 11: An input compare is generated every 8 active edges Note: the divider is reset once C1EN=’0’...

  • Page 212: Channel Control Register (Tmr14_Cctrl)

    AT32F421 Series Reference Manual 14.3.4.6 Channel control register (TMR14_CCTRL) Register Reset value Type Description Bit 15: 4 Reserved resd Kept at its default value. Channel 1 complementary polarity Bit 3 C1CP Please refer to C1P description. Bit 2 Reserved resd Kept at its default value.

  • Page 213: Channel Input Remap Register (Tmr14_Rmp)

    AT32F421 Series Reference Manual 14.3.4.11 Channel input remap register (TMR14_RMP) Register Reset value Type Description Bit 15: 0 Reserved 0x00 resd Kept at its default value. TMR14 channel 1 input remap 00: TMR14 channel 1 input is connected to GPIO Bit 1: 0 TMR14_CH1_IRMP 01: ERTC_CLK...

  • Page 214: General-Purpose Timer (Tmr15)

    AT32F421 Series Reference Manual 14.4 General-purpose timer (TMR15) 14.4.1 TMR15 introduction The general-purpose timer TMR14 consists of a 16-bit counter supporting upcounting mode. It has two capture/compare registers, and two independent channels to achieve dead-time insert, input capture and programmable PWM output. 14.4.2 TMR15 main features ...

  • Page 215: Figure 14-52 Use Ck_Int To Drive Counter, With Tmrx_Div=0X0 And Tmrx_Pr=0X16

    AT32F421 Series Reference Manual Internal clock (CK_INT) By default, the CK_INT divided by a prescaler is used to drive the counter to start counting. The configuration process is as follows: – Set the CLKDIV[1:0] bit in the TMRx_CTRL1 register to set the CK_INT frequency; –...

  • Page 216: Counting Mode

    AT32F421 Series Reference Manual Figure 14-54 Counting in external clock mode A, with PR=0x32 and DIV=0x0 TMR_CLK C2IRAW CNT_CLK COUNTER STIS[2:0] C2IF[2:0] OVFIF Clear Internal trigger input (ISx) Timer synchronization allows interconnection between several timers. The TMR_CLK of one timer can be provided by the TRGOUT signal output by another timer.

  • Page 217: Figure 14-56 Counter Structure

    AT32F421 Series Reference Manual count clock period (DIV[15:0]+1). Similar to the TMRx_PR register, when the periodic buffer is enabled, the value in the TMRx_DIV register is updated to the shadow register at an overflow event. Reading the TMRx_CNT register returns to the current counter value, and writing to the TMRx_CNT register updates the current counter value to the value being written.

  • Page 218: Tmr Input Function

    AT32F421 Series Reference Manual each counter overflow. An overflow event is generated only when the repetition counter reaches 0. The frequency of the overflow event can be adjusted by setting the repetition counter value. Figure 14-59 OVFIF when RPR=2 COUNTER PR[15:0] RPR[7:0] OVFIF...

  • Page 219: Figure 14-61 Channel 1 Input Stage

    AT32F421 Series Reference Manual Figure 14-61 Channel 1 input stage STIS STCI C1INC input divider C1IPS C1DF C1P/C1CP C1EN CNT counter Capture C1DT C1IF C1IDIV TMRx_CH1 C1IN C1IFP1 edge detector filter C1SWTR C2DF C2P/C2CP C2IFP1 TMRx_CH2 C2IF edge detector filter Input mode In input mode, the TMRx_CxDT registers latch the current counter values after the selected trigger signal is detected, and the capture compare interrupt flag bit (CxIF) is set to 1.

  • Page 220: Tmr Output Function

    AT32F421 Series Reference Manual Figure 14-62 PWM input mode configuration C1C(2'b01) edge detector STCI C1P=0 C1DF C1IF C1IRAW C1EN Capture C1DT C1IFP1(pos) C1IN Capture trigger C1CP=0 filter C2IFP1 SMSEL(3'b110) (CH1 period) STIS(3'b101) Trigger mode C1INC CNT counter Hang reset mode CI2FP2 Reset mode...

  • Page 221: Figure 14-65 Channel 2 Output Stage

    AT32F421 Series Reference Manual Figure 14-65 Channel 2 output stage Output mode CNT_value controller Polarity CNT_value=C2DT Output enable selection Compare TMRx_CM1 C2ORAW CNT_value>C2DT C2EN C2OUT C2DT To the master mode controller Output mode Write CxC[2: 0]≠2’b00 to configure the channel as output to implement multiple output modes. In this case, the counter value is compared with the value in the TMRx_CxDT register, and the intermediate signal CxORAW is generated according to the output mode selected by CxOCTRL[2: 0], which is sent to IO after being processed by the output control circuit.

  • Page 222: Figure 14-66 C1Oraw Toggles When Counter Value Matches The C1Dt Value

    AT32F421 Series Reference Manual Figure 14-66 gives an example of output compare mode (toggle) with C1DT=0x3. When the counter value is equal to 0x3, C1OUT toggles. gives an example of the combination between upcounting mode and PWM mode A. The Figure 14-67 output signal behaves when PR=0x32 but CxDT is configured with a different value.

  • Page 223: Figure 14-68 One-Pulse Mode

    AT32F421 Series Reference Manual Figure 14-68 One-pulse mode COUNTER PR[15：0] C1DT[15：0] TRGIN C1ORAW C1OUT Master timer event output When TMR is selected as the master timer, the following signal sources can be selected as TRGOUT signal to output to the salve timer, by setting the PTOS bit in the TMRxCTRL2 register. –...

  • Page 224: Tmr Brake Function

    AT32F421 Series Reference Manual Figure 14-69 Complementary output with dead-time insertion C1ORAW C1OUT Delay C1COUT Delay C1ORAW C1OUT Delay > positive pulse C1COUT C1ORAW Delay > negative pulse C1OUT C1COUT 14.4.3.5 TMR brake function When the brake function is enabled (BRKEN=1), the CxOUT and CxCOUT are jointly controlled by OEN, FCSODIS, FCSOEN, CxIOS and CxCIOS.

  • Page 225: Tmr Synchronization

    AT32F421 Series Reference Manual Figure 14-70 TMR control output Clock failure event break enable From clock control CSS(Clock Security System) overflow event break break BRKEN auto enable trigger event AOEN TMRx_BRK BRKV polarity selection polarity select CxEN run state holistic-out FCSOEN disable CxOUT enable state...

  • Page 226: Debug Mode

    AT32F421 Series Reference Manual Figure 14-72 Example of reset mode TMR_CLK COUNTER PR[15:0] DIV[15:0] STIS[2：0] SMSEL[2：0] CI1F1 OVFIF TRGIF Slave mode: Suspend mode In this mode, the counter is controlled by a selected trigger input. The counter starts counting when the trigger input is high and stops as soon as the trigger input is low.

  • Page 227: Tmr15 Registers

    AT32F421 Series Reference Manual 14.4.4 TMR15 registers These peripheral registers must be accessed by word (32 bits). TMR15 registers are mapped into a 16-bit addressable space. Table 14-10 TMR15 register map and reset value Register name Register Reset value TMR15_CTRL1 0x00 0x0000 TMR15_CTRL2...

  • Page 228: Control Register2 (Tmr15_Ctrl2)

    AT32F421 Series Reference Manual 14.4.4.2 Control register2 (TMR15_CTRL2) Register Reset value Type Description Bit 31: 11 Reserved resd Kept at its default value. Bit 10 C2IOS Channel 2 idle output state Channel 1 complementary idle output state Output OFF (OEN = 0), after dead-timer generation: Bit 9 C1CIOS 0: C1COUT=0...

  • Page 229: Tmr15 Dma/Interrupt Enable Register (Tmr15_Iden)

    AT32F421 Series Reference Manual Bit 3 Reserved resd Kept at its default value Subordinate TMR mode selection 000: Slave mode is disabled 100: Reset mode — Rising edge of the TRGIN input reinitializes the counter 101: Suspend mode — The counter starts counting when Bit 2: 0 SMSEL the TRGIN is high...

  • Page 230: Tmr15 Interrupt Status Register (Tmr15_Ists)

    AT32F421 Series Reference Manual 14.4.4.5 TMR15 interrupt status register (TMR15_ISTS) Register Reset value Type Description Kept at its default value. Bit 15: 11 Reserved resd Channel 2 recapture flag Bit 10 C2RF rw0c Please refer to C1RF description. Channel 1 recapture flag This bit indicates whether a recapture is detected when C1IF=1.

  • Page 231: Tmr15 Software Event Register (Tmr15_Sw Evt)

    AT32F421 Series Reference Manual Overflow event is generated when the counter value CVAL is re-initiated by a trigger event. 14.4.4.6 TMR15 software event register (TMR15_SWEVT) Register Reset value Type Description Kept at its default value. Bit 15: 8 Reserved resd Brake event triggered by software This bit is set to generate a brake event by software.
  • Page 232 AT32F421 Series Reference Manual Channel 1 output switch enable Bit 7 C1OSEN 0: C1ORAW is not affected by EXT input 1: When EXT input level is high, C1ORAW is cleared. Channel 1 output control This field defines the behavior of the original signal C1ORAW.
  • Page 233 AT32F421 Series Reference Manual Input capture mode: Register Reset value Type Description Channel 2 digital filter Bit 15: 12 C2DF Channel 2 input divider Bit 11: 10 C2IDIV Channel 2 configuration This field is used to define the direction of the channel 2 (input or output), and the selection of input pin when C2EN=’0’: 00: Output...

  • Page 234: Tmr15 Channel Control Register (Tmr15_Cctrl)

    AT32F421 Series Reference Manual 14.4.4.8 TMR15 channel control register (TMR15_CCTRL) Register Reset value Type Description Kept at its default value. Bit 15: 8 Reserved resd Channel 2 complementary polarity Bit 7 C2CP This bit defines the active edge for input signals. Refer to C1P description.

  • Page 235: Table 14-11 Complementary Output Channel Cxout And Cxcout Control Bits With Brake Function

    AT32F421 Series Reference Manual Table 14-11 Complementary output channel CxOUT and CxCOUT control bits with brake function Control bit Output state (1) FCSODIS FCSOEN CxEN CxCEN OEN bit CxOUT output state CxCOUT output state Output disabled Output disabled (no driven by the timer) (no driven by the timer) CxOUT=0, Cx_EN=0 CxCOUT=0, CxCEN=0...

  • Page 236: Tmr15 Counter Value (Tmr15_Cval)

    AT32F421 Series Reference Manual 14.4.4.9 TMR15 Counter value (TMR15_CVAL) Register Reset value Type Description Bit 15: 0 CVAL Counter value 14.4.4.10 TMR15 Division value (TMR15_DIV) Register Reset value Type Description Divider value The counter clock frequency f /(DIV[15: CK_CNT TMR_CLK 0]+1).

  • Page 237: Tmr15 Brake Register (Tmr15_Brk)

    AT32F421 Series Reference Manual 14.4.4.15 TMR15 brake register (TMR15_BRK) Register Reset value Type Description Bit 31: 17 Reserved resd Kept at its default value. Brake input filter This field is used to configure the filter for brake input. If the number of filter is N, it indicates that the input edge can pass through the filter only after N sampling events.

  • Page 238: Tmr15 Dma Control Register (Tmr15_Dmactrl)

    AT32F421 Series Reference Manual 01: Write protection level 3, and the following bits are write protected: TMR1_BRK: DTC, BRKEN, BRKV and AOEN TMR1_CTRL2: CxIOS and CxCIOS 10: Write protection level 2. The following bits and all bits in level 3 are write protected: TMR1_CCTRL: CxP and CxCP TMR1_BRK: FCSODIS and FCSOEN 11: Write protection level 1.

  • Page 239: General-Purpose Timer (Tmr16 And Tmr17)

    AT32F421 Series Reference Manual 14.5 General-purpose timer (TMR16 and TMR17) 14.5.1 TMR16 and TMR17 introduction The general-purpose timers TMR16 and TMR17 consist of a 16-bit counter supporting upcounting mode. Each of them has a capture/compare register, and an independent channels to achieve dead-time insert, input capture and programmable PWM output.

  • Page 240: Counting Mode

    AT32F421 Series Reference Manual Figure 14-77 Use CK_INT to drive counter, with TMRx_DIV=0x0 and TMRx_PR=0x16 CK_INT TMREN COUNTER overflow OVFIF 14.5.3.2 Counting mode The timer (TMR16 and TMR17) supports several counting modes to meet different application scenarios. Each timer has an internal 16-bit up counter. The TMRx_PR register is used to configure the counting period.

  • Page 241: Tmr Input Function

    AT32F421 Series Reference Manual Figure 14-79 Overflow event when PRBEN=0 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Figure 14-80 Overflow event when PRBEN=1 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Repetition counter mode: The TMRx_RPR register is used to configure the counting period of repetition counter. The repletion counter mode is enabled when the repetition counter value is not equal to 0.

  • Page 242: Tmr Output Function

    AT32F421 Series Reference Manual Figure 14-82 Input/output channel 1 main circuit filter edge detector input divider STCI C1IRAW C1DF C1P/C1CP TMRx_CH1 C1IDIV C1EN C1IFP1 C1IN C2IFP1 Capture trigger C1DT_shadow Compare CNT counter Capture C1DT C1DT preload C1OCTRL C1OBEN Overflow event C1ORAW polarity select polarity select...
  • Page 243 AT32F421 Series Reference Manual signal CxORAW is generated according to the output mode selected by CxOCTRL[2: 0], which is sent to IO after being processed by the output control circuit. The period of the output signal is configured by the TMRx_PR register, while the duty cycle by the TMRx_CxDT register. Output compare modes include: ...

  • Page 244: Figure 14-85 C1Oraw Toggles When Counter Value Matches The C1Dt Value

    AT32F421 Series Reference Manual Figure 14-85 C1ORAW toggles when counter value matches the C1DT value TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL [2：0] C1DT[15：0] C1ORAW Figure 14-86 Upcounting mode and PWM mode A TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL[2：0] C1DT[15：0] C1ORAW CIDT[15：0] C1ORAW C1DT[15：0] C1ORAW >32...

  • Page 245: Tmr Brake Function

    AT32F421 Series Reference Manual CxCEN=1. Figure 14-88 Complementary output with dead-time insertion C1ORAW C1OUT Delay C1COUT Delay C1ORAW C1OUT Delay > positive pulse C1COUT C1ORAW Delay > negative pulse C1OUT C1COUT 14.5.3.5 TMR brake function When the brake feature is enabled (BRKEN=1), the CxOUT and CxCOUT are jointly controlled by OEN, FCSODIS, FCSOEN, CxIOS and CxCIOS.

  • Page 246: Debug Mode

    AT32F421 Series Reference Manual Figure 14-89 TMR output control Clock failure event break enable From clock control CSS(Clock Security System) overflow event break break BRKEN auto enable trigger event AOEN TMRx_BRK BRKV polarity selection polarity select CxEN run state holistic-out FCSOEN disable CxOUT enable state...

  • Page 247: Tmr16 And Tmr17 Control Register1 (Tmrx_Ctrl1)

    AT32F421 Series Reference Manual TMRx_IDEN 0x0C 0x0000 TMRx_ISTS 0x10 0x0000 TMRx_SWEVT 0x14 0x0000 TMRx_CM1 0x18 0x0000 TMRx_CCTRL 0x20 0x0000 TMRx_CVAL 0x24 0x0000 TMRx_DIV 0x28 0x0000 TMRx_PR 0x2C 0x0000 TMRx_RPR 0x30 0x0000 TMRx_C1DT 0x34 0x0000 TMRx_BRK 0x44 0x0000 TMRx_DMACTRL 0x48 0x0000 TMRx_DMADT 0x4C 0x0000...

  • Page 248: Tmr16 And Tmr17 Dma/Interrupt Enable Register (Tmrx_Id

    AT32F421 Series Reference Manual DMA request source Bit 3 0: Capture/compare event 1: Overflow event Channel control bit flash selection This bit only acts on channels with complementary output. If the channel control bits are buffered: Bit 2 CCFS 0: Control bits are updated by setting the HALL bit 1: Control bits are updated by setting the HALL bit or a rising edge on TRGIN.

  • Page 249: Tmr16 And Tmr17 Software Event Register (Tmrx_Swevt)

    AT32F421 Series Reference Manual HALL even: CxEN, CxCEN and CxOCTRL are updated. Bit 4: 2 Reserved resd Kept at its default value. Channel 1 interrupt flag If the channel 1 is configured as input mode: This bit is set by hardware on a capture event. It is cleared by software or read access to the TMRx_C1DT 0: No capture event occurs Bit 1...
  • Page 250 AT32F421 Series Reference Manual This field defines the behavior of the original signal C1ORAW. 000: Disconnected. C1ORAW is disconnected from C1OUT; 001: C1ORAW is high when TMRx_CVAL=TMRx_C1DT 010: C1ORAW is low when TMRx_CVAL=TMRx_C1DT 011: Switch C1ORAW level when TMRx_CVAL=TMRx_C1DT 100: C1ORAW is forced low 101: C1ORAW is forced high.
  • Page 251 AT32F421 Series Reference Manual 1100: f /16, N=8 ���������������� ������ 0101: f /2, N=8 ���������������� ������ 1101: f /32, N=5 ���������������� ������ 0110: f /4, N=6 �������������� ������ 1110: f /32, N=6 ���������������� ������ 0111: f /4, N=8 ���������������� ������ 1111: f /32, N=8 ����������������...

  • Page 252: Tmr16 And Tmr17 Channel Control Register (Tmrx_Cctrl)

    AT32F421 Series Reference Manual 14.5.4.7 TMR16 and TMR17 channel control register (TMRx_CCTRL) Register Reset value Type Description Bit 15: 4 Reserved resd Kept its default value. Channel 1 complementary polarity Bit 3 C1CP 0: C1COUT is active high. 1: C1COUT is active low. Channel 1 complementary enable Bit 2 C1CEN...

  • Page 253: Tmr16 And Tmr17 Counter Value (Tmrx_Cval)

    AT32F421 Series Reference Manual Output disabled (corresponding IO disconnected from timer, and IO floating) Asynchronously: CxOUT=CxP, Cx_EN=0, CxCOUT=CxCP, CxCEN=0; If the clock is present: after a dead-time, CxOUT=CxIOS, CxCOUT=CxCIOS, assuming that CxIOS and CxCIOS do not correspond to CxOUT and CxCOUT active level.

  • Page 254: Tmr16 And Tmr17 Brake Register (Tmrx_Brk)

    AT32F421 Series Reference Manual 14.5.4.13 TMR16 and TMR17 brake register (TMRx_BRK) Register Reset value Type Description Bit 31: 16 Reserved resd Kept at its default value. Output enable This bit is used to enable the output of CxOUT and CxCOUT for those channels that are configured as Bit 15 output.

  • Page 255: Tmr16 And Tmr17 Dma Control Register (Tmrx_Dmactrl)

    AT32F421 Series Reference Manual 14.5.4.14 TMR16 and TMR17 DMA control register (TMRx_DMACTRL) Register Reset value Type Description Bit 15:13 Reserved resd Kept at its default value. DMA transfer bytes This field defines the number of DMA transfers: 00000: 1 byte 00001: 2 bytes Bit 12:8 0x00...

  • Page 256: Advanced-Control Timers (Tmr1)

    AT32F421 Series Reference Manual 14.6 Advanced-control timers (TMR1) 14.6.1 TMR1 introduction The advanced-control timer TMR1 consists of a 16-bit counter supporting up, down or up/down counting modes, four capture/compare registers, and four independent channels to achieve embedded dead-time, input capture and programmable PWM output. 14.6.2 TMR1 main features ...

  • Page 257: Figure 14-92 Count Clock

    AT32F421 Series Reference Manual Figure 14-92 Count clock Encoder mode (SMSEL=3'b001/010/011) CK_INT(form CRM) CI1FP1/CI2FP2 STIS[1:0] External clock mode A (SMSEL=3'b111) STIS[2] Internal trigger DIV_counter CK_CNT CNT_counter STIS[1:0] TRGIN C1INC C1IFP1 polarity edge External trigger External clock mode B detector C2IPF2 (ECMBEN=1) TMRx_EXT ESDIV...

  • Page 258: Figure 14-94 Block Diagram Of External Clock Mode A

    AT32F421 Series Reference Manual When TMRx_EXT is selected as the TRGIN, configure the external signal polarity (by setting the ESP bit in the TMRx_STCTRL register), external signal division (by setting the ESDIV[1:0] bit in the TMRx_STCTRL register) and external signal filter (by setting the ESF[3:0] bit in the TMRx_STCTRL register).

  • Page 259: Figure 14-96 Block Diagram Of External Clock Mode B

    AT32F421 Series Reference Manual Figure 14-96 Block diagram of external clock mode B Note: The delay is present between the signal on the input side and the actual clock of the counter due to the synchronization circuit. Figure 14-97 Counting in external clock mode B, with PR=0x32 and DIV=0x0 TMR_CLK CNT_CLK COUNTER...

  • Page 260: Counting Mode

    AT32F421 Series Reference Manual Figure 14-98 Counter timing with prescaler value changing from 1 to 4 TMR_CLK CK_CNT COUNTER DIV[15：0] PR[15：0] OVFIF Clear 14.6.3.2 Counting mode The advanced-control timer consists of a 16-bit counter supporting up, down, up/down counting modes. The TMRx_PR register is used to configure the counting period.

  • Page 261: Figure 14-100 Overflow Event When Prben=0

    AT32F421 Series Reference Manual Figure 14-100 Overflow event when PRBEN=0 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Figure 14-101 Overflow event when PRBEN=1 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Downcounting mode Set CMSEL[1:0]=2’b00 and OWCDIR=1’b1 in the TMRx_CTRL1 register to enable the downcounting mode.

  • Page 262: Figure 14-103 Counter Timing Diagram With Internal Clock Divided By 1 And Tmrx_Pr=0X32

    AT32F421 Series Reference Manual Figure 14-103 Counter timing diagram with internal clock divided by 1 and TMRx_PR=0x32 TMR_CLK COUNTER PR[15:0] DIV[15:0] TWCMSEL [1：0] OVFIF Clear Clear Clear Repetition counter mode: The TMRx_RPR register is used to configure the counting period of repetition counter. The repletion counter mode is enabled when the repetition counter value is not equal to 0.

  • Page 263: Figure 14-105 Encoder Mode Structure

    AT32F421 Series Reference Manual Encoder interface mode To enable the encoder interface mode, write SMSEL[2: 0]= 3’b001/3’b010/3’b011. In this mode, the two inputs (C1IN/C2IN) are required. Depending on the level on one input, the counter counts up or down on the edge of the other input. The OWCDIR bit indicates the direction of the counter. Figure 14-105 Encoder mode structure SMSEL=3'b001/010/011 encoder mode...

  • Page 264: Tmr Input Function

    AT32F421 Series Reference Manual High Down Down Count on both C1IN and C2IN Down Down Figure 14-106 Example of encoder interface mode C CI1RAW CI2RAW COUNTER TWCMSEL [1:0] 14.6.3.3 TMR input function The TMR1 has four independent channels. Each channel can be configured as input or output. As input, each channel input signal is processed as below: –...

  • Page 265: Figure 14-108 Channel 1 Input Stage

    AT32F421 Series Reference Manual Figure 14-108 Channel 1 input stage STIS edge detector C1INC input divider STCI C1IPS C1P/C1CP C1IDIV C1EN CNT counter Capture C1DT C1IFP1 C1IN C2IFP1 TMRx_CH3 C1INSEL C1SWTR C1IF TMRx_CH2 C1IRAW C1DF TMRx_CH1 filter C2IRAW C2DF C2IF C2P/C2CP filter edge detector...

  • Page 266: Tmr Output Function

    AT32F421 Series Reference Manual PWM input mode configuration Figure 14-109 C1C(2'b01) edge detector STCI C1P=0 C1DF C1IRAW C1IF C1IFP1(pos) C1IN C1EN Capture C1DT Capture trigger C1CP=0 filter C2IFP1 (CH1 period) SMSEL(3'b110) STIS(3'b101) Trigger mode C1INC Hang CNT counter mode reset Reset mode Encoder...

  • Page 267: Figure 14-112 Output Stage For Channel 4

    AT32F421 Series Reference Manual Figure 14-112 Output stage for channel 4 Output mode CNT_value controller Polarity CNT_value=C4DT Output enable selection Compare TMRx_CM2 C4ORAW CNT_value>C4DT C4EN C4OUT C4DT To the master mode controller Output mode Write CxC[2: 0]≠2’b00 to configure the channel as output to implement multiple output modes. In this case, the counter value is compared with the value in the TMR1_CxDT register, and the intermediate signal CxORAW is generated according to the output mode selected by CxOCTRL[2: 0], which is sent to IO after being processed by the output control circuit.

  • Page 268: Figure 14-113 C1Oraw Toggles When Counter Value Matches The C1Dt Value

    AT32F421 Series Reference Manual gives an example of the combination between upcounting mode and PWM mode A. Figure 14-114 The output signal behaves when PR=0x32 but CxDT is configured with a different value. gives an example of the combination between up/down counting mode and PWM mode Figure 14-115 A.

  • Page 269: Figure 14-116 One-Pulse Mode

    AT32F421 Series Reference Manual Figure 14-116 One-pulse mode COUNTER PR[15：0] C1DT[15：0] TRGIN C1ORAW C1OUT Master timer event output When TMR is selected as the master timer, the following signal sources can be selected as TRGOUT signal to output to the salve timer, by setting the PTOS bit in the TMRxCTRL2 register. PTOS=3’b000, TRGOUT outputs software overflow event (OVFSWTR bit in the TMRx_SWEVT register).

  • Page 270: Tmr Brake Function

    AT32F421 Series Reference Manual After the dead-time insertion, the rising edge of the CxOUT is delayed compared to the rising edge of the reference signal; the rising edge of the CxCOU is delayed compared to the falling edge of the reference signal.

  • Page 271: Tmr Synchronization

    AT32F421 Series Reference Manual  If the brake interrupt or DMA request is enabled, the brake statue flag is set, and a brake interrupt or DMA request can be generated.  If AOEN=1, the OEN bit is automatically set again at the next overflow event. Note: When the brake input is active, the OEN cannot be set, nor the status flag, BRKIF can be cleared.

  • Page 272: Debug Mode

    AT32F421 Series Reference Manual can be generated when OVFS=0. Figure 14-121 Example of reset mode TMR_CLK COUNTER PR[15:0] DIV[15:0] STIS[2：0] SMSEL[2：0] CI1F1 OVFIF TRGIF Slave mode: Suspend mode In this mode, the counter is controlled by a selected trigger input. The counter starts counting when the trigger input is high and stops as soon as the trigger input is low.

  • Page 273: Tmr1 Registers

    AT32F421 Series Reference Manual counting by setting the TMR1_PAUSE in the DEBUG module. 14.6.4 TMR1 registers These peripheral registers must be accessed by word (32 bits). TMR1 register are mapped into a 16-bit addressable space. Table 14-16 TMR1 register map and reset value Register Offset Reset value...
  • Page 274 AT32F421 Series Reference Manual counts up / down One-way count direction Bit 4 OWCDIR 0: Up 1: Down One cycle mode enable This bit is use to select whether to stop counting at an Bit 3 OCMEN update event 0: The counter does not stop at an update event 1: The counter stops at an update event Overflow event source This bit is used to select overflow event or DMA request...

  • Page 275: Tmr1 Control Register2 (Tmr1_Ctrl2)

    AT32F421 Series Reference Manual 14.6.4.2 TMR1 control register2 (TMR1_CTRL2) Register Reset value Type Description Bit 15 Reserved resd Kept at its default value. Bit 14 C4IOS Channel 4 idle output state Bit 13 C3CIOS Channel 3 complementary idle output state Bit 12 C3IOS Channel 3 idle output state...

  • Page 276: Tmr1 Dma/Interrupt Enable Register (Tmr1_Iden)

    AT32F421 Series Reference Manual 11: Divided by 8 External signal filter This field is used to filter an external signal. The external signal can be sampled only after it has been generated N times 0000: No filter, sampling by f ������...
  • Page 277 AT32F421 Series Reference Manual HALL DMA request enable Bit 13 HALLDE 0: Disabled 1: Enabled Channel 4 DMA request enable Bit 12 C4DEN 0: Disabled 1: Enabled Channel 3 DMA request enable Bit 11 C3DEN 0: Disabled 1: Enabled Channel 2 DMA request enable Bit 10 C2DEN 0: Disabled...

  • Page 278: Tmr1 Interrupt Status Register (Tmr1_Ists)

    AT32F421 Series Reference Manual 14.6.4.5 TMR1 interrupt status register (TMR1_ISTS) Register Reset value Type Description Bit 15: 13 Reserved resd Kept at its default value. Channel 4 recapture flag C4RF rw0c Bit 12 Please refer to C1RF description. Channel 3 recapture flag C3RF rw0c Bit 11...

  • Page 279: Tmr1 Software Event Register (Tmr1_Swevt)

    AT32F421 Series Reference Manual 14.6.4.6 TMR1 software event register (TMR1_SWEVT) Register Reset value Type Description Bit 15: 8 Reserved 0x00 resd Kept at its default value. Brake event triggered by software This bit is set by software to generate a brake event. Bit 7 BRKSWTR 0: No effect...
  • Page 280 AT32F421 Series Reference Manual 000: Disconnected. C1ORAW is disconnected from C1OUT; 001: C1ORAW is high when TMR1_CVAL=TMR1_C1DT 010: C1ORAW is low when TMR1_CVAL=TMR1_C1DT 011: Switch C1ORAW level when TMR1_CVAL=TMR1_C1DT 100: C1ORAW is forced low 101: C1ORAW is forced high. 110: PWM mode A －OWCDIR=0, C1ORAW is high once TMR1_C1DT>TMR1_CVAL, else low;...

  • Page 281: Tmr1 Channel Mode Register2 (Tmr1_Cm2)

    AT32F421 Series Reference Manual 0000: No filter, sampling is done at f ������ 1000: f /8, N=6 ���������������� ������ 0001: f , N=2 ���������������� ����_������ 1001: f /8, N=8 ���������������� ������ 0010: f , N=4 ���������������� ����_������ 1010: f /16, N=5 ����������������...

  • Page 282: Tmr1 Channel Control Register (Tmr1_Cctrl)

    AT32F421 Series Reference Manual This field is used to define the direction of the channel 1 (input or output), and the selection of input pin when C3EN=’0’: 00: Output 01: Input, C3IN is mapped on C3IFP3 10: Input, C3IN is mapped on C4IFP3 11: Input, C3IN is mapped on STCI.

  • Page 283: Table 14-17 Complementary Output Channel Cxout And Cxcout Control Bits With Brake Function

    AT32F421 Series Reference Manual When the channel 1 is configured as output mode: 0: C1OUT is active high 1: C1OUT is active low When the channel 1 is configured as input mode: 0: C1IN active edge is on its rising edge. When used as external trigger, C1IN is not inverted.

  • Page 284: Tmr1 Counter Value (Tmr1_Cval)

    AT32F421 Series Reference Manual CxIOS and CxCIOS do not correspond to CxOUT and CxCOUT active level. Note: If the two outputs of a channel are not used (CxEN = CxCEN = 0), CxIOS, CxCIOS, CxP and CxCP must be cleared. Note: The state of the external I/O pins connected to the complementary CxOUT and CxCOUT channels depends on the CxOUT and CxCOUT channel state and the GPIO and the IOMUX registers.

  • Page 285: Tmr1 Channel 3 Data Register (Tmr1_C3Dt)

    AT32F421 Series Reference Manual 14.6.4.16 TMR1 channel 3 data register (TMR1_C3DT) Register Reset value Type Description Channel 3 data register When the channel 3 is configured as input mode: The C3DT is the CVAL value stored by the last channel 3 input event (C1IN) Bit 15: 0 C3DT...

  • Page 286: Tmr1 Dma Control Register (Tmr1_Dmactrl)

    AT32F421 Series Reference Manual TMR1_BRK: DTC, BRKEN, BRKV and AOEN TMR1_CTRL2: CxIOS and CxCIOS 10: Write protection level 2. The following bits and all bits in level 3 are write protected: TMR1_CCTRL: CxP and CxCP TMR1_BRK: FCSODIS and FCSOEN 11: Write protection level 1. The following bits and all bits in level 2 are write protected: TMR1_CMx: C2OCTRL and C2OBEN Note: Once WPC>0, its content remains frozen until the...

  • Page 287: Window Watchdog Timer (Wwdt)

    AT32F421 Series Reference Manual 15 Window watchdog timer (WWDT) 15.1 WWDT introduction The window watchdog downcounter must be reloaded in a limited time window to prevent the watchdog circuits from generating a system reset. The window watch dog is used to detect the occurrence of system malfunctions.

  • Page 288: Debug Mode

    AT32F421 Series Reference Manual Table 15-1 Minimum and maximum timeout value when PCLK1=72 MHz Prescaler Min. Timeout value Max. Timeout value 56.5μs 3.64ms 113.5μs 7.28ms 227.5μs 14.56ms 455μs 29.12ms Figure 15-2 Window watchdog timing diagram CNT[6：0] 55 54 52 51 50 4F 4E 4D 4C 4B 4A 41 40 3F 55...

  • Page 289: Configuration Register (Wwdt_Cfg)

    AT32F421 Series Reference Manual 15.5.2 Configuration register (WWDT_CFG) Register Reset value Type Description Bit 31: 10 Reserved 0x000000 resd Kept at its default value. Reload counter interrupt Bit 9 RLDIEN 0: Disabled 1: Enabled Clock division value 00: PCLK1 divided by 4096 Bit 8: 7 01: PCLK1 divided by 8192 10: PCLK1 divided by 16384...

  • Page 290: Watchdog Timer (Wdt)

    AT32F421 Series Reference Manual 16 Watchdog timer (WDT) 16.1 WDT introduction The WDT is driven by a dedicated low-speed clock (LICK). Due to the lower clock accuracy of LICK, the WDT is best suited to the applications that have lower timing accuracy and can run independently outside the main application.

  • Page 291: Debug Mode

    AT32F421 Series Reference Manual Table 16-1 WDT timeout period (LICK=40kHz) Min.timeout (ms) Max. timeout (ms) Prescaler divider DIV[2: 0] bits RLD[11: 0] = 0x000 RLD[11: 0] = 0xFFF 409.6 819.2 1638.4 3276.8 6553.6 /128 13107.2 /256 (6 or 7) 26214.4 16.4 Debug mode When the microcontroller enters debug mode (Cortex -M4 core halted), the WDT counter stops...

  • Page 292: Reload Register (Wdt_Rld)

    AT32F421 Series Reference Manual 16.5.3 Reload register (WDT_RLD) (Reset in Standby mode) Register Reset value Type Description Bit 31: 12 Reserved 0x00000 resd Kept at its default value. Reload value The write protection must be unlocked in order to enable Bit 11: 0 0xFFF write access to the register.

  • Page 293: Enhanced Real-Time Clock (Ertc)

    AT32F421 Series Reference Manual 17 Enhanced real-time clock (ERTC) 17.1 ERTC introduction The real-time clock provides a calendar clock function. The time and date can be modified by modifying the ERTC_TIME and ERTC_DATE register. The ERTC module is in battery powered domain, which means that it keeps running and free from the influence of system reset and VDD power off as long as VBAT is powered.

  • Page 294: Ertc Initialization

    AT32F421 Series Reference Manual The ck_a is used for subsecond update, while the ck_b is used for calendar update and periodic autowakeup. The clock frequency of ck_a and ck_b can be obtained from the following equation: ck_a ck_b To obtain ck_b with frequency of 1 Hz, DIVA=127, DIVB=255, and 32.768 kHz LEXT should be used. This ck_b is then used for calendar update.
  • Page 295 AT32F421 Series Reference Manual 1. Set the IMEN =1 to enter initialization mode 2. Wait until the initialization flag INITF bit is set 3. Configure DIVB and DIVA. 4. Configure the clock and calendar values. 5. Leave the initialization mode by clearing the IMEN bit. Wait until the UPDF bit is set, indicating the completion of the calendar update.

  • Page 296: Ertc Calibration

    AT32F421 Series Reference Manual the DIVB value is at least equal to 3. 17.3.3 ERTC calibration Smooth digital calibration: Smooth digital calibration has a higher and well-distributed performance than the coarse digital calibration. The calibration is performed by increasing or decreasing ERTC_CLK in an evenly manner. The smooth digital calibration period is around 2 ERTC_CLK (32 seconds) when the ERTC_CLK is 32.768 kHz.

  • Page 297: Tamper Detection

    AT32F421 Series Reference Manual 17.3.5 Tamper detection The ERTC offers one tamper detection mode: TAMP1. It can be configured as a level detection with filter or edge detection. TAMP1 is mapped onto the tamper pin ERTC_MUX1. The TP1F will be set when a valid tamper event is detected. An interrupt will also be generated if a tamper detection interrupt is enabled.

  • Page 298: Ertc Registers

    AT32F421 Series Reference Manual Table 17-2 ERTC low-power mode wakeup Wake Clock sources Events Wake up Sleep Wakeup Standby Deepsleep Alarm clock A √ × × HEXT Time stamp √ × × Tamper event √ × × Alarm clock A √...

  • Page 299: Ertc Date Register (Ertc_Date)

    AT32F421 Series Reference Manual Bit 21: 20 Hour tens Bit 19: 16 Hour units Bit 15 Reserved resd Kept at its default value. Bit 14: 12 Minute tens Bit 11: 8 Minute units Bit 7 Reserved resd Kept at its default value. Bit 6: 4 Second tens Bit 3: 0...

  • Page 300: Ertc Initialization And Status Register (Ertc_Sts)

    AT32F421 Series Reference Manual 0: No effect 1: Add 1 hour Note: The next second takes effect when this bit is set (don’t set this bit when the hour is being incremented) Timestamp interrupt enable Bit 15 TSIEN 0: Timestamp interrupt disabled 1: Timestamp interrupt enabled Bit 14: 13 Reserved...

  • Page 301: Ertc Divider Register (Ertc_Div)

    AT32F421 Series Reference Manual TSF. Note: The clearing operation of this bit takes effect after two APB_CLK cycles. Bit 10: 9 Reserved resd Kept at its default value. Alarm clock A flag 0: No alarm clock event Bit 8 ALAF rw0c 1: Alarm clock event occurs Note: The clearing operation of this bit takes effect after...

  • Page 302: Ertc Write Protection Register (Ertc_Wp)

    AT32F421 Series Reference Manual 0: No hour mask 1: Alarm clock doesn’t care about hours AM/PM 0: AM Bit 22 AMPM 1: PM Note: This bit is applicable for 12-hour format only. It is 0 for 24-hour format. Bit 21: 20 Hour tens Bit 19: 16 Hour units...

  • Page 303: Ertc Time Stamp Date Register (Ertc_Tsdt)

    AT32F421 Series Reference Manual Bit 15 Reserved resd Kept at its default value Bit 14: 12 MT Minute tens Bit 11: 8 MU Minute units Bit 7 Reserved resd Kept at its default value Bit 6: 4 Second tens Bit 3: 0 Second units Note: The content of this register is valid only when the TSF is set in the ERTC_STS register.
  • Page 304 AT32F421 Series Reference Manual 1: Push-pull output Bit 17: 16 Reserved resd Kept at its default value Tamper detection pull-up Bit 15 TPPU 0: Tamper detection pull-up enabled 1: Tamper detection pull-up disabled Tamper detection pre-charge time 0: 1 ERTC_CLK cycle Bit 14: 13 TPPR 1: 2 ERTC_CLK cycles...

  • Page 305: Ertc Alarm Clock A Subsecond Register (Ertc_Alasbs)

    AT32F421 Series Reference Manual 17.4.15 ERTC alarm clock A subsecond register (ERTC_ ALASBS) Register Reset value Type Description Bit 31: 28 Reserved resd Kept at its default value Sub-second mask 0: No comparison. Alarm A doesn’t care about subseconds. 1: SBS[0] is compared 2: SBS[1: 0] are compared Bit 27: 24 SBSMSK 3: SBS[2: 0] are compared...

  • Page 306: Analog-To-Digital Converter (Adc)

    AT32F421 Series Reference Manual 18 Analog-to-digital converter (ADC) 18.1 ADC introduction The ADC is a peripheral that converts an analog input signal into a 12-bit digital signal. Its sampling rate is as high as 2 MSPS. It has up to 18 channels for sampling and conversion. 18.2 ADC main features In terms of analog: ...

  • Page 307: Adc Functional Overview

    AT32F421 Series Reference Manual Figure 18-1 ADC1 block diagram ADCDIV OCTESEL ADC prescaler PCLK2 ADCCLK TMR1_CH1 TMR1_CH2 OCTEN TMR1_CH3 TMR3_TRGOUT TMR15_CH1 EXINT11 ADC_IN0 OCSWTRG Trigger ADC_IN1 detection GPIO Ordinary ADC_IN14 conversion start Temp.sensor INTRV Channel manegement Ordinary Analog-to- channels V DDA digital V SSA converter...

  • Page 308: Internal Temperature Sensor

    AT32F421 Series Reference Manual channel conversion is interrupted, giving the priority to the preempted channel, and the ordinary channel continues its conversion at the end of the preempted channel conversion. If the ordinary channel trigger occurs during the preempted channel conversion, the ordinary channel conversion won’t start until the end of the preempted channel conversion.

  • Page 309: Trigger

    AT32F421 Series Reference Manual Calibration After power-on, enable ADC calibration by setting the ADCAL bit in the ADC_CTRL2 register. When the calibration is complete, the ADCAL bit is cleared by hardware and the conversion is started by software trigger. After each calibration, the calibration value is stored in ADC_ODT register, and then value is automatically sent back to the ADC so as to eliminate capacitance errors.

  • Page 310: Sampling And Conversion Sequence

    AT32F421 Series Reference Manual 18.4.2.3 Sampling and conversion sequence The sampling period can be configured by setting the CSPTx bit in the ADC_SPT1 and ADC_SPT2 registers. A single one conversion time is calculated with the following formula: A single one conversion tiem ( ADCCLK cycle ) = sampling time + 12.5 Example: If the CSPTx selects 1.5 cycles, then one conversion needs 1.5+12.5=14 ADCCLK cycles If the CSPTx selects 7.5 cycles, then one conversion needs 7.5+12.5=20 ADCCLK cycles.

  • Page 311: Repetition Mode

    AT32F421 Series Reference Manual Figure 18-5 Preempted group auto conversion mode Sampling OCLEN=2, OSN1=ADC_IN5, OSN2=ADC_IN0, OSN3=ADC_IN5 Conversion PCLEN=1, PSN3=ADC_IN14, PSN4=ADC_IN1 Ordinary channel trigger ADC_IN5 ADC_IN0 ADC_IN5 ADC_IN14 ADC_IN1 CCE and CCE flag set PCCE flag set 18.4.3.3 Repetition mode The repetition mode is enabled by setting the RPEN bit in the ADC_CTRL2 register. When a trigger signal is detected, the ordinary channels will be converted repeatedly.

  • Page 312: Data Management

    AT32F421 Series Reference Manual Figure 18-7 Partition mode OCLEN=4, OCPCNT=1, OSN1=ADC_IN5, OSN2=ADC_IN0, OSN3=ADC_IN2, OSN4=ADC_IN1, OSN5=ADC_IN7 Ordinary channel Ordinary channel Ordinary channel Ordinary channel trigger trigger trigger trigger ADC_IN5 ADC_IN0 ADC_IN2 ADC_IN1 ADC_IN7 ADC_IN5 ADC_IN0 CCE flag set CCE flag set CCE flag set CCE flag set PCLEN=2, PSN2=ADC_IN14, PSN3=ADC_IN1, PSN4=ADC_IN13...

  • Page 313: Voltage Monitoring

    AT32F421 Series Reference Manual 18.4.5 Voltage monitoring The OCVMEN bit or PCVMEN bit in the ADC_CTRL1 register is used to enable voltage monitoring based on the converted data. The VMOR bit will be set if the converted result is outside the high threshold (ADC_VMHB register) or less than the low threshold (ADC_VMLB register).

  • Page 314: Adc Status Register (Adc_Sts)

    AT32F421 Series Reference Manual 18.5.1 ADC status register (ADC_STS) Accessible by words. Register Reset value Type Description Bit 31: 5 Reserved 0x0000000 resd Kept at its default value. Ordinary channel conversion start flag This bit is set by hardware and cleared by software (writing 0).

  • Page 315: Adc Control Register2 (Adc_Ctrl2)

    AT32F421 Series Reference Manual partitioned mode on ordinary channels. 0: Partitioned mode disabled on ordinary channels 1: Partitioned mode enabled on ordinary channels Preempted group automatic conversion enable after ordinary group Bit 10 PCAUTOEN 0: Preempted group automatic conversion disabled 1: Preempted group automatic conversion enabled Voltage monitoring enable on a single channel 0: Disabled (Voltage monitoring enabled on all channels)
  • Page 316 AT32F421 Series Reference Manual 1: Enabled Trigger event select for ordinary channels conversion 000: Timer 1 CH1 event 001: Timer 1 CH2 event 010: Timer 1 CH3 event Bit 19: 17 OCTESEL 011: Unused. Do not configure. 100: Timer 3 TRGOUT event 101: Timer 15 CH1 event 111: OCSWTRG Kept at its default value...

  • Page 317: Adc Sampling Time Register 1 (Adc_Spt1)

    AT32F421 Series Reference Manual Note: When this bit is in OFF state, write a start command can wake up The ADC from power-down mode. When this bit is in ON state, write a start command repeatedly while the other bits of the register remain unchanged will start a regular group conversion.

  • Page 318: Adc Sampling Time Register 2 (Adc_Spt2)

    AT32F421 Series Reference Manual 011: 28.5 cycles 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles Sample time selection of channel ADC_IN12 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles Bit 8: 6 CSPT12 100: 41.5 cycles 101: 55.5 cycles...
  • Page 319 AT32F421 Series Reference Manual 110: 71.5 cycles 111: 239.5 cycles Sample time selection of channel ADC_IN7 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles Bit 23: 21 CSPT7 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles Sample time selection of channel ADC_IN6 000: 1.5 cycles...

  • Page 320: Adc Voltage Monitor High Threshold Register (Adc_Vwhb)

    AT32F421 Series Reference Manual 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles Sample time selection of channel ADC_IN1 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles Bit 5: 3 CSPT1 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles Sample time selection of channel ADC_IN0...

  • Page 321: Adc Ordinary Sequence Register 1 (Adc_ Osq1)

    AT32F421 Series Reference Manual 18.5.9 ADC ordinary sequence register 1 ( ADC_ OSQ1) Accessible by words. Register Reset value Type Description Bit 31: 24 Reserved 0x00 resd Kept at its default value Ordinary conversion sequence length 0000: 1 conversion 0001: 2 conversions Bit 23: 20 OCLEN ……...

  • Page 322: Adc Preempted Sequence Register (Adc_ Psq)

    AT32F421 Series Reference Manual 18.5.12 ADC preempted sequence register ( ADC_ PSQ) Accessible by words. Register Reset value Type Description Bit 31: 30 Reserved resd Kept at its default value Preempted conversion sequence length 00: 1 conversion 01: 2 conversions Bit 21: 20 PCLEN 10: 3 conversions...

  • Page 323: Comparator (Comp)

    AT32F421 Series Reference Manual 19 Comparator (COMP) 19.1 COMP introduction AT32F421 embeds an ultra-low-power comparator (CMP). They can be used for various purposes, such as, external analog signal monitor/control and wakeup from low-power mode, and working with other timers for pulse width measurement and PWM signal control. Figure 19-1 Block Diagram of Comparator Analog Digital...

  • Page 324: Design Tips

    AT32F421 Series Reference Manual 19.4 Design tips The following information can be used for design reference:  Input/Output configuration As a comparator input, the I/Os must be configured as an analog mode. The comparator output can be remapped onto external I/Os. Comparator output configuration: Multiplexed GPIOA_MUXL[3:0]=0111...

  • Page 325: Glitch Filter

    AT32F421 Series Reference Manual 19.5.2 Glitch filter The interference filter can be used to filter glitches and noise. The sensitivity of the filter is controlled by the H_PULSE_CNT and L_PULSE_CNT bits. The sensitivity of the filter affects the number of the same consecutive sampling. The level change of a certain signal would not be regarded as valid before the consecutive sampling is detected on the filter input.

  • Page 326: Comparator Control And Status Register 1 (Comp_Ctrlsts)

    AT32F421 Series Reference Manual 19.6.1 Comparator control and status register 1 (COMP_CTRLSTS) Register Reset value Type Description Comparator write protected This bit can be written only once. It is set by software and cleared by system reset. It will latch all the contents Bit 31 CMPWP rw0c...

  • Page 327: Glitch Filter Enable Register (G_Filter_En)

    AT32F421 Series Reference Manual 100: PA4 101: PA5 110: PA0 111: PA2 Comparator speed selection This bit is used to control the operating mode of the comparator in order to adjust speed and power consumption. Bit 3: 2 CMPSSEL 00: High speed/maximum power consumption 01: Medium speed/medium power consumption 10: Low speed/low power consumption 11: Ultra-low speed/ ultra-low power consumption...

  • Page 328: Glitch Filter Low Pulse Count (Low-Pulse)

    AT32F421 Series Reference Manual 19.6.4 Glitch filter low pulse count (LOW-PULSE) Register Reset value Type Description Bit 15: 6 Reserved 0x000 resd Kept at its default value. Low pulse Count level of the filter input signal must wait H_PULSE_CNT+1 cycles before becoming active input, so that the output can turn low level.

  • Page 329: Operational Amplifer (Opa)

    AT32F421 Series Reference Manual 20 Operational amplifier (OPA) The operational amplifier (OPA) applies to the AT32F421 series. 20.1 Introduction The device embeds two rail-to-rail OPAs with up to 6 MHz bandwidth and an offset less than 4.5mV. 20.2 Main features ...
  • Page 330 AT32F421 Series Reference Manual Location relationship between device pins and OPA pins Pin name OPA pin OP1_INP OP1_INM OP1_OUT OP2_INP OP2_INM OP2_OUT 2022.11.11 Page 330 Rev 2.02...

  • Page 331: Infrared Timer (Irtmr)

    AT32F421 Series Reference Manual 21 Infrared timer (IRTMR) The IRTMR (Infrared Timer) is used to generate the IR_OUT signal that drives the infrared LED so as to achieve infrared control. The IR_OUT signals consists of a low-frequency modulation envelope and high-frequency carrier signals. The low-frequency modulation envelope signal selects from TMR16_C1OUT, USART1 and USART2 through the IR_SRC_SEL[1: 0] bit in the SCFG_CFG1 register, while the high-frequency carrier signal is provided by the TMR17_C1OUT register.

  • Page 332: Debug (Debug)

    AT32F421 Series Reference Manual 22 Debug (DEBUG) 22.1 Debug introduction Cortex™-M4 core provides powerful debugging features including halt and single step support, as well as trace function that is used for checking the details of the program execution. The debug features are implemented with a serial wire debug interface.

  • Page 333: Debug Device Id (Debug_Idcode)

    SW debug port or by the user code. Register Reset value Type Description Bit 31: 0 PID 0xXXXX XXXX ro PID information PID [31: 0] AT32 part number FLASH size Packages 0x50020100 AT32F421C8T7 64KB LQFP48 0x50020101 AT32F421K8T7 64KB LQFP32 0x50020102 AT32F421K8U7 64KB QFN32 (5x5) 0x50020103 AT32F421K8U7-4...

  • Page 334: Debug Control Register (Debug_Ctrl)

    AT32F421 Series Reference Manual 22.4.2 DEBUG control register (DEBUG_CTRL) This register is asynchronously reset by POR Reset (not reset by system reset). It can be written by the debugger under reset. Register Reset value Type Description Kept at its default value. Bit 31: 28 Reserved 0x0000...
  • Page 335 AT32F421 Series Reference Manual mode 1: The whole 1.2V digital circuit is not unpowered in Standby mode, and the system clock is provided by the internal RC oscillator (HICK) Debug Deepsleep mode control bit 0: In Deepsleep mode, all clocks in the 1.2V domain are disabled.

  • Page 336: Revision History

    AT32F421 Series Reference Manual 23 Revision history Document Revision History Date Version Revision Note Initial release. 2021.11.17 2.00 1. Updated the descriptions in Section 1.1.5 Reset 2. Updated the descriptions in 3.6 Power saving modes 3.Updated the descriptions in 4.3.2 Clock configuration register (CRM_CFG) 2022.06.27 2.01...
  • Page 337 No license, express or implied, to any intellectual property right is granted by ARTERY herein regardless of the existence of any previous representation in any forms. If any part of this document involves third party’s products or services, it does NOT imply that ARTERY authorizes the use of the third party’s products or services, or permits any of the intellectual property, or guarantees any uses of the third party’s products or services...

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