Rf Layout On Four-Layer Pcb - Espressif Systems ESP32 Hardware Design Manuallines

Chapter 4. PCB Layout Design
• Ensure a complete GND plane for the RF, crystal, and chip.
• The crystal should be placed far from the clock pin to avoid interference on the chip. The gap should be at least
2.7 mm. It is good practice to add high-density ground vias stitching around the clock trace for better isolation.
• There should be no vias for the clock input and output traces, which means the traces cannot cross layers. The
clock traces should not intersect with each other.
• Components in series to the crystal trace should be placed close to the chip side.
• The external matching capacitors should be placed on the two sides of the crystal, preferably at the end of the
clock trace, but not connected directly to the series components. This is to make sure the ground pad of the
capacitor is close to that of the crystal.
• Do not route high-frequency digital signal traces under the crystal. It is best not to route any signal trace under
the crystal. The vias on the power traces on both sides of the crystal clock trace should be placed as far away
from the clock trace as possible, and the two sides of the clock trace should be surrounded by grounding copper.
• As the crystal is a sensitive component, do not place any magnetic components nearby that may cause interfer-
ence, for example large inductance component, and ensure that there is a clean large-area ground plane around
the crystal.
4.5 RF

4.5.1 RF Layout on Four-layer PCB

The RF trace is routed as shown highlighted in pink in Figure
The RF layout should meet the following guidelines:
• A π-type matching circuit should be added to the RF trace and placed close to the chip, in a zigzag.
• The RF trace should have a 50 Ω characteristic impedance. The reference plane is the second layer. For
designing the RF trace at 50 Ω impedance, you could refer to the PCB stack-up design shown below.
• Add a stub to the ground at the ground pad of the first matching capacitor to suppress the second harmonics.
It is preferable to keep the stub length 15 mil, and determine the stub width according to the PCB stack-up so
that the characteristic impedance of the stub is 100 Ω ± 10%. In addition, please connect the stub via to the
third layer, and maintain a keep-out area on the first and second layers. The trace highlighted in Figure
Stub in a Four-layer PCB Design
• The RF trace should have a consistent width and not branch out. It should be as short as possible with dense
ground vias around for interference shielding.
• The RF trace should be routed on the outer layer without vias, i.e., should not cross layers. The RF trace should
be routed at a 135° angle, or with circular arcs if trace bends are required.
• The ground plane on the adjacent layer needs to be complete. Do not route any traces under the RF trace
whenever possible.
• There should be no high-frequency signal traces routed close to the RF trace. The RF antenna should be
placed away from high-frequency components, such as crystals, DDR SDRAM, high-frequency clocks, etc. In
Espressif Systems
Fig. 7: ESP32 RF Layout in a Four-layer PCB Design
is the stub. Note that a stub is not required for package types above 0201.
26
Submit Document Feedback
ESP32 RF Layout in a Four-layer PCB Design.
ESP32
Release master