Rf Layout On Two-Layer Pcb; Flash And Psram; External Rc - Espressif Systems ESP32 Hardware Design Manuallines

Chapter 4. PCB Layout Design
addition, the USB port, USB-to-serial chip, UART signal lines (including traces, vias, test points, header pins,
etc.) must be as far away from the antenna as possible. The UART signal line should be surrounded by ground
copper and ground vias.

4.5.2 RF Layout on Two-layer PCB

In a two-layer PCB design, the RF trace is routed as shown highlighted in pink in Figure
layer PCB Design. The width of the RF trace should be greater than that of the RF trace in a four-layer board and
is normally over 20 mil. The actual width depends on the impedance formula where impedance-relevant parameters
may vary depending on the number of PCB layers.
Other good practices for routing RF traces in four-layer PCB designs still apply to two-layer board designs.

4.6 Flash and PSRAM

The layout for flash and PSRAM should follow the guidelines below:
• Place the zero-ohm series resistors on the SPI lines close to the chip.
• Route the SPI traces on the inner layer (e.g., the third layer) whenever possible, and add ground copper and
ground vias around the clock and data traces of SPI separately.
• Place the 0.1 μF capacitor to ground at the VDD_SPI close to corresponding flash and PSRAM power pins.
Figure ESP32 Flash and PSRAM Layout

4.7 External RC

External resistors and capacitors should be placed close to the chip pins, and there should be no vias around the traces.
Please ensure that 10 nF capacitors are placed close to the pins.
Espressif Systems
Fig. 10: ESP32 RF Layout in a Two-layer PCB Design
shows an example of flash (U3) and PSRAM (U4) layout.
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