Receive Go Flag - Texas Instruments 990 Maintenance Manual

~,
_ _ _ _ _ _ _
~
945408-9701
4.2.12.4 Read Request Interrupt Logic. The read request interrupt logic consists of a 4-bit
binary counter and two flip-flops. During initialization, the output flip-flop is reset. During
normal operation the logic is reset by ADDS 12-. If the data terminal ready latch is set and
ADDS12- is high when STPRCK- from the receive go latch goes low, the read request interrupt
logic output flip-flop is set after a delay of one-half bit time (10-bit code) or one and one-half
bit time (11-bit code). When reset, the read request interrupt logic produces an interrupt to the
device (if the interrupt mask latch is not set) and provides its status to the computer via the
multiplexer.
4.2.12.5 New Status Flag. The new status flag is made up of a flip-flop with an AND gate at
each input (data and clock). The flag is set whenever Data Carrier Detect (DCDE) on the device
input interface changes state or when Data Set Ready (DSRE) on that same interface goes low.
The flag is reset whenever the data terminal ready latch is reset or when ADDS 13- is low. When
the new status flag is set, NSTFG- provides an interrupt to the device (if the interrupt mask
latch is not set).
4.2.12.6 Interrupt Mask Latch. The interrupt mask latch is a flip-flop whose output is used to
disable the CRUINT- signal to the computer. This latch is set during initialization by DTRA, or
during normal operation by ADDS 14-. When the interrupt mask latch is set, MASKINT- disables
CRU Interrupt (CRUINT-). When reset, MASKINT- enables the interrupt merging logic.
4.2.12.7 Diagnostic Mode Latch. The diagnostic mode latch is a flip-flop that controls the
operation of the diagnostic loop logic. The latch is set during initialization by DTRA, and is set
and reset during normal operation by ADDS 15-. When the diagnostic mode latch is set, DIAGM
gates DSR-, DCD-, RCVD, and RCR- through diagnostic loop logic to the multiplexer and gates
RTS, XMTD, DTR-, and RTS- to the EIA line drivers. When reset, the diagnostic mode latch
gates DTR-, RTS-, XMTD, and RTS to the multiplexer and sends ones to the EIA line drivers.
4.2.12.8 Interrupt Merging Logic. Interrupt merging logic consists of three gates which perform
the OR function for Write Request (WRQ-), Read Request (RRQ-), and New Status (NSTFG-)
when the module is being used with an EIA device and the interrupt mask latch is reset.
4.2.13 RECEIVE SHIFf CLOCK GENERATOR. The receive shift clock generator consists of a
4-bit binary counter and four gates that produce, from DAT ACLK, Receive Shift Clock
(RSCLK), a clock signal with a pulse width equal to that of DATACLK and a period 16 times as
long as DATACLK's. The frequency of RSCLK is equal to the receive baud rate, and the active
pulse is delayed by one-half bit time from the time the generator begins to count DATACLK.
The receive shift clock generator is active when the receive go latch is set and data is being
received from a peripheral device. The receive shift clock generator clocks the receive bit
counter, the receive go latch, and the receive shift register.
4.2.14 RECEIVE BIT COUNTER. The receive bit counter consists of a 4-bit binary counter and
two gates that are used to stop the Receive Shift Clock (RSCLK) from clocking data from the
device into the receive shift register. Whenever RCVDE from the device is low, the receive shift
clock generator and receive bit counter are activated. After one-half bit time, the receive bit
counter sets the receive go flag (RSCLKA) allowing the receive shift clock generator and receive
bit counter to remain active independently of RCVDE. After counting 10 or 11 RSCLKA pulses,
the receive bit counter disables the receive go flag and terminates the operation for that
character.
4.2.15 RECEIVE GO FLAG. The receive go flag is made up of the circuitry shown in figure
4-4. Whenever RCVDDI (RCVDE from the device) is low, RCVEN is high and activates the
receive shift clock generator and the receive bit counter. Upon receipt of RSTOPA- (11-bit code)
25
Digital Systems Division