Input Operation; Error Detection; Block Diagram Description; Address Decoder - Texas Instruments 990 Maintenance Manual

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945408-9701
Address:
Decoder . . . . . . . . .
Module . . . . . . . . .
Addressable Input/Output Lines
. . . 4.2.3
. . . . 1.5
. F3-1, F4-6,
F4-7
Asynchronous (Start/Stop) Data Transmission
Formats . . . . . . . . . . . . . . . .F 1-3
Baud Rate Clock:
Description . . . . . .
Logic Diagram . . . . . .
C~ock, Sign~ls..
.:.... ·,..,. ,.:T; .
Baua Race Se1ecnon, uA
I
ALLK
Bit Counter:
Receive . .
Transmit
Block Diagram:
Description
Simplified .
Detailed Functional
Buff er Register, Receive
Character Format
Characteristics:
Electrical .
Physical . . .
Clock:
Baud Rate . . . .
Logic Diagram, Baud Rate
Signals, Baud Rate
Computer Hot Mock-Up System:
Model 990/10
Model 990/4
Condition:
Mark
Space . . .
Configurations, Jumper
Considerations, Timing
CRUBIT, 12-15 Signal
CRUDATAIN
CRUDATAOUT
CRUINT- . . . . .
Current Loop Interface
Data Carrier Detect (DCDE)
Data Reception . . . . . .
Data Set Ready (DSRE) . .
Data Terminal Ready (DTRE)
Data Terminal Ready Latch
Data Transmission Formats .
DAT ACLK Baud Rate Selection
Decoder, Address . . . . . . . .
Decoder Output For CRUBIT, 12-15
Detailed Functional Block Diagram
Detailed Interface Discussion . . .
Detect (PDCD) Signal, Pseudo Data
Carrier . . . . .
Detection, Error . . . . . . . .
Diagnostic Loop Logic . . . . . .
Diagnostic Mode Latch . . . . . .
Diagram, Transmit Shift Register Signals
Timing . . . . . . . . .
Documents, Related . . . . . . . . .
4.2.2
.F4-2
.T5-2
.T4-1
. 4.2.14
4.2.7
. 4.2
.Fl-2
.F4-1
.4.2.20
. 1.2.4
.1.4. Tl-1
. 1.3
4.2.2
.F4-2
.T5-2
.F5-2
.F5-1
1.2.2
1.2.2
.T2-1
3.2.2
.4.3.1.2
. .4.3.1.6
.4.3.1.1
.4.3.1.7
. 4.2.9
.4.3.3.8
. 4.4.4
. 4.3.3.10
. .4.3.3.2
. 4.2.12.1
4.4.2
.T4-1
4.2.3
.T4-2
.F4-1
. 4.3
.4.3.3.6
. 3.2.5
.4.2.10
. 4.2.12.7
. . F5-6
. Preface
46
Echo Character . . . . . . .
Echo Character Sample Routine
EIA:
Line Drivers . . . .
Line Receivers . . .
Electrical Characteristics
Equipment Overview
Error Detection
Flags:
New Status
Receive Go
Thning Error
Transmit Go
Write Request
.3.2.6.1
. . F3-4
. 4.2.11
. 4.2.17
.1.4, Tl-1
. 1.2
. . 3.2.5
. 4.2.12.5
. . 4.2.15
. . 4.2.22
. . 4.2.5
. 4.2.12.3
Format, Character . . . . . . . . . .
Formats, Asynchronous (Start/Stop) Data
Transmission . . . . . .
1.2.4
.Fl-3
Gating Logic, Transmit Shift
General Description . .
1/0 Reset Signal, TILINE
IMODSELA- . . . . .
Input Character Transfer
Input:
Addressable Lines
Operation . . . . .
Status Signals
Inspection And Preparation For
Installation
Installation . .
Instructions:
Multiple Bit
Operating
Single Bit
Interface:
Current Loop
Diagram . . .
Discussion . . .
Module-To-Current Loop Device
Module-To-EIA Device
Interrupt Logic:
Read Request
Status And
Interrupt Mask Latch
Interrupt Merging Logic
Interrupt Response
Interrupts . . . . .
Jumper Configurations
Jumper Schedule
Latches:
Data Terminal Ready
Diagnostic Mode
Interrupt Mask . . .
Logic Diagram, Receive Go
Request To Send
Line Drivers
Line Receivers
Lines, Addressable:
Input . . . . .
4.2.4
.Section I
. 4.3.5
.4.3.1.3
.F3-3
.F4-6
3.2.4
T3-2
. 2.3
. 2.4
1.2.3
. Section III
1.2.3
4.2.9
. . Fl-2, F4-5
. 4.3
. . . 4.3.2
. . 4.3.3
. 4.2.12.4
. . 4.2.12
. 4.2.12.6
. 4.2.12.8
. . 1.2.3
.3.2.1, 4.4.3
.T2-1
.T2-1
. 4.2.12.1
. 4.2.12.7
. 4.2.12.6
. . . F4-4
. 4.2.12..2
. 4.2.11
. 4.2.17
. . F4-6
Digital Systems Division