Texas Instruments 990 Maintenance Manual page 31

~-------
~
945408-9701
DTRA
XMSRIN= 1+CRUDATAOUT
A QA
QB
8 QC
164
QD
QE
QF
QG
K
QH
D
p
XMSRCLK=XSCLK+STORECLK
74
K
Q
XSCLK
CL
XMTD
XMTGO
SETGO-
(A)133020
Figure 4-3. Transmit Shift Register Logic
4.2.12 STATUS AND INTERRUPT WGIC. Combinational logic and several latches on the
module provide status and interrupt information to the computer. The following paragraphs
discuss that circuitry.
4.2.12.1 Data Terminal Ready Latch. The data terminal ready latch is a flip-flop that is reset by
TILINE I/O Reset (TILORES-) from the 990 during the computer's power-up sequence or by a
RSET instruction from the computer. When the data terminal ready latch is reset, it disables data
transfer through the module. The data terminal ready flag is also reset whenever bit 9 of the CRU
output word is logic 0 and the CRU address bits (CRUBIT, 12-15) are set to 1001
2
(ADDS9-
=
0).
When the latch is set, it drives Data Terminal Ready (DTRE) high and enables the remainder of the
module's circuitry for data transfer.
4.2.12.2 Request To Send Latch. The request to send latch is a flip-flop used to control the
Request To Send (RTSE) signal to the peripheral device. During initialization, the request to
send latch is set by the data terminal ready latch (DTRA) and drives RTSE low. During
preparation to send data from the computer to the peripheral device, ADDS 10- resets this latch
and drives RTSE high.
4.2.12.3 Write Request Flag. The write request flag is a flip-flop used to produce an interrupt
and a status signal. The flag is set whenever STPXCK- from the transmit bit counter is low
signifying the end of a transmitted character, and reset by DTRA during initialization or by
ADDS 11-. When the write request flag is set while in use with an EIA device and the interrupt
mask latch is not set, an interrupt is sent to the device, and the write request flag notifies the
computer of its status via the multiplexer.
24
Digital Systems Division