Timing Considerations; Output Operation - Texas Instruments 990 Maintenance Manual

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When the interrupt signal is recognized by the computer and the interrupt occurs at a level less than
or equal to the interrupt level in the computer status register, then the following actions occur:
I. The new workspace pointer and program-counter contents are fetched from memory
locations determined by the interrupt level.
2. The current workspace pointer, program-counter and status-register contents are stored in
workspace registers 13, 14 and 15 of the new workspace.
3. The new status register contents are set to inhibit interrupts of lower priority than the
level of the interrupt.
4. The interrupt processing routine is entered at the address specified by the new program
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The interrupt-processing routine determines which module generated the interrupt by interrogating
bit F
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of all modules corresponding to the interrupt level until it finds an active interrupt bit. The
program then examines input bits B (Write Request), C (Read Request), D (Data Carrier Detect),
and E (Data Set Ready) of that module to determine the condition that caused the interrupt, and
the routine must clear the interrupt condition by generating an output (either a I or a 0) to the ap-
plicable address bit.
3.2.2 TIMING CONSIDERATIONS. When data is being transferred to the CPU, a timing error
can occur if the program does not store a received character into memory before a new character
is received. When such an overrun occurs, CRU input bit 9 (TIMERR) from the module sets to
flag the condition. This bit clears automatically when the read request interrupt logic is reset.
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Timing is not critical when data is being transferred from the CPU. However, efficient use of the
communication line requires that the next character to be transmitted be presented to the
interface within one bit time following the Writer Request interrupt. The time interval, in seconds,
between characters for a particular format and baud rate is given by the number of bits per charac-
ter (including start and stop bits) divided by the baud rate. The reciprocal of this character time is
the character rate. The interval between bits (bit time) is the reciprocal of the baud rate.
3.2.3 OUTPUT OPERATION. A character may be output from the computer to the module using
an 8-bit Load CR (LDCR) instruction. Any of the addressing modes of the 990 Computer may be
used. The direct-addressing mode is of the form:
LDCR @CHAR, 8
This instruction results in an 8-bit transfer from memory location CHAR to the current CRU
base address starting with bit 0 and incremented through bit 7. Figure 3-2 illustrates this
transfer. Initiating this sequence starts data transmission from the module when the entire 8-bit
character is present in the module. The data is sent serially on the communication line.
During the transfer operation, CRU bit 8 (Transmit in Progress) remains true; it resets when the
character has been completely transmitted and Write Request (bit B) has been set. A new
character output to the module must not be started until Transmit in Progress drops and Write
Request sets, Outputs to clear intem1pt bits reset independently of the output data lines.
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Digital Systems Division