Texas Instruments 990 Maintenance Manual page 36

~-------
~
945408-9701
(A)133023A
CPU TO MODULE MEMORY WORD
9
(DATA TRANSFER
IS SERIAL)
TRUE DATA
1
=
ON~
O= OFF
1
=
ON~
O= OFF
BIT VALUE DON'T CARE {
1
=
ON~
0= OFF
1
=
ON~
O= OFF
MODULE INTERNAL BIT ADDRESS
2
3
CHARACTER TO BE
4
TRANSMITTED
5
6
8 NOT USED
9 DTR (DATA TERMINAL READY) C
A RTS (REQUEST TO SEND)
0
B CLRWRQ (CLEAR WRITE REQUEST) M
C CLRRRQ (CLEAR READ REQUEST) M
D CLRNSF (CLEAR NEW STATUS FLAG) A
E ENABLE INTERRUPTS N
F DIAGNOSTIC MODE D
Figure 4-6. Full Duplex ITY /EIA Module Addressable Input Lines
4.3.1.3 IMODSELA-. IMODSELA- is the address module select of a CRU chassis slot.
IMODSELA- is wired into the computer backpanel and addressed by software. IMODSELA- is a
low-active signal that enables the module to send and receive information between the computer
and a peripheral device.
4.3.1.4 STORECLK-. STORECLK- is a low-active pulse from the computer that indicates to the
module that the operation is a write operation (SETB or LDCR). STORECLK- transfers the data
on CRUDATAOUT to the module serially.
4.3.1.5 TLIORES-. TLIORES- is the TILINE 1/0 reset signal. It is low-active and is generated
either by an RSET instruction or during the computer's power-up sequence.
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Digital Systems Division