Texas Instruments 990 Maintenance Manual page 26

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945408-9701
SECTION IV
THEORY OF OPERATION
4.1 GENERAL
This section contains a detailed block diagram description of the Full Duplex TTY /EIA Module,
describes the module's interfaces with the Model 990 Computer and a peripheral device, and
provides a discussion of the module's operation.
4.2 BLOCK DIAGRAM DESCRIPTION
Figure 4-1 is a detailed functional block diagram of the Full Duplex TTY /EIA module. The
following discussion is based on figure 4-1.
4.2.1 4-MHz OSCILLATOR. The 4-MHz crystal-controlled oscillator produces a square wave
(OSCLK) whenever power is applied to the module. The oscillator's output is used by the baud
rate clock to produce DATACLK, the basis for all the timing signals on the module.
4.2.2 BAUD RA TE CLOCK. The baud rate clock consists of three cascaded 4-bit binary
counters as shown in figure 4-2. The first counter is preset to count from 3 through 15 .and
divides the frequency of OSCLK by 13. A jumper connecting either E20 or E22 to E21 presets
the second counter to count from 0 through 15 (E20 to E21 ; divides the frequency of
MOD13CRY by 16) or from 5 through 15 (E22 to E21; divides the frequency of MOD13CRY
by 11). The E22-to-E21 jumper plug produces a 110-baud output at E2, while connecting E20 to
E2 l enables outputs of 75, 300, 1200, 2400, 4800, and 9600 baud at E2 through E7. The third
counter is preset to count from 0 through 15 to frequency-divide MODI lCRY by 16 and produce
the 7 5- and 300-baud signals at E2 and E3, respectively.
A jumper plug connecting E 1 A or E 1 B to one of E2 through E7 selects the frequency of
DAT ACLK according to the schedule given in table 4-1. The baud-rate clock is active as long as
power is applied to the module.
4.2.3 ADDRESS DECODER. The address decoder examines bits 12 through 15 of the 12-bit
CRU address word from the 990 to -decode seven signals ((ADDS,9-15)-) to control status and
interrupt latches on the module. Table 4-2 shows the outputs generated by the address decoder
for the CRUBIT,12-15 combinations with bit 12 equal to logic I. For CRUBIT,12-15 combina-
tions with bit 12 equal to logic 0, all address decoder outputs are held at logic l (inactive). Each
address decoder output is a low-active pulse having the same pulse width as STORECLK-. Table
4-2 also lists the action caused by the address decoder outputs.
4.2.4 TRANSMIT SHIFf GATING LOGIC. Transmit shift gating logic consists of several gates
and inverters whose function is to provide the transmit shift generator with data and clock
inputs during data transmission from the computer to the device attached to the module.
Transmit shift gating logic provides the serial data from the computer (CRUDAT AOUT) to the
transmit shift register as XMSRTN whenever the transmit go flag is reset. If the transmit go flag
is set, the input to the transmit shift register is held at logic l. The clock signal provided to the
transmit shift register (XMSRCLK) is either Transmit Shift Clock (XSCLK) from the transmit
shift clock generator or Store Clock (STORECLK-) from the computer. If the transmit go flag is
set, XMSRCLK is equivalent to XSCLK. If the transmit go flag is reset, bit 12 of the CRU
address word (CRUBIT,12-15) is logic 0, and the module has been selected (CRUSELO
=
l)
XMSRCLK is equivalent to STORECLK- inverted.
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Digital Systems Division