Block Diagram - Pepperl+Fuchs AVS78E Manual

Singleturn absolute encoder
Connection
Signal
Ground wire
GND (rotary encoder)
+U (rotary encoder)
b
Pulse (+)
Pulse (-)
Data (+)
Data (-)
Preset
Counting direction
Interface
Description
The Synchronous Serial Interface was specially developed for transferring the output data of an absolute encoder to a control
device. The control module sends a clock bundle and the absolute encoder responds with the position value.
Thus only 4 lines are required for the clock and data, no matter what the resolution of the rotary encoder is. The RS 422 interface
is optically isolated from the power supply.
SSI signal course Standard
Clock +
D
Data +
n
MSB
D , ..., D
1
S:
MSB:
LSB:
SSI output format Standard
• At idle status signal lines "Data +" and "Clock +" are at high level (5 V).
• The first time the clock signal switches from high to low, the data transfer in which the current information (position data (D
and special bit (S)) is stored in the encoder is introduced.
• The highest order bit (MSB) is applied to the serial data output of the encoder with the first rising pulse edge.
• The next successive lower order bit is transferred with each following rising pulse edge.
• After the lowest order bit (LSB) has been transferred the data line switches to low until the monoflop time T
• No subsequent data transfer can be started until the data line switches to high again or the time for the clock pause T
expired.
• After the clock sequence is complete, the monoflop time T
• The monoflop time T
m
SSI output format ring slide operation (multiple transmission)
• In ring slide operation, multiple transmission of the same data word over the SSI interface makes it possible to offer the
possibility of detecting transmission errors.
• In multiple transmission, 25 bits are transferred per data word in standard format.
• If the clock change is not interrupted after the last falling pulse edge, ring slide operation automatically becomes active. This
means that the information that was stored at the time of the first clock change is generated again.
• After the first transmission, the 26
the monoflop time T , a new current data word will be transmitted with the following pulses.
m
If the pulse line is exchanged, the data word is generated offset.
Ring slide operation is possible up to max. 13 bits.

Block diagram

Refer to "General Notes Relating to Pepperl+Fuchs Product Information".
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Cable
green-yellow
1
2
3
4
5
6
7
8
T
D D D
n-1 n-2
: Position data
n
Special bit
Most significant bit
Least significant bit
determines the lowest transmission frequency.
th
pulse controls data repetition. If the 26
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Terminal compartment
Grounding terminal
1
2
5
6
8
7
4
3
D D
n-3 2 1
T = 1/f:
T
m
T
p
is triggered with the last falling pulse edge.
m
th
pulse follows after an amount of time greater than
Line length
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T
p
T
m
S
LSB
Duration of period of clock signal
Monoflop time 10 s ... 30 s
:

: Clock pause monoflop time (T
AVS78E Mining
1 2 3 4 5 6 7 8

1 MHz

T
)
p m
)
n
has expired.
m
has
p
5