Logic Analyzer Connector J13 Pin Assignments - Motorola M68MPB16Z3 User Manual

MEVB SUPPORT INFORMATION
Table 4-6. Logic Analyzer Connector J12 Pin Assignments (continued)
Pin
17
18
19
20
Table 4-7. Logic Analyzer Connector J13 Pin Assignments
Pin
1
2
3
4
5
6
7
4-6
Mnemonic
SIZ0 TRANSFER SIZE – Output signal that indicate the
number of bytes still to be transferred during this cycle.
R/W READ/WRITE – Output signal that indicates the
direction of data transfer on the bus.
BGACK / BUS GRANT ACKNOWLEDGE – Active-low input
signal that indicates an external device has assumed
bus mastership.
CS2 CHIP SELECT 2 – Output signal that selects peripheral
or memory devices at programmed addresses.
GND GROUND
Mnemonic
+5V +5 VDC POWER – Input voltage (+5Vdc @ 1.0 A) used
by the MEVB logic circuits. (To make this pin a no
connection, remove the jumper from jumper header
W21 on the MPFB.)
SPARE No connection
DSACK1 DATA AND SIZE ACKNOWLEDGE 1 – Active-low
input signal that allows asynchronous data transfers
and dynamic bus sizing between the MCU and external
devices.
AVEC AUTOVECTOR – Active-low input signal that requests
an automatic vector during interrupt acknowledge.
HALT HALT – Active-low input/output signal that suspends
external bus activity, to request a retry when used with
BERR, or for single-step operation.
AS ADDRESS STROBE – Active-low output signal that
indicates a valid address is on the address bus.
DS DATA STROBE – Active-low output signal. During a
read cycle, indicates that an external device should
place valid data on the data bus. During a write cycle,
indicates that valid data is on the data bus.
Signal
Signal
M68MPB16Z3UM/D