Xycom XVME-500 Manual page 50

lXVME-500/590 Manual
February, 1988
9
Bit 6
0
0
1
1
Single Channel
Sequential Channel
Random Channel
External Trigger
The use of input conversion modes is explained in greater detail in Section 3.4.1
D 4 This bit provides a means for a module software reset. If
"toggled" to logic 'l', then back to logic '0', a software reset
will occur (in bits D7 and D2)
D 3 A logic '1' written to this location will enable the module to
generate VMEbus interrupts (if the associated jumpers are set
appropriately; see Section 2.5.3)
D 2 This bit is an 'interrupt-pending' flag.
says an A/D conversion has been completed. The interrupt-pending
bit can be cleared in one of three ways:
Dl & D0: These bits are not used by the XVME-500/590 s t a t u s / c o n t r o l
register.
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Table 3-2. Input Mode Options
Mode Bits
Bit 5
0
1
0
1
Starts conversion process when reading lower 8 bits
Channels are converted in a sequence, beginning
with a specific number; starts conversion process
when reading lower 8 bits
Starts conversion after channel number is written
to Gain Channel register (in read mode; see Table
2-6)
Starts conversion on positive trigger signal
received on Pin 50 (ground reference on Pin 49) of
of connector JKl (see Figure 3-6 for timing)
Causing a new A/D conversion (see bit D7)
1)
Performing backplane or software reset (see bit D4)
2)
Reading the converted input data from the lower order
3)
data byte
A/D Conversion Mode
Single
Sequential
Random
External Trigger
Logic '1' at this location
3-5
Channel
Channel
Channel